The MIPS Instruction Set

Transcription

1 The MIPS Instruction Set MIPS is a Reduced Instruction Set Computer (RISC), Characterized By: It is a Load-Store Machine. Computation Is Done On Data In Registers, i.e., Operands of Arithmetic And Logical Operations Do Not Reside In Memory. Data Is Moved Between Memory And Registers Before Being Used and Back To Memory After Computation Is Finished By Load and Store Instructions A Relatively Small Number Of Instructions and Data Types All Instructions Are Of The Same Length There Are A Very Small Number Of Instruction Formats (3) There Are A Small Number Of Addressing Modes - Three For Accessing Operands (Register-Direct, Based, Immediate) and One For Computing Jump Addresses (PC-Relative) Courtesy D. Rennels Set 2 ( 1-30 ) M. Louie - v.11

2 MIPS R2000 / R3000 ISA Programmable Storage: Byte Addressable R0 R1 R Addresses 2 30 Memory Words; 1 Word = 4 Bytes Bit General Purpose Registers - R1 - R31 General Purpose - Register 0 = Constant Value 0 PC = Program Counter Register R31 PC LO HI F0 F2 F4 F1 F3 F5 F30 Single Precision Double Precision F31 Set 2 ( 2-30 ) M. Louie - v.11

3 MIPS R2000/R3000 ISA (Floating Point) 32 Floating Point Registers (F0-F31) - Double Precision = 16 FP Register Pairs - Single Precision = 16 FP Registers (Even Addresses) HI,LO Registers for 64-Bit Integer Arithmetic Results - HI,LO = 64-Bit Integer Product (Multiplication) - LO=Quotient, HI=Remainder (Division) Set 2 ( 3-30 ) M. Louie - v.11

4 MIPS Instruction Formats R-Type Instructions OP RS RT RD Shamt Func 6 Bits 5 Bits 5 Bits 5 Bits 5 Bits 6 Bits Here is the meaning of each field name in the MIPS instructions: - OP: Operation of the instruction - RS: The First Register Source Operand - RT: The Second Register Source Operand - RD: The Register Destination Operand; it gets the result of the operation - SHAMT: Shift Amount (This term is explained in Chapter 4; You will not need it until then) - Func: Function; This field selects the variant of the operation in the OP Field For convenience we will express values of fields as decimal digits Patterson & Hennessy Set 2 ( 4-30 ) M. Louie - v.11

5 MIPS Instruction Formats I-Type Instructions OP RS RT Address 6 Bits 5 Bits 5 Bits 16 Bits Immediate Addressing Format - addi, ori, andi Data Transfer Instructions - lw, sw Conditional Branch - beq, bne. Patterson & Hennessy Set 2 ( 5-30 ) M. Louie - v.11

6 MIPS Addressing Modes Instruction Formats Register (direct) OP RS RT RD Register Immediate OP RS RT Immed Base + Index OP RS RT Immed Register Memory PC-Relative OP RS RT Immed PC Memory Courtesy D. Patterson Set 2 ( 6-30 ) M. Louie - v.11

7 Four Basic MIPS Instructions MIPS Assembly Language Category Instruction Example Meaning Comments Arithmetic Add add $1,$2,$3 $1=$2+$3 3 Ops Data in Reg Subtract sub $1,$2,$3 $1=$2-$3 3 Ops Data in Reg Data Transfer Load Word lw $1,100($2) $1=Memory[$2+100] Data from Mem to Reg Store Word sw $1,100($2) Memory[$2+100]=$1 Data from Reg to Mem Patterson & Hennessy Set 2 ( 7-30 ) M. Louie - v.11

8 Four Basic MIPS Instructions MIPS Machine Language Name Fmt Example add R add $1,$2,$3 sub R sub $1,$2,$3 lw I lw $1,100($2) sw I sw $1,100($2) Field Size 6 bits 5 bits 5 bits 5 bits 5bits 6 bits All Instructions 32 Bits Fmt R R op rs rt rd shamt func Arithmetic Instruction Fmt Fmt I I op rs rt Address Data Transfer Fmt Patterson & Hennessy Set 2 ( 8-30 ) M. Louie - v.11

9 Assembly and Machine Language Programs for a Simple Example A[i] = h + A[i]; is compiled into: lw $8,Astart($19) # Temporary reg $8 gets A[i] add $8,$18,$8 # Temporary reg $8 gets h + A[i] sw $8,Astart($19) # Stores h + A[i] back into A[i] op rs rt (rd) (shamt) address/ func Patterson & Hennessy Set 2 ( 9-30 ) M. Louie - v.11

10 Multiply / Divide Start Multiply, Divide - MULT rs, rt - MULTU rs, rt - DIV rs, rt - DIVU rs,rt Registers Move Result From Multiply, Divide - MFHI rd - MFLO rd Move To HI or LO - MTHI rd - MTLO rd HI LO Courtesy D. Patterson Set 2 ( ) M. Louie - v.11

11 Immediate Addressing in MIPS Example: - The add instruction that has one constant operand is called add immediate or addi. To add 4 to reg. 29, with result in reg. 28: addi $28,$29,4 # $28 = $ What is the Corresponding MIPS Machine Code Answer: - The Instruction Is The Following Machine Code (Using Decimal # s): OP RS RT Immediate In Binary It Is: Patterson & Hennessy Set 2 ( ) M. Louie - v.11

12 Adding The Conditional Branch and Jump Instructions Compare Two Registers and If Condition is Met, Goto Label L Category Instruction Example Meaning Comments Conditional Branch branch on equal beq $1,$2,L if $1 == $2 goto L Equal Test and Branch branch on not equal bne $1,$2,L if $1!= $2 goto L Not Equal Test and Branch set on less than slt $1,$2,$3 if $2<$3 $1=1 else $1=0 Compare for less than; set register with result. Used with beq/bne for branch on less than Unconditional Jump jump j L goto L jump to target address jump register jr $31 goto $31 for switch and procedure return Patterson & Hennessy Set 2 ( ) M. Louie - v.11

13 MIPS jump, branch, compare Instructions Examples: Let Label L be at a word offset F from PC+4 Instruction Example Meaning Comments branch on equal beq $1,$2,L if $1==$2 goto PC+4+(F*4) Equal Test; PC relative branch on not eq bne $1,$2,L if $1!= $2 goto PC+4+(F*4) Not Equal Test; PC relative set on less than slt $1,$2,$3 if $2<$3 $1=1 else $1=0 Compare less than, 2 s comp set less than imm. slti $1,$2,100 if $2<100 $1=1 else $1=0 Compare < constant, 2 s comp set less than uns. sltu $1,$2,$3 if $2<$3 $1=1 else $1=0 Compare less than, natural no. set l.t. imm. uns. sltiu $1,$2,100 if $2<100 $1=1 else $1=0 Compare < constant, natural jump j L goto L Jump to target address jump register jr $31 goto $31 For switch, procedure return jump and link jal L $31=PC+4, goto L For procedure call Courtesy D. Patterson Set 2 ( ) M. Louie - v.11

14 Branch Instructions are PC Relative For branches/jumps, 16-bit Address Field is a word offset to Label L For branches, PC <- PC (Address Field)*4. For jumps, (Address Field)*4 replaces the lower bits of (PC+4) (e.g., let PC=16 and Label L at address 100). Name Fmt Example Comments beq I beq $1,$2,L bne I bne $1,$2,L slt R slt $1,$2,$3 j J 2 25 j L jr R jr $31 Field Size 6 bits 5 bits 5 bits 5 bits 5bits 6 bits All Instructions 32 Bits Fmt R R op rs rt rd shamt func Arithmetic Fmt Fmt I I op rs rt Address Data Transfer Fmt, branch Fmt Patterson & Hennessy Set 2 ( ) M. Louie - v.11

15 A Coding Example with Conditional Branches Example: - In the following C code segment, f,g,h,i, and j are variables: if (i == j) goto L1; f = g + h; L1: f = f - i; - Assuming that the five variables correspond to five registers $16 through $20, what is the compiled MIPS code? Answer: - The Compiled Program (Assembly Code) is: beq $19,$20,L1 # goto L1 if i equals j add $16,$17,$18 # f = g + h L1:sub $16,$16,$19 # f = f - i What would the machine code look like for this? Patterson & Hennessy Set 2 ( ) M. Louie - v.11

16 Another C Compilation Example C Code: Loop:g = g + A[i]; i = i+ j; if (i!= h) goto Loop; Assembly Code: Loop:mult $19,$10 # (HI,LO) regs = i*4 mflo $9 # reg $9 = least sig. 32 product bits lw $8,Astart($9)# Temporary reg $8 = A[i] add $17,$17,$8 # g = g + A[i] add $19,$19,$20 # i = i + j bne $19,$18,Loop # goto Loop if i!= h Patterson & Hennessy Set 2 ( ) M. Louie - v.11

17 An Example Using a Case Statement C Code: switch (k) { case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3; f = i - j; break; } The following MIPS assembly language will work, provided four words in memory, starting at location JumpTable, have addresses corresponding to the labels L0,L1,L2, and L3 respectively. Since we are using the variable k to index into this array of words, we must first multiply by 4 to turn k into its byte address equivalent. Loop: mult $10,$21 # (HI,LO) regs = k*4 mflo $9 # Temp reg $9 = least sig. 32 product bits lw $8,JumpTable($9) # Temp reg $8 = Jumptable[k] jr $8 # Jump based on register $8 L0: add $16,$19,$20 # k=0 so f gets i+j j Exit L1: add $16,$17,$18 # k=1 so f gets g+h j Exit L2: sub $16,$17,$18 # k=2 so f gets g-h j Exit L3: sub $16,$19,$20 # k=3 so f gets i-j Exit: Patterson & Hennessy Set 2 ( ) M. Louie - v.11

18 Why are Stacks So Great? Stacking of Procedure Calls & Returns and Environments A CALL B B CALL C C A A B A B C RET RET RET A A B Some Machines Provide a Memory Stack as Part of the Architecture Sometimes Stacks are Implemented via Software Convention (e.g., MIPS) Courtesy D. Patterson Set 2 ( ) M. Louie - v.11

19 Call-Return Linkage: Stack Frames HIMEM ARGS Callee Save Regs (old FP, RA) Local Variables FP Reference Args and Local Vars at Fixed (negative) Offset From FP SP LOMEM Grows and shrinks during expression evalution Many Variations on Stacks Possible (up/down, last pushed / next) Courtesy D. Patterson Set 2 ( ) M. Louie - v.11

20 Definitions for MIPS Procedure Call Convention Stack Frame -- A block of memory on the stack for the procedure call environment. Purpose: - Holds values passed as arguments to the procedure - Store values that the calling procedure needs after the callee returns - Provides storage space for local variables Caller-Saved Registers -- Registers 8-15, 24, and 25. Assumed temporary values that the callee can overwrite without restoring before returning Callee-Saved Registers -- Registers Assumed long-lived values that the callee can overwrite but must restore before returning Reserved Registers -- Registers 1, 26, and 27. Strictly used by the operating system and assembler. Not to be used by user programs or compilers Global Register -- Register 28. Pointer to a program s static data Argument Registers -- Registers 4-7. For passing proc. call arguments Stack Pointer -- Register 29. Pointer to last allocated word on the stack Set 2 ( ) M. Louie - v.11

21 MIPS Procedure Call Convention Before the caller makes the procedure call, the caller: 1.1 Pushes onto the stack caller-saved register values and argument register values that the caller wants to use after the callee returns 1.2 Stores procedure call arguments in regs. 4-7 and pushes any remaining arguments onto the stack for the callee stack frame When the procedure is invoked, the callee then: 2.1 Allocates memory on the stack for its stack frame 2.2 Saves environment registers (e.g. reg. 31: return addr., and reg. 30: frame pointer) and callee-saved registers onto the stack so that the callee can alter them and then restore them before returning 2.3 Updates the frame pointer to point to the callee stack frame Just before the callee returns, the callee: 3.1 Puts return values in registers Restores regs. saved in Step 2.2 (above) and pops the stack frame Set 2 ( ) M. Louie - v.11

22 MIPS Uses a Jump and Link Instruction for Procedure Calls Category Instruction Example Meaning Comments Unconditional Jump jump j L goto L jump to target address jump register jr $31 goto $31 for switch statements jump and link jal L $31=PC+4, goto L for procedure call Name Fmt Example Comments jal J jal L (L s addr. =1000) PROG PROC PROC Save Reg Push PC+4 Save Reg Push PC+4 Save Reg Push PC+4 Courtesy D. Rennels Set 2 ( ) M. Louie - v.11

23 Details of the MIPS Instruction Set Register Zero always has the value Zero (even if you try to write to it) Jump/Link instr. puts the Return Addr PC+4 into the Link Register All instructions change all 32-bits of the destination register (including lui,lb,lh) and all read all 32-bits of sources (add,sub,and,or,...) Immediate Arithmetic and Logical Instructions are Extended as Follows: - Logical Immediates are Zero Extended to 32 Bits - Arithmetic Immediates are Sign Extended to 32 Bits The data loaded by the instruction lb and lh are extended as follows: - lbu,lhu are Zero Extended - lb,lh are Sign Extended Overflow can occur in these Arithmetic and Logical instructions: - add,sub,addl - It cannot occur in addu, subu, addiu, and, or,xor, nor, shifts, mult, multu, div, divu Courtesy D. Patterson Set 2 ( ) M. Louie - v.11

24 Complex Instruction Set Computers (CISC) - Multiple Length Instruction Formats - More Addressing Modes - Typical Memory Operands can be used in Arithmetic and Logical operations - An instruction may do several things (e.g., Test, Decrement, and Branch) The Reasons for this are historic - There were few registers in early machines, so a Load-Store Architecture would be Inefficient (Why?) - Memory was Expensive and Slow - Making special short instructions reduced memory bandwidth - Each instruction took several clock cycles so Compound Instructions could speed up programs Modern Technology caused the development of RISC machines: - More registers in the processor - Pipelining to execute one instruction every clock cycle - Cheaper Faster Memory Courtesy D. Rennels Set 2 ( ) M. Louie - v.11

25 IA-32 Intel Instruction Set Architecture IA-32: Intel s 32-bit instruction set architecture for the Pentium, P6 family (including Pentium Pro, Pentium II, Celeron, Pentium III), and Pentium 4 Software compatibility -- Applications written for the Pentium will also run on the Pentium 4 Newer Pentium generations improve hardware performance: - Pentium - 2 pipelines to execute up to 2 instructions per clock. Separate instruction and data caches; each 1 cache level. 32-bit registers but internal data paths of 128 and 256 bits for fast data transfers - Pentium Pro - Executes up to 3 instructions per clock. 2 cache levels - Pentium II - Enlarged instruction and data caches - Pentium III - New set of 128-bit registers - Pentium 4 - Significantly higher clock speeds. 144 new instructions for high performance arithmetic operations and memory management operations. High speed processor-memory bus. Hennessy & Patterson Set 2 ( ) M. Louie - v.11

26 Intel Pentium 4 32-bit Architecture Basic execution environment: - Basic program execution registers: 8 general purpose registers 6 segment registers Flags register, and Instruction Pointer register - Floating point unit (FPU) registers: 8 FPU data registers FPU control register, FPU status register, FPU instruction pointer, FPU operand pointer, FPU tag register, FPU opcode register - Eight 64-bit registers and eight 128-bit registers for high performance single-instruction, multiple-data stream operations - 5 control registers identify the current operating mode and characteristics of the currently executing task Set 2 ( ) M. Louie - v.11

27 Pentium 4 Memory Segment Segment = Logical unit of memory up to 4 GBytes of Contiguous Memory - For isolation of separate code, data, and stack modules in memory Segment Registers: Pointers to the base of 16 current segments Offset: Logical memory address location with respect to a segment base Address translation when using segments: - Segment base address + Offset = Logical linear memory address Segment Descriptors Linear Memory Segment Register Access Rights Segment Size Base Address Segment Logical Memory Address Offset Set 2 ( ) M. Louie - v.11

28 Pentium 4 Addressing Modes Instructions act on zero or more operands. Operands may be located in: - The Instruction itself (immediate operand) - Register - Memory location - I/O Port Memory Addressing Modes - Displacement (Absolute Address) - Base Register (Register Indirect) - Base Register + Displacement - (Index Register * Scale) + Displacement - Base Register + Index Register + Displacement) - Base Register + (Index Register * Scale) + Displacement Set 2 ( ) M. Louie - v.11

29 Some Pentium 4 Operations Over 330 Operations Some Control Operations JNZ Short-Label Jump if non-zero to target instruction CALL Target Subroutine Call-- save environment info & jump RET Pop return address from stack & jump LOOP Short-Label Loop Branch, Decrement CX reg., Jump if CX!=0 Some Data Transfer Operations CMOVcc Do a move operation if flags=specific state PUSH SOURCE Push operand onto stack & decrement stack ptr. POP SOURCE Pop operand from stack & increment stack ptr. Some Arithmetic and Logical Operations FSINCOS Sine & Cosine; operand & result on stack XADD DEST,SOURCE Exchange DEST/SOURCE values; DEST=DEST+SOURCE BSF DEST,SOURCE Find position of least-signif. 1-bit in SOURCE BOUND INDEX,LOWER,UPPER Checks if array INDEX is in LOWER/UPPER bounds Some Software Support Operations ENTER SIZE,NEST-LVL Create a procedure stack frame VERW SOURCE Check if SOURCE segment is accessible/writable Set 2 ( ) M. Louie - v.11

30 Pentium 4 General Instruction Format Instruction Prefixes Opcode ModR/M SIB Displacement Immediate Up to four prefixes of 1-byte each (optional) 1 or 2 byte opcode 1-byte (if required) 1-byte (if required) Address displacement of 1, 2, or 4 bytes (if required) Immediate data of 1, 2, or 4 bytes (if required) Mod Reg/ Opcode R/M Scale Index Base - Instruction format: 1 to 16 bytes in length - Mod: Addressing mode for operand in memory - Reg/Opcode: Register number or 3 more bits of opcode - R/M: Register number or combined with Mod for an addressing mode - SIB: For addressing modes requiring Scale, Index, or Base - Instruction prefixes: Override default segment, operand size or address size; Indicate probable result of a conditional branch; Cause an instruction to be repeated for an entire string Intel Set 2 ( ) M. Louie - v.11