CS 121 Digital Logic Design. Chapter 3
|
|
- Johnathan Berry
- 7 years ago
- Views:
Transcription
1 CS 121 Digital Logic Design Chapter 3 Gate-Level Minimization
2 Outline 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3.4 Product of sums simplification 3.5 Don t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function
3 3.1 Introduction (1-1) Gate-Level Minimization refers to the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit. Notes about simplification of Boolean expression: Minimum number of terms and literals in each term (minimum number of gates and inputs in the digram). Reduce the complexity of the digital gates. The simplest expression is not unique. Simplification Methods: Algebraic minimization lack on specific rules. (section 2.4). Karnaugh map or K-map.
4 3.2 The Map Method (1-12) A Karnaugh map is a graphical tool for assisting in the general simplification procedure. Combination of 2, 4, adjacent squares The relation is: Logic circuit Boolean function Truth table K- map conical form satndrad form. Conical form: ( sum of minterms, product of maxterms. Standrad form: ( simplifier : sum of product, product of sum
5 3.2 The Map Method (2-12) Two-variable maps: Y Y X X
6 3.2 The Map Method (3-12) Rules for K-map: o We can reduce functions by circling 1 s in the K- map o Each circle represents a minterm reduction o Following circling, we can deduce minimized andor form. Rules to consider o Every cell containing a 1 must be included at least once. o The largest possible power of 2 rectangle must be enclosed. o The 1 s must be enclosed in the smallest possible number of rectangles.
7 3.2 The Map Method (4-12) Two-Variable maps (cont.) Example 1: F(X,Y) = XY + XY From the map, we see that F (X,Y) = X. Note: There are implied 0s in other boxes. 1 1 X This can be justified using algebraic manipulations: F(X,Y) = XY + XY = X(Y +Y) = X.1 = X
8 3.2 The Map Method (5-12) Two-Variable maps (cont.) Example 2: G(x,y) = m1 + m2 + m3 Y G(x,y) = m1 + m2 + m3 = X Y + XY + XY From the map, we can see that : G = X + Y X
9 3.2 The Map Method (6-12) Two-Variable maps (cont.) Example 3: F = Σ(0, 1) Using algebraic manipulations: x y F F = Σ(0,1) = x y + x y = x (y+y ) = x 1 1 X
10 3.2 The Map Method (7-12) Three-variable maps: 3 variables 8 squares ( minterms). On a 3-variable K-Map: One square represents a minterm with three variables Two adjacent squares represent a product term with two variables Four adjacent terms represent a product term with one variables Eight adjacent terms is the function of all ones (logic 1).
11 3.2 The Map Method (8-12) Three-variable maps (cont.): Example 1: F(X,Y) = X Y Z + X YZ + XY Z + XYZ Y Z using algebraic manipulations: F = X Y Z + X YZ + XY Z + XYZ = Z (X Y + X Y + XY + XY) = Z (X (Y +Y) + X (Y +Y)) = Z (X + X) = Z x
12 3.2 The Map Method (9-12) three-variable maps (cont.) Example 2: F=AB C +AB C +ABC +ABC + A B C + A BC From the map, we see that F=A+B C +BC A 0 1 B C
13 3.2 The Map Method (10-12) three-variable maps (cont.) Example 4 : F (x, y, z)= Σm (2, 3, 6, 7) using algebraic manipulations: F(x, y, z) = x yz + xyz + x yz + xyz = yz (x + x) + yz (x + x) = yz + yz = y (z + z ) = y x 0 1 y z Y
14 3.2 The Map Method (11-12) three-variable maps (cont.) Example (3-1), (3-2) :
15 3.2 The Map Method (12-12) three-variable maps (cont.) Example (3-3), (3-4) :
16 3.3 Four-Variables Map (1-9) 4 variables 16 squares ( minterms). On a 4-variable K-Map: Two adjacent squares represent a term of three literals. Four adjacent squares represent a term of two literals. Eight adjacent squares represent a term of one literal. Note: The larger the number of squares combined, the smaller the number of literals in the term.
17 3.3 Four-Variables Map (2-9) Flat Map Vs. Torus
18 3.3 Four-Variables Map (3-9) Example 1 (3-5) : F(w,x,y,z) = ( 0,1,2,4,5,6,8,9,12,13,14) w x 00 y z W YZ Y XYZ F = y + w yz + xyz
19 3.3 Four-Variables Map (4-9) Example 2 (3-6) : F = A B C + B CD + A BCD + AB C B C A B 00 C D A CD B D F = B D + B C + A CD
20 3.3 Four-Variables Map (5-9) Simplification using Prime Implicants o A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map. o If a minterm in a square is covered by only one prime implicant, that implicant is called Essential. o Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map. o Notes: Two adjacent 1 s form prime implicant, if they are not within a group of four adjacent squares. Four adjacent 1 s form prime implicant, if they are not within a group of eight adjacent squares and so on.
21 3.3 Four-Variables Map (6-9) Simplification using Prime Implicants B D Example 1: F(A,B,C,D) = (0,2,3,5,7,8,9,10,11,13,15) CD C B D ESSENTIAL Prime Implicants C BD A AB D AD B BD A 1 1 B D Minterms covered by single prime implicant
22 3.3 Four-Variables Map (7-9) Simplification using Prime Implicants Example 1: F(A,B,C,D) = (0,2,3,5,7,8,9,10,11,13,15) o Essential prim implicants:bd, B D o Prime implicant: CD, B C, AD, AB. o The minterms that not cover by essential implicants are: m3, m9, m11. The simplified expression is optained from the sum of the essential implicants and other prime implicants that may be needed to cover any remaining minterms. o So this function can be written with these ways: F = BD + B D + CD + AD F = BD + B D + CD + AB F = BD + B D + B C + AD F = BD + B D + B C + AB
23 3.3 Four-Variables Map (8-9) Simplification using Prime Implicants Example 2: F(W,X,Y,Z) = (0,2,3,8,9,10,11,12,13,14,15) X Z W Y X X Y Note: that all of these prime implicants are essential. Z W
24 3.3 Four-Variables Map (9-9) Simplification using Prime Implicants Example 3: F(W,X,Y,Z) = (0,2,3,4,7,12,13,14,15) W X Z W YZ Y W Y Z XY Z W X W X Y XYZ Essential: WX Prime: XYZ, XY Z, W Y Z, W YZ, W X Y, W X Z Z WX
25 3.5 Producut-of-Sum simplification (1-9) 1. Mark with 1 s the minterms of F. 2. Mark with 0 s the minterms of F. 3. Circle 0 s to express F. 4. Complement the result in step 3 to obtain a simplified F in product-of-sums form.
26 3.5 Producut-of-Sum simplification (1-9) Example 1: Simplify : F= (0,1,2,5,8,9,10) in Product-of-Sums Form CD C F = AB + CD + BD F = (F ) = (A +B ) + (C +D ) + (B +D) BD A B AB D
27 3.5 Producut-of-Sum simplification (1-9) Example 2: Simplify : F(x, y, z) = (0, 2, 5,7)in Product-of-Sums Form x 0 y z X Z F = XZ + X Z F = (F ) = (X +Z ) + (X+Z) XZ
28 3.6 Don't Cares Condition (1-4) Sometimes a function table or map contains entries for which it is known: The input values for the minterm will never occur, or The output value for the minterm is not used. Functions that have unspecified outputs for some input combinations are called incompletely specified functions. In these cases, the output value is defined as a don't care ( an x entry) assumed to be either 0 or 1. The choice between 0 and 1 is depending on the way the incompletely specified function is simplied. By placing don't cares in the function table or map, the cost of the logic circuit may be lowered.
29 3.6 Don't Cares Condition (2-4) Example : A logic function having the binary codes for the BCD digits as its inputs. Only the codes for 0 through 9 are used. The six codes, 1010 through 1111 never occur, so the output values for these codes are x to represent don t cares.
30 3.6 Don't Cares Condition (3-4) Example (3.9) : F(W,X,Y,Z) = (1,3,7,11,15) d(w,x,y,z) = (0,2,5) Y Y x 1 1 x x 1 1 x W 0 x X W 0 x X Z F = YZ + W Z Z F = YZ + W X
31 3.6 Don't Cares Condition (4-4) Example (3.9) : F(W,X,Y,Z) = (1,3,7,11,15) d(w,x,y,z) = (0,2,5) Y x 1 1 x W 0 x X Z F = Z + WY F = Z ( W + Y)
32 3.7 NAND and NOR Implementation (1-15) Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates.
33 3.7 NAND and NOR Implementation (2-15) NAND Implementation NAND gate: a universal gate. Any digital system can be implemented with it.
34 3.7 NAND and NOR Implementation (3-15) NAND Implementation To facilitate the conversion to NAND logic, there are alternative graphic symbol for it.
35 3.7 NAND and NOR Implementation (4-15) NAND Implementation Two-Level Implementation Procedures of Implementation with two levels of NAND gates: 1. Express simplified function in sum of products form. 2. Draw a NAND gate for each product term that has at least two literals to constitute a group of first-level gates 3. Draw a single gate using AND-invert or invert-or in the second level 4. A term with a single literal requires an inverter in the first level.
36 3.7 NAND and NOR Implementation (5-15) NAND Implementation Two-Level Implementation F = AB + CD = [(AB + CD) ] = [(AB) *(CD) ]
37 3.7 NAND and NOR Implementation (6-15) NAND Implementation Two-Level Implementation Example (3.10): F(X,Y,Z) = (1,2,3,4,5,7) x 0 y z X Y F = XY + X Y + Z XY Z
38 3.7 NAND and NOR Implementation (7-15) NAND Implementation Multilevel Implementation Procedures of Implementation with multilevel of NAND gates: 1. Convert all AND gates to NAND gates with ANDinvert graphic symbols 2. Convert all OR gates to NAND gates with invert- OR graphic symbols 3. Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal
39 3.7 NAND and NOR Implementation (8-15) NAND Implementation Multilevel Implementation EXAMPLE 1: F = A(CD + B) + BC
40 3.7 NAND and NOR Implementation (9-15) NAND Implementation Multilevel Implementation EXAMPLE 2: F = (AB + A B).(C + D )
41 3.7 NAND and NOR Implementation (10-15) NOR Implementation The NOR operation is the dual of the NAND operation. The NOR gate is anothar universal gate to implement any Boolean function.
42 3.7 NAND and NOR Implementation (11-15) NOR Implementation To facilitate the conversion to NOR logic, there are alternative graphic symbol for it.
43 3.7 NAND and NOR Implementation (12-15) NOR Implementation Two-Level Implementation Procedures of Implementation with two levels of NOR gates: 1. Express simplified function in product of sums form. 2. Draw a NOR gate for each product term that has at least two literals to constitute a group of first-level gates 3. Draw a single gate using OR-invert or invert-and in the second level 4. A term with a single literal requires an inverter in the first level.
44 3.7 NAND and NOR Implementation (13-15) NOR Implementation Two-Level Implementation Example : F = (A+B).(C+D).E E
45 3.7 NAND and NOR Implementation (14-15) NOR Implementation Multilevel Implementation Procedures of Implementation with multilevel of NOR gates: 1. Convert all OR gates to NOR gates with OR-invert graphic symbols 2. Convert all AND gates to NOR gates with invert- AND graphic symbols 3. Check all the bubbles in the diagrams. For a single bubble, invert aninverter (one-input NAND gate) or complement the input literal
46 3.7 NAND and NOR Implementation (15-15) NOR Implementation Multi-Level Implementation Example : F = (A B + A B).(C+D ) A B A B
47 3.8 Other Two-Level Implementations (1-7) Nondegeneratd forms Implementation 16 possible combinations of two-level forms with 4 types of gates: AND, OR, NAND, and NOR 8 are degenerate forms: degenerate to a single operation. (AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-NAND, NAND-NOR, NOR-AND, NOR-NAND) 8 are generate forms: NAND-AND = AND-NOR = AND-OR-INVERT OR-NAND = NOR-OR = OR-AND-INVERT
48 3.8 Other Two-Level Implementations (3-7) Nondegeneraetd forms Implementation 2 nd level 1 st level AND OR NAND NOR Discussed before Generated forms AND AND (3.4) NAND # Discuss now OR (3.4) OR $ NOR NAND # NAND (3.6) AND NOR NOR $ OR (3.6)
49 3.8 Other Two-Level Implementations (4-7) Nondegeneraetd forms Implementation AND-OR-INVERT o AND-NOR = NAND-AND = AND-OR-INVERT o Similar to AND-OR, AND-OR-INVERT requires an expression in sum of products Example: F = (AB + CD + E)
50 3.8 Other Two-Level Implementations (5-7) Nondegeneraetd forms Implementation OR-AND-INVERT o AND-NOR = NAND-AND = AND-OR-INVERT o Similar to OR-AND, OR-AND-INVERT requires an expression in product of sums Example: F = [(A+B). (C+D). E ]
51 3.8 Other Two-Level Implementations (6-7) Nondegeneraetd forms Implementation Equivalent Nondegenerate form a b Implements the Function Simplify F into To Get an Output of AND-NOR NAND-AND AND-OR- INVERT sum-of-products form by combining 0 s in the map F OR-NAND NOR-OR OR-AND- INVERT product-of-sums form by combining 1 s in the map and then complementing F
52 3.8 Other Two-Level Implementations (7-7) Nondegeneraetd forms Implementation Example (3.11) : F(x,y,z) = (0,7) AND-OR-INVERT: F = x y + xy + z F = ( x y + xy + z ) OR-AND-INVERT: F = x y z + xyz F = [ (x y z + xyz ) ] F = [ (x+y+z). (x +y +z) ]
53 3.9 Exclusive-OR Function (1-7) Exclusive-OR (XOR) denoted by the symbol : x y = xy + x y Exclusive-OR is equal to 1, when the values of x and y are diffrent. Exclusive-NOR (XNOR): (x y ) = xy + x y Exclusive-NOR is equal to 1, when the values of x and y are same. Only a limited number of Boolean functions can be expressed in terms of XOR operations, but it is particularly useful in arithmetic operations and errordetection and correction circuits.
54 3.9 Exclusive-OR Function (2-7) Exclusive-OR principles: x 0 = x x 1 = x x x = 0 x x = 1 x y = x y = (x y) x y = y x (x y) z = x (y z)
55 3.9 Exclusive-OR Function (3-7) Implementaion Exclusive-OR with AND-OR-NOT: x y = xy + x y Implementaion Exclusive- OR with NAND: x y = xy + x y = x (x +y ) + y (x +y ) = x (xy) + y (xy) = [ (x(xy) + y(xy) ) ] = [ (x(xy) ) + (y(xy) ) ]
56 3.9 Exclusive-OR Function (4-7) Odd Function: The 3-variable XOR function is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1. Multiple-variable exclusive OR operation = odd function : odd number of variables be equal to 1. (A B C) = (AB + A B) C + (A B + AB) C = AB C + A BC + A B C + ABC = (1,2,4,7)
57 3.9 Exclusive-OR Function (5-7) Odd Function:
58 3.9 Exclusive-OR Function (6-7) Odd Function: A B C D= (1,2,4,7,8,11,13,14)
59 3.9 Exclusive-OR Function (7-7) Parity Generation and Checking: Exclusive-OR function is useful in systems requiring error-detection and correction circuits. A parity bit is used for purpose of detection errors during transmission. Parity bit : an extra bit included with a binary message to make the number of 1 s either odd or even. The circuit generates the parity bit in transmitter is called parity generator. The circuit checks the parity bit in receiver is called parity checker.
60 3.9 Exclusive-OR Function (8-7) Parity Generation and Checking: Example : Three-bit message with even parity Three-bit Massage Parity bit X Y Z P o From the truth table, P constitutes an odd function. o It is equal 1 when numerical value of 1 s in a minterm is odd o P = x y z
61 3.9 Exclusive-OR Function (8-7) Parity Generation and Checking: Example : Three-bit message with even parity o From the truth table, C constitutes an odd function. o It is equal 1 when numerical value of 1 s in a minterm is odd o C = x y z P
Karnaugh Maps. Circuit-wise, this leads to a minimal two-level implementation
Karnaugh Maps Applications of Boolean logic to circuit design The basic Boolean operations are AND, OR and NOT These operations can be combined to form complex expressions, which can also be directly translated
More informationCSEE 3827: Fundamentals of Computer Systems. Standard Forms and Simplification with Karnaugh Maps
CSEE 3827: Fundamentals of Computer Systems Standard Forms and Simplification with Karnaugh Maps Agenda (M&K 2.3-2.5) Standard Forms Product-of-Sums (PoS) Sum-of-Products (SoP) converting between Min-terms
More informationBOOLEAN ALGEBRA & LOGIC GATES
BOOLEAN ALGEBRA & LOGIC GATES Logic gates are electronic circuits that can be used to implement the most elementary logic expressions, also known as Boolean expressions. The logic gate is the most basic
More informationUnited States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1
United States Naval Academy Electrical and Computer Engineering Department EC262 Exam 29 September 2. Do a page check now. You should have pages (cover & questions). 2. Read all problems in their entirety.
More informationKarnaugh Maps & Combinational Logic Design. ECE 152A Winter 2012
Karnaugh Maps & Combinational Logic Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 4 Optimized Implementation of Logic Functions 4. Karnaugh Map 4.2 Strategy for Minimization 4.2. Terminology
More informationSimplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
More informationUnit 3 Boolean Algebra (Continued)
Unit 3 Boolean Algebra (Continued) 1. Exclusive-OR Operation 2. Consensus Theorem Department of Communication Engineering, NCTU 1 3.1 Multiplying Out and Factoring Expressions Department of Communication
More informationBoolean Algebra Part 1
Boolean Algebra Part 1 Page 1 Boolean Algebra Objectives Understand Basic Boolean Algebra Relate Boolean Algebra to Logic Networks Prove Laws using Truth Tables Understand and Use First Basic Theorems
More informationCH3 Boolean Algebra (cont d)
CH3 Boolean Algebra (cont d) Lecturer: 吳 安 宇 Date:2005/10/7 ACCESS IC LAB v Today, you ll know: Introduction 1. Guidelines for multiplying out/factoring expressions 2. Exclusive-OR and Equivalence operations
More informationCSE140: Components and Design Techniques for Digital Systems
CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing What we covered thus far: Number representations Logic gates Boolean algebra Introduction to CMOS HW#2 due, HW#3 assigned
More informationBoolean Algebra (cont d) UNIT 3 BOOLEAN ALGEBRA (CONT D) Guidelines for Multiplying Out and Factoring. Objectives. Iris Hui-Ru Jiang Spring 2010
Boolean Algebra (cont d) 2 Contents Multiplying out and factoring expressions Exclusive-OR and Exclusive-NOR operations The consensus theorem Summary of algebraic simplification Proving validity of an
More informationexclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576
exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576 Outline exclusive OR gate (XOR) Definition Properties Examples of Applications Odd Function Parity Generation and Checking
More information1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
More informationCSE140: Midterm 1 Solution and Rubric
CSE140: Midterm 1 Solution and Rubric April 23, 2014 1 Short Answers 1.1 True or (6pts) 1. A maxterm must include all input variables (1pt) True 2. A canonical product of sums is a product of minterms
More informationBoolean Algebra. Boolean Algebra. Boolean Algebra. Boolean Algebra
2 Ver..4 George Boole was an English mathematician of XIX century can operate on logic (or Boolean) variables that can assume just 2 values: /, true/false, on/off, closed/open Usually value is associated
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationDigital circuits make up all computers and computer systems. The operation of digital circuits is based on
Digital Logic Circuits Digital circuits make up all computers and computer systems. The operation of digital circuits is based on Boolean algebra, the mathematics of binary numbers. Boolean algebra is
More informationLogic in Computer Science: Logic Gates
Logic in Computer Science: Logic Gates Lila Kari The University of Western Ontario Logic in Computer Science: Logic Gates CS2209, Applied Logic for Computer Science 1 / 49 Logic and bit operations Computers
More informationGates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
More information2.0 Chapter Overview. 2.1 Boolean Algebra
Thi d t t d ith F M k 4 0 2 Boolean Algebra Chapter Two Logic circuits are the basis for modern digital computer systems. To appreciate how computer systems operate you will need to understand digital
More information3.Basic Gate Combinations
3.Basic Gate Combinations 3.1 TTL NAND Gate In logic circuits transistors play the role of switches. For those in the TTL gate the conducting state (on) occurs when the baseemmiter signal is high, and
More informationTwo-level logic using NAND gates
CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 1 Two-level logic using NND gates Replace minterm ND gates with NND gates Place
More informationBasic Logic Gates Richard E. Haskell
BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that
More informationA Course Material on DIGITAL PRINCIPLES AND SYSTEM DESIGN
A Course Material on By MS.G.MANJULA ASSISTANT PROFESSOR DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SASURIE COLLEGE OF ENGINEERING VIJAYAMANGALAM 638 56 QUALITY CERTIFICATE This is to certify
More informationDESIGN OF GATE NETWORKS
DESIGN OF GATE NETWORKS DESIGN OF TWO-LEVEL NETWORKS: and-or and or-and NETWORKS MINIMAL TWO-LEVEL NETWORKS KARNAUGH MAPS MINIMIZATION PROCEDURE AND TOOLS LIMITATIONS OF TWO-LEVEL NETWORKS DESIGN OF TWO-LEVEL
More informationDigital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
More informationChapter 2: Boolean Algebra and Logic Gates. Boolean Algebra
The Universit Of Alabama in Huntsville Computer Science Chapter 2: Boolean Algebra and Logic Gates The Universit Of Alabama in Huntsville Computer Science Boolean Algebra The algebraic sstem usuall used
More informationUnderstanding Logic Design
Understanding Logic Design ppendix of your Textbook does not have the needed background information. This document supplements it. When you write add DD R0, R1, R2, you imagine something like this: R1
More informationCombinational circuits
Combinational circuits Combinational circuits are stateless The outputs are functions only of the inputs Inputs Combinational circuit Outputs 3 Thursday, September 2, 3 Enabler Circuit (High-level view)
More informationCDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline Multi-Level Gate Circuits NAND and NOR Gates Design of Two-Level Circuits Using NAND and NOR Gates
More informationSwitching Algebra and Logic Gates
Chapter 2 Switching Algebra and Logic Gates The word algebra in the title of this chapter should alert you that more mathematics is coming. No doubt, some of you are itching to get on with digital design
More informationLogic Reference Guide
Logic eference Guide Advanced Micro evices INTOUCTION Throughout this data book and design guide we have assumed that you have a good working knowledge of logic. Unfortunately, there always comes a time
More informationLecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
More informationENGI 241 Experiment 5 Basic Logic Gates
ENGI 24 Experiment 5 Basic Logic Gates OBJECTIVE This experiment will examine the operation of the AND, NAND, OR, and NOR logic gates and compare the expected outputs to the truth tables for these devices.
More informationGates & Boolean Algebra. Boolean Operators. Combinational Logic. Introduction
Introduction Gates & Boolean lgebra Boolean algebra: named after mathematician George Boole (85 864). 2-valued algebra. digital circuit can have one of 2 values. Signal between and volt =, between 4 and
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationA single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc
Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into acc
More informationBinary Adders: Half Adders and Full Adders
Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order
More informationCombinational Logic Design
Chapter 4 Combinational Logic Design The foundations for the design of digital logic circuits were established in the preceding chapters. The elements of Boolean algebra (two-element switching algebra
More informationCOMPUTER SCIENCE. Paper 1 (THEORY)
COMPUTER SCIENCE Paper 1 (THEORY) (Three hours) Maximum Marks: 70 (Candidates are allowed additional 15 minutes for only reading the paper. They must NOT start writing during this time) -----------------------------------------------------------------------------------------------------------------------
More informationNAND and NOR Implementation
University of Wisconsin - Madison EE/omp ci 352 Digital ystems Fundamentals harles R. Kime ection 2 Fall 200 hapter 2 ombinational Logic ircuits Part 7 harles Kime & Thomas Kaminski NND and NOR Implementation
More informationDEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453
More informationwww.mohandesyar.com SOLUTIONS MANUAL DIGITAL DESIGN FOURTH EDITION M. MORRIS MANO California State University, Los Angeles MICHAEL D.
27 Pearson Education, Inc., Upper Saddle River, NJ. ll rights reserved. This publication is protected by opyright and written permission should be obtained or likewise. For information regarding permission(s),
More informationTake-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas
Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count
More informationDesign and Development of Virtual Instrument (VI) Modules for an Introductory Digital Logic Course
Session ENG 206-6 Design and Development of Virtual Instrument (VI) Modules for an Introductory Digital Logic Course Nikunja Swain, Ph.D., PE South Carolina State University swain@scsu.edu Raghu Korrapati,
More informationThe string of digits 101101 in the binary number system represents the quantity
Data Representation Section 3.1 Data Types Registers contain either data or control information Control information is a bit or group of bits used to specify the sequence of command signals needed for
More informationLevent EREN levent.eren@ieu.edu.tr A-306 Office Phone:488-9882 INTRODUCTION TO DIGITAL LOGIC
Levent EREN levent.eren@ieu.edu.tr A-306 Office Phone:488-9882 1 Number Systems Representation Positive radix, positional number systems A number with radix r is represented by a string of digits: A n
More informationCounters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
More informationDigital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
More informationNEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.
CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache
More informationFORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. Lab 2. The Full-Adder
FORDHAM UNIVERSITY CISC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. Science Spring, 2011 Lab 2 The Full-Adder 1 Introduction In this lab, the student will construct
More informationClass One: Degree Sequences
Class One: Degree Sequences For our purposes a graph is a just a bunch of points, called vertices, together with lines or curves, called edges, joining certain pairs of vertices. Three small examples of
More informationMULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
CHAPTER3 QUESTIONS MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. ) If one input of an AND gate is LOW while the other is a clock signal, the output
More informationKarnaugh Maps (K-map) Alternate representation of a truth table
Karnaugh Maps (K-map) lternate representation of a truth table Red decimal = minterm value Note that is the MS for this minterm numbering djacent squares have distance = 1 Valuable tool for logic minimization
More information1.4. Arithmetic of Algebraic Fractions. Introduction. Prerequisites. Learning Outcomes
Arithmetic of Algebraic Fractions 1.4 Introduction Just as one whole number divided by another is called a numerical fraction, so one algebraic expression divided by another is known as an algebraic fraction.
More informationDigital Logic Design
Digital Logic Design Version 4.6 printed on February 2016 First published on August 2006 Background and Acknowledgements This material has been developed for the first course in Digital Logic Design. The
More informationGray Code Generator and Decoder by Carsten Kristiansen Napier University. November 2004
Gray Code Generator and Decoder by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Design of a Gray Code Generator and
More informationplc numbers - 13.1 Encoded values; BCD and ASCII Error detection; parity, gray code and checksums
plc numbers - 3. Topics: Number bases; binary, octal, decimal, hexadecimal Binary calculations; s compliments, addition, subtraction and Boolean operations Encoded values; BCD and ASCII Error detection;
More informationPUTNAM TRAINING POLYNOMIALS. Exercises 1. Find a polynomial with integral coefficients whose zeros include 2 + 5.
PUTNAM TRAINING POLYNOMIALS (Last updated: November 17, 2015) Remark. This is a list of exercises on polynomials. Miguel A. Lerma Exercises 1. Find a polynomial with integral coefficients whose zeros include
More informationFORDHAM UNIVERSITY CISC 3593. Dept. of Computer and Info. Science Spring, 2011. The Binary Adder
FORDHAM UNIVERITY CIC 3593 Fordham College Lincoln Center Computer Organization Dept. of Computer and Info. cience pring, 2011 1 Introduction The Binar Adder The binar adder circuit is an important building
More informationIntroduction. The Quine-McCluskey Method Handout 5 January 21, 2016. CSEE E6861y Prof. Steven Nowick
CSEE E6861y Prof. Steven Nowick The Quine-McCluskey Method Handout 5 January 21, 2016 Introduction The Quine-McCluskey method is an exact algorithm which finds a minimum-cost sum-of-products implementation
More informationChapter 1. Computation theory
Chapter 1. Computation theory In this chapter we will describe computation logic for the machines. This topic is a wide interdisciplinary field, so that the students can work in an interdisciplinary context.
More informationSPECIAL PRODUCTS AND FACTORS
CHAPTER 442 11 CHAPTER TABLE OF CONTENTS 11-1 Factors and Factoring 11-2 Common Monomial Factors 11-3 The Square of a Monomial 11-4 Multiplying the Sum and the Difference of Two Terms 11-5 Factoring the
More informationSistemas Digitais I LESI - 2º ano
Sistemas Digitais I LESI - 2º ano Lesson 6 - Combinational Design Practices Prof. João Miguel Fernandes (miguel@di.uminho.pt) Dept. Informática UNIVERSIDADE DO MINHO ESCOLA DE ENGENHARIA - PLDs (1) - The
More informationChapter 1: Digital Systems and Binary Numbers
Chapter 1: Digital Systems and Binary Numbers Digital age and information age Digital computers general purposes many scientific, industrial and commercial applications Digital systems telephone switching
More informationCourse Requirements & Evaluation Methods
Course Title: Logic Circuits Course Prefix: ELEG Course No.: 3063 Sections: 01 & 02 Department of Electrical and Computer Engineering College of Engineering Instructor Name: Justin Foreman Office Location:
More informationLecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots
Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots Registers As you probably know (if you don t then you should consider changing your course), data processing is usually
More informationFactoring Polynomials
UNIT 11 Factoring Polynomials You can use polynomials to describe framing for art. 396 Unit 11 factoring polynomials A polynomial is an expression that has variables that represent numbers. A number can
More informationDigital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
More informationChapter 7 Memory and Programmable Logic
NCNU_2013_DD_7_1 Chapter 7 Memory and Programmable Logic 71I 7.1 Introduction ti 7.2 Random Access Memory 7.3 Memory Decoding 7.5 Read Only Memory 7.6 Programmable Logic Array 77P 7.7 Programmable Array
More informationSample Test Questions
mathematics College Algebra Geometry Trigonometry Sample Test Questions A Guide for Students and Parents act.org/compass Note to Students Welcome to the ACT Compass Sample Mathematics Test! You are about
More informationELEC 2210 - EXPERIMENT 1 Basic Digital Logic Circuits
Objectives ELEC - EXPERIMENT Basic Digital Logic Circuits The experiments in this laboratory exercise will provide an introduction to digital electronic circuits. You will learn how to use the IDL-00 Bit
More informationC H A P T E R. Logic Circuits
C H A P T E R Logic Circuits Many important functions are naturally computed with straight-line programs, programs without loops or branches. Such computations are conveniently described with circuits,
More informationAdvanced GMAT Math Questions
Advanced GMAT Math Questions Version Quantitative Fractions and Ratios 1. The current ratio of boys to girls at a certain school is to 5. If 1 additional boys were added to the school, the new ratio of
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More information(1) /30 (2) /30 (3) /40 TOTAL /100
Your Name: SI Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY AVIS IRVINE LOS ANGELES RIVERSIE SAN IEGO SAN FRANCISCO epartment of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA
More informationSECTION C [short essay] [Not to exceed 120 words, Answer any SIX questions. Each question carries FOUR marks] 6 x 4=24 marks
UNIVERSITY OF KERALA First Degree Programme in Computer Applications Model Question Paper Semester I Course Code- CP 1121 Introduction to Computer Science TIME : 3 hrs Maximum Mark: 80 SECTION A [Very
More informationCOMBINATIONAL CIRCUITS
COMBINATIONAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/combinational_circuits.htm Copyright tutorialspoint.com Combinational circuit is a circuit in which we combine the different
More informationIE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584-640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines
More informationCM2202: Scientific Computing and Multimedia Applications General Maths: 2. Algebra - Factorisation
CM2202: Scientific Computing and Multimedia Applications General Maths: 2. Algebra - Factorisation Prof. David Marshall School of Computer Science & Informatics Factorisation Factorisation is a way of
More informationCOMPUTER SCIENCE 1999 (Delhi Board)
COMPUTER SCIENCE 1999 (Delhi Board) Time allowed: 3 hours Max. Marks: 70 Instructions: (i) All the questions are compulsory. (ii) Programming Language: C++ QUESTION l. (a) Why main function is special?
More informationSolutions Manual for How to Read and Do Proofs
Solutions Manual for How to Read and Do Proofs An Introduction to Mathematical Thought Processes Sixth Edition Daniel Solow Department of Operations Weatherhead School of Management Case Western Reserve
More informationGeometry Module 4 Unit 2 Practice Exam
Name: Class: Date: ID: A Geometry Module 4 Unit 2 Practice Exam Multiple Choice Identify the choice that best completes the statement or answers the question. 1. Which diagram shows the most useful positioning
More informationLecture Notes in Discrete Mathematics. Marcel B. Finan Arkansas Tech University c All Rights Reserved
Lecture Notes in Discrete Mathematics Marcel B. Finan Arkansas Tech University c All Rights Reserved 2 Preface This book is designed for a one semester course in discrete mathematics for sophomore or junior
More informationSection 1. Finding Common Terms
Worksheet 2.1 Factors of Algebraic Expressions Section 1 Finding Common Terms In worksheet 1.2 we talked about factors of whole numbers. Remember, if a b = ab then a is a factor of ab and b is a factor
More informationUpon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
More informationClick on the links below to jump directly to the relevant section
Click on the links below to jump directly to the relevant section What is algebra? Operations with algebraic terms Mathematical properties of real numbers Order of operations What is Algebra? Algebra is
More informationAMC 10 Solutions Pamphlet TUESDAY, FEBRUARY 13, 2001 Sponsored by Mathematical Association of America University of Nebraska
OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO AMERICAN MATHEMATICS COMPETITIONS nd Annual Mathematics Contest 10 AMC 10 Solutions Pamphlet TUESDAY, FEBRUARY 1, 001
More informationPROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1 This work covers part of outcome 3 of the Edexcel standard module: Outcome 3 is the most demanding
More informationLab 1: Study of Gates & Flip-flops
1.1 Aim Lab 1: Study of Gates & Flip-flops To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flip-flops. 1.2 Hardware Requirement a. Equipments -
More informationFigure 8-1 Four Possible Results of Adding Two Bits
CHPTER EIGHT Combinational Logic pplications Thus far, our discussion has focused on the theoretical design issues of computer systems. We have not yet addressed any of the actual hardware you might find
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 9 - Register Transfer and Microoperations Microoperations Digital systems are modular in nature, with modules containing registers, decoders, arithmetic
More informationEG1108: Electrical Engineering
EG1108: Electrical Engineering Part 2: Application Examples Ben M. Chen Professor of Electrical and Computer Engineering National University of Singapore Office: E4 06 08 Phone: 6516 2289 Email: bmchen@nus.edu.sg
More informationHow to bet using different NairaBet Bet Combinations (Combo)
How to bet using different NairaBet Bet Combinations (Combo) SINGLES Singles consists of single bets. I.e. it will contain just a single selection of any sport. The bet slip of a singles will look like
More informationSIMPLIFYING SQUARE ROOTS
40 (8-8) Chapter 8 Powers and Roots 8. SIMPLIFYING SQUARE ROOTS In this section Using the Product Rule Rationalizing the Denominator Simplified Form of a Square Root In Section 8. you learned to simplify
More information4. How many integers between 2004 and 4002 are perfect squares?
5 is 0% of what number? What is the value of + 3 4 + 99 00? (alternating signs) 3 A frog is at the bottom of a well 0 feet deep It climbs up 3 feet every day, but slides back feet each night If it started
More informationearlier in the semester: The Full adder above adds two bits and the output is at the end. So if we do this eight times, we would have an 8-bit adder.
The circuit created is an 8-bit adder. The 8-bit adder adds two 8-bit binary inputs and the result is produced in the output. In order to create a Full 8-bit adder, I could use eight Full -bit adders and
More informationPhiladelphia University Faculty of Information Technology Department of Computer Science ----- Semester, 2007/2008.
Philadelphia University Faculty of Information Technology Department of Computer Science ----- Semester, 2007/2008 Course Syllabus Course Title: Computer Logic Design Course Level: 1 Lecture Time: Course
More information