Overview. Technology Details

Transcription

1 Overview D/AVE HD is an evolution in the D/AVE family supporting high quality 2D rendering and basic 3D rendering for displays up to 4K x 4K. Targeting modern graphics applications on high resolution displays in the Industrial, Medical, Military, Avionics, Automotive and Consumer markets, D/AVE HD is designed to be fast with powerful functionality and at the same time optimized regarding size and footprint. D/AVE HD is available for both FPGA and ASIC integration with high customizability as well as scalability and a peak performance between 1 and 16 pixels per clock cycle. D/AVE HD offers several enhancements over the previous D/AVE 2D version as related to various blit operations, cache enhancements, texture pre-fetch and power management. By providing the CDC-200 (Customizable Display Controller) and the GUIliani HMI Framework together with D/AVE HD, TES offers a complete graphics subsystem. Technology Details Rendering High render quality o General sub pixel positioning o Direct-edge anti-aliasing o Blurring of primitive edges Hardware accelerated primitives o Fast clear/rectangle fill o Lines o Triangles o Quadrangles o Beziers (optional) o Advanced Blit operations supporting scaling, stretching, rotating, coloring and alpha-blending o Convolution Filtering Fill styles o Constant color o Gouraud Shading (Alpha/Color Gradients) o Pattern o Multi-Texturing with perspective correction Blending o Normal alpha blending o Independent alpha/color blending o Source/Destination factors: 0, 1, source alpha, 1-source alpha Different connection styles for poly lines (useful e.g. for map applications): miter, round, bevel Various bitmap formats (textures and frame buffers) o 8 bit alpha/luminance, ARGB4444, ARGB1555, RGB565, ARGB8888 etc. o Indexed formats for CLUT (Color Look Up Table) o Easily extendable o Run-Length-Encoded Textures High resolutions

2 o Frame buffers and textures up to 4k x 4k pixels Optional: HW extension for full OpenVG 1.1 compliance Support for basic 3D graphics operations o Z-Buffer o Texturing with perspective correction Support for Image Transformation & Warping Rotation Engine Composition Engine System Concept & Features Base version (single pipeline) 1 pixel per clock cycle (MPixels/s = MHz) o Core can scale to multiple parallel pixel pipelines to multiply pixel throughput Read prefetching / Multiple outstanding reads o No unnecessary reads (no full cache lines when not all pixels accessed) o Hide bus read latency Sophisticated caching mechanisms for command lists, textures and framebuffer data Optimization of applications by using detailed performance counters for o Total active cycles o Cache access efficiency o Bus accesses o etc. Pipelined architecture for high clock frequencies Hardware multi-threading support o Rendering jobs can be halted and resumed o Hardware can store and load rendering context System security features o Command list can be check-sum protected o Stop on bus error for integration with memory protection units o Hardware out-of-framebuffer memory access protection Power Memory blocks controlled by Chip Select port Prepared for efficient automatic clock gating Global clock gating as option Integration Low resource consumption (starting at 250K gates) Single clock domain architecture o Bus interface clock frequency may differ from core frequency High latency capable 3-5 separate bus master interfaces vs. 1 single bus master (internal arbitration option) Adaptors for common bus protocols o ARM AMBA: APB for register access, AHB or AXI (preferred) for memory bus master access o Altera Avalon as bus adaptors for both register and bus master access o Other bus protocols can be easily adapted

3 Resource Usage The actual resource usage of D/AVE HD depends mainly on the number of pixel pipelines and partly on the bus and cache configuration. The following numbers give an indication of the resource usage for a typical configuration. FPGA Resource Usage (single pipeline) 32 bit AXI, no OpenVG 64 bit AXI, OpenVG Logic cells ~ logic elements ~ logic elements DSP blocks 56 multipliers (9x9) 78 multipliers (9x9) RAM blocks 12 M9K blocks ~25 M9K blocks All numbers given for Altera Cyclone III device family Std. Cell ASIC Resource Usage (single pipeline) 32 bit AXI, no OpenVG 64 bit AXI, OpenVG Gate count ~250k NAND2 gate equivalents ~500k NAND2 gate equivalents Memory blocks 6-11 memory blocks, all simple dual ported (one read port, one write port) Exact sizes depend on cache configuration. Typically, the memory area is about the same as the logic area.

4 Block diagram Display List Reader Global Events Performance Counters Counter Values SBI Config/Status Controller Status / Config Global Status IRQ Status/Enable/Clear Stream Controller Register Writes IRQ Interrupt Controller IRQ Start MBI MBI (Scissor/Overdraw Buffer) Arbiter MBI 2nd level texture cache MBI (Texture) MBI (Tex #n...) Pixel Pipeline #1 Config Register File Global Status MBI (Framebuffer) MBI Pixel Pipeline #n Clear Unit

5 Performance The peak performance of 1 pixel per pixel pipeline and cycle can be achieved under the following conditions: Large primitives Texture miss rate balanced compared to the available bus bandwidth Sufficient bus bandwidth in general The external bus architecture supports byte write enables (e.g. AXI) and sufficient internal buffers for handling outstanding accesses to hide the read latency Memory read latencies for command list, texture and framebuffer read accesses can be hidden in principle with sufficient FIFO depth configuration in the prefetching caches. In practice, with a decent bus integration and cache configuration, this means that larger primitives, i.e. having a size of more than 10x10 pixels reach about 90% of this rate, approximating the 100% the larger they get. This even holds for a textured/filtered fill of these objects (e.g. blits) with transparency over the background and only degrades towards 50% when textures are rotated.

6 Software Drivers TES provides a Generic D/AVE HD API driver allowing easy usage of the high level features of D/AVE HD without the need to directly access the registers. The driver has the following features: Plain ANSI-C Code Fully reentrant & thread-safe Minimal OS dependency (HAL part separated) No floating point usage No inline assembler required Support for multiple D/AVE HD instances Multi-threading support, i.e. multiple applications can use D/AVE HD concurrently, even via different APIs Small memory footprint On top of this proprietary D/AVE HD API, standard APIs or Wrapper APIs can be provided on request: OpenVG 1.1 OpenGL-ES 1.1 (subset) D/AVE 2D Wrapper API Others are possible Application Application Application Application D/AVE 2D Wrapper OpenGL ES 1.1 (subset) OpenVG 1.1 D/AVE HD Driver HAL part D/AVE Hardware

7 Verification Concept A 100% algorithmic equivalent C model is used as reference for the verification of the RTL code. This real-time capable reference model is called Soft D/AVE which acts as a pixel accurate emulator on Windows PC. The emulator is also used for driver and application development. The following test metrics are used: Functional Coverage Code Coverage using Cadence IUS Static Code Checking Timing Checks FPGA prototyping Sales & Marketing Contact TES Electronic Solutions GmbH Frankenstrasse Hamburg Germany graphics@tes-dst.com