Fujitsu Petascale Supercomputer PRIMEHPC FX10. 4x2 racks (768 compute nodes) configuration. Copyright 2012 FUJITSU LIMITED

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Georgiana Pitts
7 years ago
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1 Fujitsu Petascale Supercomputer PRIMEHPC FX10 4x2 racks (768 compute nodes) configuration

PRIMEHPC FX10 Highlights Scales up to 23.

technology employed in the FX1 and the K computer,

PRIMEHPC FX10 Hybrid parallel (VISIMPACT)

(HPC-ACE) K computer SPARC64 VII 4C/40GF 121TFLOPS,

2 PRIMEHPC FX10 Highlights Scales up to 23.2 PFLOPS Improves Fujitsu s supercomputer technology employed in the FX1 and the K computer, the world s fastest supercomputer. PRIMEHPC FX10 Hybrid parallel (VISIMPACT) Collective Sw FX1 Tofu interconnect ISA extension (HPC-ACE) K computer SPARC64 VII 4C/40GF 121TFLOPS, CY2008~ SPARC64 TM VIIIfx 8C/128GF 11PFLOPS, CY2010~ 1 SPARC64 TM IXfx 16C/236.5GF ~ 23PFLOPS, CY2012~

3 PRIMEHPC FX10 Features High-speed and ultra-large-scale computing environment Up to 23.2 PFLOPS (98,304 nodes, 1,024 racks, 6 petabytes of memory) SPARC64 IXfx high performance w/ low power consumption GFLOPS, and over 2GFLOPS/W High execution performance with massively parallel apps Tofu interconnect, Technical Computing Suite, and VISIMPACT High reliability and high operability for a large-scale system 2

Implementation of PRIMEHPC FX10 CPU 236.

4 Implementation of PRIMEHPC FX10 CPU GFlops L2$ : : Node 1 CPU SX ctrl MC CPU Node DDR3 DIMM ICC GFlops Memory of up to 64 GB System board (SB) 4 nodes (4 CPUs) 946 GFlops Memory of up to 256 GB Rack 96 compute nodes (24 SBs) 6 IO nodes (6 IOSBs) 22.7 TFlops Memory of up to 6 TB Maximum configuration 1,024 racks 98,304 compute nodes 6,144 IO nodes 23.2 PFlops Memory of up to 6 PB 3

SPARC64 IXfx Inherited features from SPARC64 TM VIIIfx High performance HPC-ACE Embedded memory controller Hardware barrier mechanism Low power Moderate frequency Dynamic/Leakage power reduction

5 SPARC64 IXfx Inherited features from SPARC64 TM VIIIfx High performance HPC-ACE Embedded memory controller Hardware barrier mechanism Low power Moderate frequency Dynamic/Leakage power reduction High reliability RAS features New features Doubled number of cores Doubled size of L2$ 4 DDR3 interface MAC MAC L2$ Data L2$ Data HSIO L2$ Control SPARC64 TM IXfx L2$ Data L2$ Data MAC MAC DDR3 interface

6 SPARC64 VIIIfx / IXfx Specifications SPARC64 TM VIIIfx SPARC64 TM IXfx Number of cores 8 cores 16 cores Clock frequency 2 GHz GHz Cache L1 I: 32KB/core, D: 32KB/core I: 32KB/core, D: 32KB/core L2 6MB (Shared cache) 12MB (Shared cache) Peak performance 128 Gigaflops Gigaflops Memory throughput 64 GB/s 85 GB/s Power consumption 58W 110W Process 45 nm 40 nm Die size 22.7 mm 22.6 mm 21.9 mm 22.9 mm Number of transistors Approximately 760 million Approximately 1.87 billion 5

Tofu Interconnect Highly scalable and usable direct network (6D

simultaneous transfer) Good collective communication performance

reduction in H/W Direct attached interconnect controller SPARC64

Inter- Connect Controller A Z Z B Tofu realizes scalable systems

7 Tofu Interconnect Highly scalable and usable direct network (6D mesh/torus) 10 redundant high BW links, 4 RDMA engines (4x2 simultaneous transfer) Good collective communication performance with Tofu original algorithms Tofu barrier for barrier & reduction in H/W Direct attached interconnect controller SPARC64 TM IXfx C Y CPU 20GB/s x 2 Y X B X (ICC) 5GB/s x 2 x10 links XYZ Inter- Connect Controller A Z Z B Tofu realizes scalable systems beyond 100,000 nodes With low power consumption, low latency, and high BW 6 ABC

8 PRIMEHPC FX10 Software Structure User/ISV Applications HPC Portal / System Management Portal System operations management System configuration management System control System monitoring System installation & operation Job operations management Job manager Job scheduler Resource management Parallel execution environment High-performance file system Lustre-based distributed file system High scalability IO bandwidth guarantee High reliability & availability VISIMPACT TM Shared L2 cache on a chip Hardware intra-processor synchronization Compilers Hybrid parallel programming Sector cache support SIMD / Register file extensions Support Tools IDE Profiler & Tuning tools Interactive debugger MPI Library Scalability of High-Func. Barrier Comm. File system, operations management Application development environment Linux-based enhanced Operating System PRIMEHPC FX10 7 Enhanced hardware support System noise reduction Error detection / Low power

9 PRIMEHPC FX10 Specifications System specifications Number of racks 4 to 1,024 Number of compute nodes 384 to 98,304 Theoretical Peak performance 90.8 Tera FLOPS to 23.2 Peta FLOPS Total memory capacity 12 TB to 6 PB Interconnect Tofu interconnect Cooling method Direct water cooling + air cooling Option : Exhaust cooling unit Node specifications Theoretical peak performance Giga FLOPS Processor SPARC64 IXfx (1.848 GHz, 16 cores) x 1 Memory capacity 32 GB, 64 GB Memory bandwidth 85 GB/s Interconnect link bandwidth 5 GB/s x 2 (bi-directional) 8

10 PRIMEHPC FX10 Summary Improves Fujitsu s supercomputer technology employed in the K computer, the world s fastest supercomputer Newly developed SPARC64 IXfx processor (236.5GFLOPS) Tofu interconnect (scales up to 98,304 nodes) Fujitsu provides all hardware and software Processor and interconnect Technical Computing Suite HPC middleware, as well as FEFS high-performance distributed file system 9

11 10

Current Status of FEFS for the K computer

Current Status of FEFS for the K computer Shinji Sumimoto Fujitsu Limited Apr.24 2012 LUG2012@Austin Outline RIKEN and Fujitsu are jointly developing the K computer * Development continues with system