Multicycle Datapath Approach. Multicycle Datapath Approach

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Dulcie Snow
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1 Multicycle Datapath Approach Let an instruction take more than clock cycle to complete Break up instructions into steps where each step takes a cycle while trying to» balance the amount of work to be done in each step» restrict each cycle to use only one major functional unit Not every instruction takes the same number of clock cycles In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result only need one memory but only one memory access per cycle need only one ALU/adder but only one ALU operation per cycle Multicycle Datapath Approach Let an instruction take more than clock cycle to complete Break up instructions into steps where each step takes a cycle while trying to» balance the amount of work to be done in each step» restrict each cycle to use only one major functional unit Not every instruction takes the same number of clock cycles In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result only need one memory but only one memory access per cycle need only one ALU/adder but only one ALU operation per cycle 2 Page

2 Multicycle Datapath Approach, con t At the end of a cycle Store values needed in a later cycle by the current instruction in an internal register (not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed) PC Memory Address Read Data (Instr. or Data) Write Data IR MDR Read Addr Register Read Read Addr 2Data File Write Addr Read Write Data Data 2 A B ALU ALUout IR Instruction Register MDR Memory Data Register A, B regfile read data registers ALUout ALU output register Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory) 3 The Multicycle Datapath with Control Signals PCWriteCond PCWrite IorD MemRead MemWrite MemtoReg IRWrite PCSource ALUOp Control ALUSrcB ALUSrcA RegWrite RegDst PC Address Write Data Memory Read Data (Instr. or Data) IR MDR Instr[3-26] Read Addr Register Read Read Addr 2 Data File Write Addr Read Data 2 Write Data Instr[5-] Sign Extend 32 Instr[5-] Instr[25-] Shift left 2 A B PC[3-28] Shift left 2 zero ALU ALU control 28 ALUout 2 4 Page 2

3 Multicycle Control Unit Multicycle datapath control signals are not determined solely by the bits in the instruction e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next Must use a finite state machine (FSM) for control a set of states (current state stored in State Register) next state function (determined by current state and the input) output function (determined by current state and the input) Combinational control logic... Datapath control points... Inst Opcode... State Reg Next State 5 The Five Steps of the Load Instruction Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 lw IFetch Dec Exec Mem WB IFetch: Instruction Fetch and Update PC Dec: Instruction Decode, Register Read, Sign Extend Offset Exec: Execute R-type; Calculate Memory Address; Branch Comparison; Branch and Jump Completion Mem: Memory Read; Memory Write Completion; R-type Completion (RegFile write) WB: Memory Read Completion (RegFile write) INSTRUCTIONS TAKE FROM 3-5 CYCLES! 6 Page 3

4 Single Cycle vs. Multiple Cycle Timing Single Cycle Implementation: Clk Cycle Cycle 2 Multiple Cycle Implementation: lw sw Waste multicycle clock slower than /5 th of single cycle clock due to state register overhead Clk Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch 7 8 Page 4

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Solutions. Solution 4.1. 4.1.1 The values of the signals are as follows:

Solutions. Solution 4.1. 4.1.1 The values of the signals are as follows: 4 Solutions Solution 4.1 4.1.1 The values of the signals are as follows: RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a. 1 0 0 (Reg) 0 Add 1 (ALU) 0 b. 1 1 1 (Imm) 0 Add 1 (Mem) 0 ALUMux is the