PROCESSOR: DATAPATH & CONTROL - 1

Transcription

1 PROCESSOR: DATAPATH & CONTROL - Dr. Bill Yi Santa Clara University (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3 rd Ed., Morgan Kaufmann, 27) (Also based on presentation: Dr. Nam Ling, COEN2 Lecture Notes)

2 COURSE CONTENTS Introduction s Computer Arithmetic Performance Processor: path Processor: Control Pipelining Techniques Memory Input/Output Devices 2

3 PROCESSOR: DATAPATH & CONTROL Elements of path Single-Cycle path 3

4 Subset of MIPS s We aim to design a processor to implement a subset of the core MIPS instruction set: Memory-reference instructions: lw and sw instructions (R-type): add, sub, and, or, slt Branch instruction beq and jump j 4

5 Performance Performance of a machine is determined by: count Clock cycle time Clock cycles per instruction CPI Processor design (path and control) will affect: Clock cycle time Clock cycles per instruction Inst. Count Cycle Time 5

6 Execution Steps lw/sw: fetch instruction, inc. PC (need inst., PC, +4 adder) select registers (rs, rt) (need register file) calculate mem. address (need inst., sign ext, ) read/write (need ) write register (for lw) (need register file) (R): fetch instruction, inc. PC (need inst., PC, +4 adder) select registers (rs, rt) (need register file) operation on two (need ) write registers (rd) (need register file) Branch (beq): fetch instruction, inc. PC (need inst., PC, +4 adder) select registers (rs, rt) (for beq) (need register file) test condition, cal. target address (need, inst., sign ext, x4 shifter) update PC (need PC, adder) Jump (j): fetch instruction, inc. PC (need inst., PC, +4 adder) calculate target address (need inst., x4 shifter) update PC (need PC) First step common to all, second step common to all (except jump) 6

7 Generic Implementation Generic Implementation: use the program counter (PC) to supply instruction address get the instruction from read registers use the instruction to decide exactly what to do 7

8 Resources Needed PC address Add Sum 6 32 Sign extend Shifter a. Program counter Register numbers register register 2 Registers register b. 2 4 c. Adder control Zero d. Sign-extension unit Address Mem h. Shifter Reg Mem e. Register file f. g. unit 8

9 control lines Function 4 control AND OR Add Zero Subtract Set on less than (slt) f. NOR Note: NOR is needed for other parts of MIPS instruction set 9

10 Register File () register number register number 2 Register Register Register n Register n M u x M u x 2 register number register number 2 Register file register 2

11 Register File () Note: we still use the real clock to determine when to write Register number n-to- decoder n n C Register D C Register D Register C Register n D C Register n D

12 Clocking Methodology Defines when signals can be read and when they can be written We assume edge-triggered clocking: values updated only on a clock edge Diagram below: all signals must propagate from state element through the combinational logic, and to state element 2 in one clock cycle Time needed for signals to reach state element 2 defines length of clock cycle State element Combinational logic State element 2 Clock cycle 2

13 Abstract View of path Two types of functional units: elements that operate on values (combinational) e.g. elements that contain state (sequential) e.g. register, Register # PC Address Registers Address Register # Register # 3

14 Fetch path Next Address Logic 4 Add PC address Inst 4

15 R-type () s The path below works for R-type () instructions Register # PC Address Registers Register # Register # Address 5

16 Load/Store s We add a sign extender Register # PC Address Registers Register # Register # Address 6 sign extend 32 6

17 Branch & Jump s We add next address logic. Note for jump : destination address = concatenating upper 4 bits of current PC+4 to the 26-bit address field in jump inst and adding as the 2 lower bits) 7

18 Branch & Jump s PC + 4 M ux Inst [25-] Shift left PC + 4 [3-28] 32 J addrr [3-] 32 Shift left 2 Add zero Register # PC Address Registers Register # Register # Address 6 sign extend 32 8

19 Building the path Use multiplexers (MUX) to stitch them together Do not duplicate functional units common to different instructions Add control signals (for MUX selection, operation, state element read/write) Independent operations can be in parallel 9

20 Building the path PCSrc 4 Add 26 Shift left Shift left 2 Add M ux PC address register register 2 register Registers 2 Reg 6 Sign 32 extend Src M ux 4 operation Zero Address Mem Mem MemtoReg M ux 2

21 A Single-cycle path This path executes each basic instruction in a single clock cycle No resource (functional unit) can be used more than once during a single cycle PCSrc 4 Add 26 Shift left Shift left 2 Add M ux PC address register register 2 register Registers 2 Reg 6 Sign 32 extend Src M ux 4 operation Zero Address Mem Mem MemtoReg M ux 2

22 The R-FormatR path PCSrc 4 Add Reg Shift left 2 Add M u x PC address [3 ] [25 2] [2 6] [5 ] M u x RegDst [5 ] register register 2 register 2 Registers 6 Sign 32 extend Src M u x control Zero Mem Address Mem MemtoReg M u x [5 ] Op 22

23 The Load path PCSrc 4 Add Reg Shift left 2 Add M u x PC address [3 ] [25 2] [2 6] [5 ] M u x RegDst [5 ] register register 2 register 2 Registers 6 Sign 32 extend Src M u x control Zero Mem Address Mem MemtoReg M u x [5 ] Op 23

24 The Store path PCSrc 4 Add Reg Shift left 2 Add M u x PC address [3 ] [25 2] [2 6] [5 ] M u x RegDst [5 ] register register 2 register 2 Registers 6 Sign 32 extend Src M u x control Zero Mem Address Mem MemtoReg M u x [5 ] Op 24

25 The BEQ path PCSrc 4 Add Reg Shift left 2 Add M u x PC address [3 ] [25 2] [2 6] [5 ] M u x RegDst [5 ] register register 2 register 2 Registers 6 Sign 32 extend Src M u x control Zero Mem Address Mem MemtoReg M u x [5 ] Op 25

26 Control Signals Selecting the operations to perform (, read/write, etc.) Controlling the flow of (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $7, $8 Format: op rs rt rd shamt funct s operation based on instruction type and function code 26

27 Control : 4 control inputs AND OR add subtract set-on-less-than NOR Example: lw $, ($2) 35 2 op rs rt 6 bit offset What are the inputs and what are the control signals for this operation? 27

28 Control To generate 4-bit control signals from instruction, we apply 2-level decoding From instruction opcode, main control generates 2-bit Op & Op: = lw, sw = beq, = arithmetic If Op = generates control = (add) If Op = generates control = (subtract) If Op = use the 6-bit function code in instruction to generate control Describe the control generation algorithm using a truth table (can turn into gates): Op Funct field Operation Op Op F5 F4 F3 F2 F F Cntrl X X X X X X X X X X X X X X X X X X X X X X X X X X X X 28

29 Main Control M ux 4 Add [3 26] Control RegDst Branch Mem MemtoReg Op Mem Src Reg Shift left 2 Add PC address [3 ] [25 2] [2 6] [5 ] [5 ] M ux register register 2 Registers 2 register 6 32 Sign extend M ux control Zero Address M ux Note also the use of different fields (bits) of the instruction & the use of MUX [5 ] 29

30 Main Control Opcode R egd st A LU S rc Memto- Reg Reg Mem Mem W rite Branch Op p R -form at lw sw X X beq X X Note: 9 control signals generated from main control we ignore jump instruction here 3

31 Control Unit Logic Simple combinational logic (from truth tables) Inputs PLA Op 2 Op Op control block Operation3 = (not implementing NOR here) Op5 Op4 Op3 Op2 Op Op F(5 ) 6 F3 F2 F F Operation2 Operation Operation 3 Operation R-format Iw sw beq Outputs RegDst Src MemtoReg Reg Mem Mem Branch Op control unit Main control unit OpO 3

32 Single-Cycle Implementation So far all logic combinational We wait for everything to settle down, and the right thing to be done E.g. might not produce right answer right away We use write signals along with clock to determine when to write to state elements (e.g. registers,, PC) (i.e. write to state elements when operations are completed and settled) Cycle time determined by length of the longest path. This path is certainly a lw instruction, which uses 5 functional units in series: instruction, register file,,, register file. Although CPI =, overall performance is not good, since several instructions could fit in a shorter cycle State element Combinational logic State element 2 write Clock cycle We are ignoring some details like setup and hold times 32

33 Critical Path for Different Classes Functional Units Used class R () Register file Register file Load w ord Register file Register file Store w ord Register file Branch (beq) Register file PC next address Jum p PC next address N ote: N ot consid ering op erations in p arallel e.g. P C + 4 can b e in p arallel w ith reg ister access; not including resources like mux, sign ext, etc. PCSrc PC 4 Add address 26 Shift left 2 4 register Registers register 2 register 2 Reg 6 Sign 32 extend Shift left 2 Src M ux Add 4 operation Zero Address M ux Mem Mem MemtoReg M ux 33

34 Single-Cycle path & Control Including Jump 34

35 Single-cycle Problems & Solutions Single Cycle Problems: what if we had a more complicated instruction like floating point? very long cycle time (hence very inefficient for other instructions) each functional unit can only be used once per clock cycle, hence some units must be duplicated (wasteful of area) One Solution: use a smaller cycle time have different instructions take different numbers of cycles a multicycle path Pipelining (will discuss later) Example: insert state elements for multi-cycle implementation: PC Address Memory or register Memory register Register # Registers Register # Register # A B Out 35

36 Single-cycle Summary Elements of path: instruction subset, resources, clocking method path for different instruction classes Building single-cycle path: multiplexors, functional units, control signals Single-cycle path control unit logic: control, main control Single-cycle path & control: complete picture, critical path, problems 36