ELC4438: Embedded System Design Finite State Machine for RISC SPM

Transcription

1 ELC4438: Embedded System Design Finite State Machine for RISC SPM Liang Dong Electrical and Computer Engineering Baylor University

2 Partitioned Sequential Machine Datapaths Datapath Unit External Control Inputs Control Unit Finite State Machine Control signals Datapath Logic Clock Datapath Registers Status signals Clock 2

3 Application-Driven Architecture Application Architecture Instruction Set Control Sequence Control Unit FSM 3

4 Design Example Binary Counter Synchronous 4-bit binary counter Incremented by a count of at each active edge of the clock enable must be asserted for counting to occur rst overrides all activity and drives the count to a value of. Wrap count to when the count reaches 2. Functional elements of the architecture of the datapath unit: 4-bit register to hold count, mux that steers either count or the sum of count and to the input of the register a 4-bit adder to increment count 4

5 Binary Counter Architecture Binary_Counter_Arch Datapath_Unit_Arch + Mux enable Control_Unit Count_Register clk rst count 5

6 enable Alternative Counter Design - Explicit Finite State Machine rst enable enable enable enable enable enable enable enable enable enable enable enable Can this grow to larger counters? 6

7 Project Control Project is application oriented Datapath and functional units designed to meet needs of instruction set Reduced complexity by splitting control / datapath. FSM allows for easy addition of operations Allows use of single functional unit for multiple operations Use counters with FSM to reduce number of states Add state use counter to determine when operation done 7

8 RISC Stored Program Machine (SPM) RISC_SPM Controller Processor Load_R Load_R Load_R2 Load_R3 Load_PC R R R2 R3 PC IR Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Mux_ Bus_ Load_Reg_Y Reg_Y opcode ALU Memory alu_zero_flag Load_Reg_Z Reg_Z mem_word ad dr es s zero Zflag Sel_Bus_2_Mux 2 Mux_2 Add_R write Bus_2 8

9 Instruction Sequence Fetch instruction from memory Decode instruction and fetch operands Execute instruction ALU operations Update storage registers Update program counter (PC) Update the instruction register (IR) Update the address register (ADD_R) Update memory Control datapaths 9

10 Control Functions Functions of the control unit: Determine when to load registers Select the path of data through the multiplexers Determine when data should be written to memory Control the three-state busses in the architecture.

11 RISC_SPM Controller Processor Control Signal Load_Add_Reg Load _PC Load_IR Inc_PC Sel_Bus Mux Sel_Bus_2_Mux Load_R Load_R Load_R2 Load_R3 Load_Reg_Y Load Reg_Z write Control Signals Action Loads the address register Loads Bus_2 to the program counter Loads Bus_2 to the instruction register Increments the program counter Selects among the Program_Counter, R, R, R2, and R3 to drive Bus_ Selects among Alu_out, Bus_, and memory to drive Bus_2 Loads general purpose register R Loads general purpose register R Loads general purpose register R2 Loads general purpose register R3 Loads Bus_2 to the register Reg_Y Stores output of ALU in register Reg_Z Loads Bus_ into the SRAM memory Load_R Load_R Load_R2 Load_R3 Load_PC Inc_PC instruction Sel_Bus Mux Load_IR Load_Add_Reg Load_Reg_Y Load_Reg_Z zero Sel_Bus_2_Mux write opcode R R R2 R3 Reg_Y alu_zero_flag Zflag Reg_Z Bus_2 ALU Mux_ 2 Mux_2 PC IR Bus_ Memory ad mem_word dr es s Add_R

12 RISC SPM: Instruction Set [] The design of the controller depends on the processor's instruction set. RISC SPM has two types of instructions. Short Instruction 8 bits (basic arithmetic) opcode source destination Long Instruction 6 bits (accessing memory) opcode source destination don't care don't care address 2

13 RISC SPM: Instruction Set [2] Instr Instruction Word Action opcode src dest NOP???? none ADD src dest dest <= src + dest SUB src dest dest <= dest - src AND src dest dest <= src && dest NOT src dest dest <= ~src RD*?? dest dest <= memory[add_r] WR* src?? memory[add_r] <= src BR*???? PC <= memory[add_r] BRZ*???? PC <= memory[add_r] HALT???? Halts execution until reset * Requires a second word of data;? denotes a don't care. 3

14 Controller Design Three phases of operation: fetch, decode, and execute. Fetching: Retrieves an instruction from memory (2 clock cycles) Decoding: Decodes the instruction, manipulates datapaths, and loads registers ( cycle) Execution: Generates the results of the instruction (,, or 2 cycles) 4

15 Controller States [] S_idle S_fet S_fet2 S_dec S_ex State entered after reset is asserted. No action. Load the Add_R with the contents of the PC Load the IR with the word addressed by the Add_R, Increment the PC Decode the IR Assert signals to control datapaths and register transfers. Execute the ALU operation for a single-byte instruction, Conditionally assert the zero flag, Load the destination register 5

16 Controller States [2] S_rd S_rd2 S_wr S_wr2 S_br S_br2 S_halt Load Add_R with the second byte of an RD instruction Increment the PC. Load the destination register with memory[add_r] Load Add_R with the second byte of a WR instruction, Increment the PC. Write memory[add_r] with the source register Load Add_R with the second byte of a BR instruction Increment the PC. Load the PC with the memory[add_r] Default state to trap failure to decode a valid instruction Which states are similar? 6

17 Controller ASM: NOP/ADD/SUB/AND S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Instruction Decode Execute S_dec 3 NOP src = R Sel_R Sel_Bus_ Load_Reg_Y S_ex 4 dest = R Sel_R Sel_ALU Load_R Load_Reg_Z ADD src = R Sel_R Sel_Bus_ Load_Reg_Y dest = R Sel_R Sel_ALU Load_R Load_Reg_Z SUB AND src = R2 Sel_R2 Sel_Bus_ Load_Reg_Y Sel_R3 Sel_Bus_ Load_Reg_Y dest = R2 Sel_R2 Sel_ALU Load_R2 Load_Reg_Z Sel_R3 Sel_ALU Load_R3 Load_Reg_Z... 7

18 Controller ASM: NOT S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Instruction Decode Execute S_dec 3 NOP src = R Sel_R Sel_Bus_ dest = R Load_R Sel_ALU Load_Reg_Z... src = R Sel_R Sel_Bus_ dest = R Load_R Sel_ALU Load_Reg_Z NOT src = R2 Sel_R2 Sel_Bus_ dest = R2 Load_R2 Sel_ALU Load_Reg_Z... Sel_R3 Sel_Bus_ Load_R3 Sel_ALU Load_Reg_Z 8

19 Controller ASM: RD S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Instruction Decode S_dec 3 Execute NOP Sel_PC Sel_Bus_ Load_Add_R 5 S_rd / Sel_Mem Load_Add_R Inc_PC S_rd2 6 dest = R Sel_Mem Load_R... dest = R Sel_Mem Load_R RD dest = R2 Sel_Mem Load_R2 Sel_Mem Load_R3... 9

20 Controller ASM: WR S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Instruction Decode S_dec 3 Execute NOP Sel_PC Sel_Bus_ Load_Add_R 7 S_wr / Sel_Mem Load_Add_R Inc_PC S_wr2 8 src = R Sel_R write... src= R Sel_R write WR src = R2 Sel_R2 write Sel_R3 write... 2

21 Controller ASM: BR/BRZ S_idle rst Instruction Fetch S_fet / Sel_PC Sel_Bus_, Load_Add_R S_fet2 / Sel_Mem, Load_IR, Inc_PC 2 Instruction Decode S_dec 3 Execute NOP Sel_PC Sel_Bus_ Load_Add_R 9 S_br / Sel_Mem Load_Add_R S_br2 Sel_Mem Load_PC... BR zero Inc_PC BRZ S_halt 2

22 Questions on RISC SPM Why not include memory as part of the processing unit? How could the design be simplified? 22

23 Testing RISC SPM Clear the memory Load the memory with a simple program and data Execute simple program Reads values from memory into registers Perform subtraction to decrement a loop counter Add register contents while executing the loop Branch to a halt when the loop index is Probe memory locations and control signals to ensure correct execution 23

24 System on Chip (SoC) 24

25 System on Chip cores Reusability portability flexibility Soft core Firm core Hard core Predictability, performance, time to market