Samar Abdi. (slides courtesy of A. Gerstlauer, D. Gajski and R. Doemer)
|
|
- Clinton Taylor
- 7 years ago
- Views:
Transcription
1 COEN 691B: Embedded System Design Lecture 1: Introduction, Course Logistics Samar Abdi (slides courtesy of A. Gerstlauer, D. Gajski and R. Doemer) Assistant Professor Electrical and Computer Engineering Concordia University
2 Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 2
3 Embedded Systems Systems that are part of a larger system Application-specific Diverse application areas Tight constraints Real-time, performance, power, size Cost, time-to-market, reliability Ubiquitous Far bigger market than generalpurpose computing (PCs, servers) $46 billion in 04, >$90 billion by 2010, 14% annual growth 4 billion devices in 04 98% of processors sold [Turley02, embedded.com] COEN 691B: Embedded System Design 3
4 System Design is hard COEN 691B: Embedded System Design 4
5 Logic transistors per chip (in millions) Productivity (K) Trans./Staff-Mo. and getting harder Growing system complexities Increasing application demands Networked and distributed Cyber-physical integration Increasingly programmable & customizable Technological advances Multi-Processor System-On-Chip (MPSoC) 10, ,000 1,000 10, IC capacity Gap Productivity Source: SEMATECH; Courtesy of: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 5
6 General-Purpose Computing Reaching physical limits of technology scaling Power/utilization/ walls and dark silicon Efficiency/optimality vs. flexibility/generality Opportunity and need for specialization Heterogeneous multi-core / Asynchronous CMP GP-GPUs COEN 691B: Embedded System Design 6
7 Processor Implementation Options Source: T. Noll, RWTH Aachen, via R. Leupers, From ASIP to MPSoC, Computer Engineering Colloquium, TU Delft, 2006 COEN 691B: Embedded System Design 7
8 Multi-Processor System-on-Chip (MPSoC) System Memory Memory Controller CPU GPU Local RAM Frontside Bus DSP DSP RAM Hardware Accelerator Bridge DSP Bus Shared RAM Hardware Accelerator Video Front End Local Bus COEN 691B: Embedded System Design 8
9 MPSoC Challenges Complexity High degree of parallelism at various levels High degree of design freedom Multiple optimization objectives design constraints Applications Programming Model? Heterogeneity Of components Processors, memories, busses Of design tasks Architecture, mapping, scheduling COEN 691B: Embedded System Design 9
10 Abstraction Accuracy Abstraction Levels Move to higher levels of abstraction [ITRS07, itrs.net] Electronic system-level (ESL) design Level Number of components System level Algorithm 1E0 1E1 1E2 RTL Gate Transistor 1E3 1E4 1E5 1E6 1E7 Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 10
11 Arbiter1 TX System-Level Design From specification Functionality, behavior Application algorithms Constraints To implementation Architecture Spatial and temporal order Components and connectivity Across hardware and software Design automation at the system level Modeling and simulation Synthesis Verification ARM MP3 IP Bridge DCTBus DCT DCT Jpeg BUS1 (AHB) M1 Requirements, constraints Proc Proc stripe MBUS M1Ctrl DMA Proc Proc System Design DSP I/O1 Enc Dec I/O2 Proc BUS2 (DSP) I/O3 HW Codebk I/O4 SI BO BI SO Implementation (HW/SW synthesis) COEN 691B: Embedded System Design 11
12 Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 12
13 Course Logistics Course website: Lectures: F, 17:45 20:15, MB-S2.285 Office hours: M, W 15:00 16:00, EV All lectures slides will be made available on course website Immediately after the class COEN 691B: Embedded System Design 13
14 No Final Exam Midterm (20%) November 11, in class Grading Fixed and no make-up test offered Programming assignments(40% total) Project (40%) All submissions must be made on EAS Login with ENCS account to COEN 691B: Embedded System Design 14
15 Programming Assignments Total four programming assignments To be done independently or in teams of two First assignment will be posted by next class SystemC modeling for embedded system specification Digital camera example (JPEG encoder) Original C model will be posted on course website this weekend All SystemC models will be refined stepwise from the original C model All models must be validated for functional correctness against the C model COEN 691B: Embedded System Design 15
16 Project Teams of 2-3 students allowed Possible project ideas will be listed on course website by next class Project goals Independent research or development project ES design example/case study for an application ES design automation tool Literature review, proposal, implementation Final report and presentation in publishable quality Project timeline Abstract (Submit by Sept. 30) Detailed problem definition and review of related work (present on October 28) Demonstration and final presentation (December 2) Final report (Submit by December 7) COEN 691B: Embedded System Design 16
17 Plagiarism Midterms, Programming Assignment and Projects require original work Strictly enforced All plagiarism cases will be reported Please refer to Concordia s code of conduct: COEN 691B: Embedded System Design 17
18 Textbooks Main textbook D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, 2009 ( orange book ) SystemC Reference T. Groetker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer, 2002 ( black book") Several online tutorials and examples available Additional reading material (papers) will be posted on the webpage as the course progresses COEN 691B: Embedded System Design 18
19 Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 19
20 Modeling A model: Abstraction of physical reality Mathematical formula, drawing/blueprint, data Core of any design process Specification Define (formally!) desired characteristics, golden reference Exploration Validate design choices Analysis and evaluation Static analysis Simulation/experiments Predict before the system is built Contract of what to build Detect problems early (and cheaply) Stimuli Model Simulator Results Correctness of model? Accuracy vs. simplicity COEN 691B: Embedded System Design 20
21 System Specification Capture requirements (what) Functional Free of any implementation details (not how) Non-functional Quality metrics Performance constraints Formal representation Models of computation Objects and compositions Concurrency and time Executable Analysis or simulation Application development Precise description of desired system behavior Complete and unambiguous P1 P2 d d Natural language Ambiguous Incomplete P3 P4 C1 C2 P5 COEN 691B: Embedded System Design 21
22 Arbiter Bridge System Architecture Processing elements (PEs) Processors General-purpose, programmable Digital signal processors (DSPs) Application-specific instruction set processor (ASIP) Custom hardware processors Intellectual property (IP) Memories CPU P1 CPU Bus P2 HW P3 P4 C1, C2 Mem C1, C2 IP P5 IP Bus Communication elements (CEs) Transducers, bus bridges I/O peripherals Busses Communication media Parallel, master/slave protocols Serial and network media Application mapping Allocation Partitioning Scheduling COEN 691B: Embedded System Design 22
23 System Implementation Hardware Microarchitecture Register-transfer level (RTL) Software binaries Application object code Real-time operating system (RTOS) Hardware abstraction layer (HAL) Interfaces Pins and wires Arbiters, muxes, interrupt controllers (ICs), etc. Bus protocol state machines CPU Arbiter Program HW EXE RTOS HAL IC Mem Bridge Specification for further manufacturing Logic synthesis Layout IP COEN 691B: Embedded System Design 23
24 Instruction-Set Simulator (ISS) Arbiter Bridge C1 System-Level Design Flow CPU Mem B1 B2 v1 Computation & Communication C2 HW Platform library IP System Synthesis Front-End B3 Application specification B4 System-Level Design Languages (SLDLs) Transaction-Level Models TLM n C/C++ code Software / Hardware Synthesis Back-End C-based RTL Software Object Code Hardware VHDL/Verilog COEN 691B: Embedded System Design 24
25 Models vs. Languages Models Poetry Recipe Story State Sequent. machine program Dataflow Languages English Spanish Japanese C C++ Java Recipes vs. English Sequential programs vs. C Computation models describe system behavior Conceptual notion, e.g., recipe, sequential program Languages capture models Concrete form, e.g., English, C Variety of languages can capture one model E.g., sequential program model C,C++, Java One language can capture variety of models E.g., C++ sequential program model, object-oriented model, state machine model Certain languages better at capturing certain models Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 25
26 Text vs. Graphics Models versus languages not to be confused with text versus graphics Text and graphics are just two types of languages Text: letters, numbers Graphics: circles, arrows (plus some letters, numbers) X = 1; if (N) Y = X + 1; X =1 N? Y = X + 1 Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 26
27 Simulation vs. Synthesis Ambiguous semantics of languages Finite state machine case X is when X1=>... when X2=> -- Look-up table Controller Memory Simulatable but not synthesizable or verifiable Impossible to automatically discern implicit meaning Need explicit set of constructs Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 27
28 Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 28
29 Design Flow Design methodology Sequence of design models Flow of transformations between models Models Well-defined, rigorous semantics Systematic flow from specification to implementation Languages Representation of models in machine-readable form COEN 691B: Embedded System Design 29
30 Evolution of Design Flows Capture & Simulate Describe & Synthesize Specify, Explore & Refine Specs Specs Executable Spec Functionality Algorithms Algorithms Algorithms Algorithms System Gap SW? SW? Architecture Network Connectivity Protocols Design Describe Design SW/HW Performance Simulate Logic Simulate Logic Logic Timing Physical Physical Physical Manufacturing Manufacturing Manufacturing 1960's 1980's 2000's Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 30
31 Models of Computation (MoCs) Y-Chart Behavior (Function) System Structure (Netlist) Processor Specification Algorithm Boolean logic (a v b) Logic Circuit PE,Bus RTL Gates Models of Structure (MoSs) Transfer Physical (Layout) Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 31
32 C W PC Status Processor Synthesis Software processor Compilation and linking Hardware processor High-level synthesis BB1 N IF Y C M em const B1... RF / Scratch pad B2 BB2 BB3 offset AG status ALU M U L M em ory address N Y IF Algorithm model (program) B3 Microarchitecture model (RTL) Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 32
33 A rb iter B rid g e Structure Partitioning, mapping System Synthesis Timing Scheduling C P U M em P1 P3 P 1 d P3 C 1 d P5 CPU Bus C 1, C 2 C 1, C 2 IP Bus P 2 P4 C 2 P2 P4 P5 HW IP Specification model (processes) Architecture model (TLM) Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 33
34 Bottom-Up Methodology Behavior (Function) System Processor Structure (Netlist) Each level generates library for the next higher level Circuit: Standard cells for logic level Logic: RTL components for processor level Processor: Processing and communication components for system level System: System platforms for different applications Floorplanning and layout on each level Start Logic Circuit Physical (Layout) PE,Bus RTL Gates Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 34
35 Top-down Methodology Behavior (Function) System Structure (Netlist) Start Functional description is converted into component netlist on each level Each component function is decomposed further on the next abstraction level Layout is given only for transistor components Physical (Layout) Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 35
36 Meet-in-the-Middle Methodology Behavior (Function) System Structure (Netlist) Gate netlist is hand-off Three levels of synthesis System is synthesized with processor components Processor components are synthesized with RTL library RTL components are synthesized with standard cells Two levels of layout System layout is performed with standard cells Standard cells layout with transistors Start Physical (Layout) Gates Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 36
37 Platform-Based Design Behavior (Function) Start System Processor Logic Circuit Structure (Netlist) Platform Meet-in-the-middle at the system level System platform with standard components System design reduced to mapping of specification onto pre-defined platform Physical (Layout) RTL Gates Transistors Source: D. Gajski, UC Irvine COEN 691B: Embedded System Design 37
38 System Modeling Basis of any design flow and design automation Inputs and outputs of design steps Capability to capture complex systems Precise, complete and unambiguous Models at varying levels of abstraction Level and granularity of implementation detail Speed vs. accuracy Design models as an abstraction of a design instance Representation of some aspect of reality Virtual prototyping for validation through simulation or formal analysis Specification for further implementation/synthesis Describe desired functionality Documentation & specification Abstraction to hide details that are not relevant or not yet known Different parts of the model or different use cases for the same model COEN 691B: Embedded System Design 38
39 Abstraction Levels unstructured High abstraction untimed Structure Implementation Detail Timing physical layout real time Spatial order Low abstraction Temporal order COEN 691B: Embedded System Design 39
40 Top-Down Design Flow requirements Product planning constraints pure functional Specification untimed System Design bus functional Architecture timing accurate Processor Design RTL / ISA Implementation cycle accurate gates Logic Design gate delays Structure Timing COEN 691B: Embedded System Design 40
41 Top-Down Design Flow requirements Product planning constraints pure functional Specification model untimed Computation design partitioned Timed model scheduled Communication design bus functional Transaction-level model timing accurate Processor design RTL / IS Implementation model cycle accurate Structure Logic design Timing COEN 691B: Embedded System Design 41
42 Top-Down Design Flow requirements Product planning constraints Capture Algor. IP pure functional Specification model untimed Computation refinement Comp. IP transaction level Timed model estimated timing Communication refinement Proto. IP bus functional Transaction-level model timing accurate RTL IP Hardware synthesis Interface synthesis Software synthesis RTOS IP RTL / IS Implementation model cycle accurate Structure Logic design Timing COEN 691B: Embedded System Design 42
43 Design Methodology System design Validation flow Capture Algor. IP Specification model Computation refinement Comp. IP Compilation Validation Analysis Estimation Simulation model Timed model Communication refinement Proto. IP Compilation Validation Analysis Estimation Simulation model Transaction-level model Compilation Validation Analysis Estimation Simulation model RTL IP Hardware synthesis Interface synthesis Software synthesis RTOS IP Backend Implementation model Compilation Validation Analysis Estimation Simulation model COEN 691B: Embedded System Design 43
44 Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 44
45 Languages Represent a model in machine-readable form Apply algorithms and tools Syntax defines grammar Possible strings over an alphabet Textual or graphical Semantics defines meaning Mapping onto an abstract state machine model Operational semantics Mapping into a mathematical domain (e.g. functions) Denotational semantics Semantic model vs. design models Basic semantic models can represent many design models Discrete event model for hardware and system simulation Design models can be represented in different languages COEN 691B: Embedded System Design 45
46 Evolution of Design Languages Netlists Structure only: components and connectivity Gate-level [EDIF], system-level [SPIRIT/XML] Hardware description languages (HDLs) Event-driven behavior: signals/wires, clocks Register-transfer level (RTL): boolean logic Discrete event [VHDL, Verilog] System-level design languages (SLDLs) Software behavior: sequential functionality/programs C-based, event-driven [SpecC, SystemC, SystemVerilog] COEN 691B: Embedded System Design 46
47 System-Level Design Languages (SLDLs) Goals Executability Validation through simulation Synthesizability Implementation in HW and/or SW Support for IP reuse Modularity Hierarchical composition Separation of concepts Completeness Support for all concepts found in embedded systems Orthogonality Orthogonal constructs for orthogonal concepts Minimality Simplicity Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 47
48 System-Level Design Languages Requirements (SLDLs) Behavioral hierarchy Structural hierarchy Concurrency Synchronization Exception handling Timing State transitions Composite data types not supported partially supported supported Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 48
49 System-Level Design Languages (SLDLs) C/C++ ANSI standard programming languages, software design Traditionally used for system design because of practicality, availability SystemC C++ API and class library Initially developed at UC Irvine, standard by Open SystemC Initiative (OSCI) SpecC C extension Developed at UC Irvine, standard by SpecC Technology Open Consortium (STOC) SystemVerilog Verilog with C extensions for testbench development Matlab/Simulink Specification and simulation in engineering, algorithm design Unified Modeling Language (UML) Software specification, graphical, extensible (meta-modeling) Modeling and Analysis of Real-time and Embedded systems (MARTE) profile IP-XACT XML schema for IP component documentation, standard by SPIRIT consortium Rosetta (formerly SLDL) Formal specification of constraints, requirements SDL Telecommunication area, standard by ITU Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 49
50 Separation of Concerns Fundamental principle in modeling of systems Clear separation of concerns Address separate issues independently System-Level Description Language (SLDL) Orthogonal concepts Orthogonal constructs System-level Modeling Computation encapsulated in modules / behaviors Communication encapsulated in channels Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 50
51 Computation vs. Communication Traditional model P1 s1 P2 Processes and signals Mixture of computation and communication Automatic replacement impossible s2 s3 Channel concept (OOP) B1 C1 v1 B2 v2 Tasks and channels Separation of computation and communication Plug-and-play v3 Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 51
52 Computation vs. Communication Protocol Inlining Specification model Exploration model B1 C1 v1 v2 B2 v3 Computation in behaviors Communication in channels Implementation model B1 v1 B2 v2 v3 Channel disappears Communication inlined Wires exposed Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 52
53 Intellectual Property (IP) Communication IP: Channel with wrapper C1 v1 v2 v3 replacable at any time C2 IP Virtual channel IP protocol channel in wrapper Protocol inlining with hierarchical channel B1 B2 B1 B2 v1 v1 v2 v2 before after Source: R. Doemer, UC Irvine COEN 691B: Embedded System Design 53
54 Lecture Outline What are Embedded Systems and why should we care? Course organization/policies ES modeling ES design methodologies Languages Case study for the programming assignments Intro to Real-Time Systems 54
55 Programming Assignment: Digital Camera Specification CCD Sensor SoC CCD Control pixel Jpeg Encoder bytes File I/O Flash Memory JpegEncoder Pixel 8x8 block 8x8 block 8x8 block Read DCT Quant Huff bytes COEN 691B: Embedded System Design 55
56 Pixel rows Charge-Coupled Device (CCD) Special sensor that captures an image Light-sensitive silicon solid-state device composed of many cells When exposed to light, each cell becomes electrically charged. This charge can then be converted to a 8-bit value where 0 represents no exposure while 255 represents very intense exposure of that cell to light. Some of the columns are covered with a black strip of paint. The light-intensity of these pixels is used for zerobias adjustments of all the cells. Lens area Covered columns Pixel columns Electromechanical shutter Electronic circuitry The electromechanical shutter is activated to expose the cells to light for a brief moment. The electronic circuitry, when commanded, discharges the cells, activates the electromechanical shutter, and then reads the 8-bit charge value of each cell. These values can be clocked out of the CCD by external logic through a standard parallel bus interface. Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 56
57 Compression JPEG (Joint Photographic Experts Group) Popular standard format for representing digital images in a compressed form Provides for a number of different modes of operation Mode used in this chapter provides high compression ratios using DCT (discrete cosine transform) Image data divided into blocks of 8 x 8 pixels 3 steps performed on each block DCT Quantization Huffman encoding Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 57
58 Discrete Cosine Transform (DCT) Transforms original 8 x 8 block into a cosinefrequency domain Upper-left corner values represent low frequency components Essence of image Lower-right corner values represent finer details Can reduce precision of these values and retain reasonable image quality FDCT (Forward DCT) formula C(h) = if (h == 0) then 1/sqrt(2) else 1.0 Auxiliary function used in main function F(u,v) F(u,v) = ¼ C(u) C(v) Σx=0..7 Σy=0..7 Dxy cos(π(2u + 1)u/16) cos(π(2y + 1)v/16) Gives encoded pixel at row u, column v Dxy is original pixel value at row x, column y Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 58
59 Quantization Achieve high compression ratio by reducing image quality Reduce bit precision of encoded data Fewer bits needed for encoding One way is to divide all values by a factor of 2 Simple right shifts can do this Dequantization would reverse process for decompression After DCT Divide each cell s value by After quantization Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 59
60 Huffman Encoding (ZigZag) Serialize 8 x 8 block of pixels Values are converted into single list using zigzag pattern Perform Huffman encoding More frequently occurring pixels assigned short binary code Longer binary codes left for less frequently occurring pixels Each pixel in serial list converted to Huffman encoded values Much shorter list, thus compression Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 60
61 Huffman Encoding (2) Pixel frequencies on left Pixel value 1 occurs 15 times Pixel value 14 occurs 1 time Build Huffman tree from bottom up Create one leaf node for each pixel value and assign frequency as node s value Create an internal node by joining any two nodes whose sum is a minimal value This sum is internal nodes value Repeat until complete binary tree Traverse tree from root to leaf to obtain binary code for leaf s pixel value Append 0 for left traversal, 1 for right traversal Huffman encoding is reversible No code is a prefix of another code Pixel frequency -1 15x 0 8x -2 6x 1 5x 2 5x 3 5x 5 5x -3 4x -5 3x -10 2x 144 1x -9 1x -8 1x -4 1x 6 1x 14 1x Huffman tree Huffman codes Source: T. Givargis, F. Vahid. Embedded System Design, Wiley COEN 691B: Embedded System Design 61
62 Programming Assignments 1. C model to a concurrent SystemC Process Network model 2. Timing measurement for individual tasks and creation of a timed model 3. Modeling the RTOS scheduling layer to determine performance of SW implementation 4. Modeling a HW-SW solution by moving the DCT to a faster HW module COEN 691B: Embedded System Design 62
63 What will you learn? How to model embedded systems? Models of computations: process and state-based System-level modeling language (SystemC) Concurrency, Timing, Scheduling, Communication How to predict performance of embedded systems? ISS-based, measurements and source-level timing analysis How to do hardware-software co-design? Partitioning and mapping of applications Synthesis of platforms How to ensure correctness of embedded systems? Formal verification and simulation techniques COEN 691B: Embedded System Design 63
64 Summary Embedded systems are pervasive, difficult to design, and have a huge market! Over $90 billion market for embedded processors Embedded SW deployed in billions of electronic products Embedded SW has become the major cost component in modern cars A model-based approach from specification to implementation is essential for success! COEN 691B: Embedded System Design 64
System-On Chip Modeling and Design A case study on MP3 Decoder
System-On Chip Modeling and Design A case study on MP3 Decoder Pramod Chandraiah, Hans Gunar Schirner, Nirupama Srinivas and Rainer Doemer CECS Technical Report 04-17 June 21, 2004 Center for Embedded
More informationDigital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
More informationArchitectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
More information7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
More informationAgenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
More informationCprE 588 Embedded Computer Systems Homework #1 Assigned: February 5 Due: February 15
CprE 588 Embedded Computer Systems Homework #1 Assigned: February 5 Due: February 15 Directions: Please submit this assignment by the due date via WebCT. Submissions should be in the form of 1) a PDF file
More informationEEM870 Embedded System and Experiment Lecture 1: SoC Design Overview
EEM870 Embedded System and Experiment Lecture 1: SoC Design Overview Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw Feb. 2013 Course Overview
More informationSystems on Chip Design
Systems on Chip Design College: Engineering Department: Electrical First: Course Definition, a Summary: 1 Course Code: EE 19 Units: 3 credit hrs 3 Level: 3 rd 4 Prerequisite: Basic knowledge of microprocessor/microcontroller
More informationWhat is a System on a Chip?
What is a System on a Chip? Integration of a complete system, that until recently consisted of multiple ICs, onto a single IC. CPU PCI DSP SRAM ROM MPEG SoC DRAM System Chips Why? Characteristics: Complex
More informationCodesign: The World Of Practice
Codesign: The World Of Practice D. Sreenivasa Rao Senior Manager, System Level Integration Group Analog Devices Inc. May 2007 Analog Devices Inc. ADI is focused on high-end signal processing chips and
More informationYAML: A Tool for Hardware Design Visualization and Capture
YAML: A Tool for Hardware Design Visualization and Capture Vivek Sinha, Frederic Doucet, Chuck Siska, Rajesh Gupta, Stan Liao, Abhijit Ghosh Center for Embedded Computer Systems, University of California,
More informationSystem-on. on-chip Design Flow. Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems. jouni.tomberg@tut.
System-on on-chip Design Flow Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems jouni.tomberg@tut.fi 26.03.2003 Jouni Tomberg / TUT 1 SoC - How and with whom?
More informationDesign and Verification of Nine port Network Router
Design and Verification of Nine port Network Router G. Sri Lakshmi 1, A Ganga Mani 2 1 Assistant Professor, Department of Electronics and Communication Engineering, Pragathi Engineering College, Andhra
More informationModeling a GPS Receiver Using SystemC
Modeling a GPS Receiver using SystemC Modeling a GPS Receiver Using SystemC Bernhard Niemann Reiner Büttner Martin Speitel http://www.iis.fhg.de http://www.iis.fhg.de/kursbuch/kurse/systemc.html The e
More informationIntroduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationTesting of Digital System-on- Chip (SoC)
Testing of Digital System-on- Chip (SoC) 1 Outline of the Talk Introduction to system-on-chip (SoC) design Approaches to SoC design SoC test requirements and challenges Core test wrapper P1500 core test
More informationİSTANBUL AYDIN UNIVERSITY
İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B1205.090015 Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER
More informationEingebettete Systeme. 4: Entwurfsmethodik, HW/SW Co-Design. Technische Informatik T T T
Eingebettete Systeme 4: Entwurfsmethodik, HW/SW Co-Design echnische Informatik System Level Design: ools and Flow Refinement of HW/SW Systems ools for HW/SW Co-Design C-based design of HW/SW Systems echnische
More informationMicroelectronic System-on-Chip Modeling using Objects and their Relationships
Microelectronic System-on-Chip Modeling using Objects and their Relationships Frederic Doucet, Rajesh K. Gupta {doucet, rgupta}@ics.uci.edu Center for Embedded Computer Systems University of California
More informationComputer Systems Structure Input/Output
Computer Systems Structure Input/Output Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Examples of I/O Devices
More informationTesting & Verification of Digital Circuits ECE/CS 5745/6745. Hardware Verification using Symbolic Computation
Testing & Verification of Digital Circuits ECE/CS 5745/6745 Hardware Verification using Symbolic Computation Instructor: Priyank Kalla (kalla@ece.utah.edu) 3 Credits Mon, Wed, 1:25-2:45pm, WEB L105 Office
More informationSystemC Tutorial. John Moondanos. Strategic CAD Labs, INTEL Corp. & GSRC Visiting Fellow, UC Berkeley
SystemC Tutorial John Moondanos Strategic CAD Labs, INTEL Corp. & GSRC Visiting Fellow, UC Berkeley SystemC Introduction Why not leverage experience of C/C++ developers for H/W & System Level Design? But
More informationBest Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
More informationPlatform-Based Design and the First Generation Dilemma Jiang Xu and Wayne Wolf
Platform-Based Design and the First Generation Dilemma Jiang Xu and Wayne Wolf Dept. of ELE, Princeton University Jiangxu, Wolf@ee.Princeton.edu Abstract In this paper, we analyze system-level design methodologies
More informationon-chip and Embedded Software Perspectives and Needs
Systems-on on-chip and Embedded Software - Perspectives and Needs Miguel Santana Central R&D, STMicroelectronics STMicroelectronics Outline Current trends for SoCs Consequences and challenges Needs: Tackling
More informationDesign Cycle for Microprocessors
Cycle for Microprocessors Raúl Martínez Intel Barcelona Research Center Cursos de Verano 2010 UCLM Intel Corporation, 2010 Agenda Introduction plan Architecture Microarchitecture Logic Silicon ramp Types
More informationImage Compression through DCT and Huffman Coding Technique
International Journal of Current Engineering and Technology E-ISSN 2277 4106, P-ISSN 2347 5161 2015 INPRESSCO, All Rights Reserved Available at http://inpressco.com/category/ijcet Research Article Rahul
More informationExample-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm Computer Technology /99 Overview Ultra-Low-Power
More informationElectronic system-level development: Finding the right mix of solutions for the right mix of engineers.
Electronic system-level development: Finding the right mix of solutions for the right mix of engineers. Nowadays, System Engineers are placed in the centre of two antagonist flows: microelectronic systems
More informationARM Webinar series. ARM Based SoC. Abey Thomas
ARM Webinar series ARM Based SoC Verification Abey Thomas Agenda About ARM and ARM IP ARM based SoC Verification challenges Verification planning and strategy IP Connectivity verification Performance verification
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationDigitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation
More informationIntroduction to System-on-Chip
Introduction to System-on-Chip COE838: Systems-on-Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
More informationSystem Modelingg Models of Computation and their Applications Axel Jantsch Laboratory for Electronics and Computer Systems (LECS) Royal Institute of Technology, Stockholm, Sweden February 4, 2005 System
More informationAims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic
Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go
More informationSDLC Controller. Documentation. Design File Formats. Verification
January 15, 2004 Product Specification 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-mail: info@cast-inc.com URL: www.cast-inc.com Features AllianceCORE
More informationSchool of Computer Science
School of Computer Science Computer Science - Honours Level - 2014/15 October 2014 General degree students wishing to enter 3000- level modules and non- graduating students wishing to enter 3000- level
More informationLesson 10:DESIGN PROCESS EXAMPLES Automatic Chocolate vending machine, smart card and digital camera
Lesson 10:DESIGN PROCESS EXAMPLES Automatic Chocolate vending machine, smart card and digital camera 1 Automatic Chocolate Vending Machine (ACVM) 2 Diagrammatic representation of ACVM Keypad for user Interface
More informationSerial port interface for microcontroller embedded into integrated power meter
Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia
More informationComputer Organization & Architecture Lecture #19
Computer Organization & Architecture Lecture #19 Input/Output The computer system s I/O architecture is its interface to the outside world. This architecture is designed to provide a systematic means of
More informationIntroduction to Embedded Systems. Software Update Problem
Introduction to Embedded Systems CS/ECE 6780/5780 Al Davis logistics minor Today s topics: more software development issues 1 CS 5780 Software Update Problem Lab machines work let us know if they don t
More informationChapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
More informationELEC 5260/6260/6266 Embedded Computing Systems
ELEC 5260/6260/6266 Embedded Computing Systems Spring 2016 Victor P. Nelson Text: Computers as Components, 3 rd Edition Prof. Marilyn Wolf (Georgia Tech) Course Topics Embedded system design & modeling
More informationAdvanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2
Lecture Handout Computer Architecture Lecture No. 2 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 2,Chapter3 Computer Systems Design and Architecture 2.1, 2.2, 3.2 Summary 1) A taxonomy of
More informationCAD TOOLS FOR VLSI. FLOORPLANNING Page 1 FLOORPLANNING
FLOORPLANNING Page 1 FLOORPLANNING Floorplanning: taking layout information into account at early stages of the design process. BEHAVIORAL D. STRUCTURAL D. Systems Algorithms Processors Register transfers
More informationContents. System Development Models and Methods. Design Abstraction and Views. Synthesis. Control/Data-Flow Models. System Synthesis Models
System Development Models and Methods Dipl.-Inf. Mirko Caspar Version: 10.02.L.r-1.0-100929 Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis
More informationInstruction Set Design
Instruction Set Design Instruction Set Architecture: to what purpose? ISA provides the level of abstraction between the software and the hardware One of the most important abstraction in CS It s narrow,
More informationNetworking Remote-Controlled Moving Image Monitoring System
Networking Remote-Controlled Moving Image Monitoring System First Prize Networking Remote-Controlled Moving Image Monitoring System Institution: Participants: Instructor: National Chung Hsing University
More informationMasters in Human Computer Interaction
Masters in Human Computer Interaction Programme Requirements Taught Element, and PG Diploma in Human Computer Interaction: 120 credits: IS5101 CS5001 CS5040 CS5041 CS5042 or CS5044 up to 30 credits from
More informationRAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
More informationSystem-on-Chip Design Verification: Challenges and State-of-the-art
System-on-Chip Design Verification: Challenges and State-of-the-art Prof. Sofiène Tahar Hardware Verification Group Concordia University Montréal, QC, CANADA MCSOC 12 Aizu-Wakamatsu, Fukushima, Japan September
More informationwhat operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored?
Inside the CPU how does the CPU work? what operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored? some short, boring programs to illustrate the
More informationMasters in Computing and Information Technology
Masters in Computing and Information Technology Programme Requirements Taught Element, and PG Diploma in Computing and Information Technology: 120 credits: IS5101 CS5001 or CS5002 CS5003 up to 30 credits
More informationMasters in Networks and Distributed Systems
Masters in Networks and Distributed Systems Programme Requirements Taught Element, and PG Diploma in Networks and Distributed Systems: 120 credits: IS5101 CS5001 CS5021 CS4103 or CS5023 in total, up to
More informationA SoC design flow based on UML 2.0 and SystemC
A SoC design flow based on UML 2.0 and SystemC Sara Bocchio 1, Elvinia Riccobene 2, Alberto Rosti 1, and Patrizia Scandurra 3 1 STMicroelectronics, AST Agrate Lab R&I, Italy {sara.bocchio, alberto.rosti}@st.com
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationMPSoC Virtual Platforms
CASTNESS 2007 Workshop MPSoC Virtual Platforms Rainer Leupers Software for Systems on Silicon (SSS) RWTH Aachen University Institute for Integrated Signal Processing Systems Why focus on virtual platforms?
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationMemory Systems. Static Random Access Memory (SRAM) Cell
Memory Systems This chapter begins the discussion of memory systems from the implementation of a single bit. The architecture of memory chips is then constructed using arrays of bit implementations coupled
More informationMaking Multicore Work and Measuring its Benefits. Markus Levy, president EEMBC and Multicore Association
Making Multicore Work and Measuring its Benefits Markus Levy, president EEMBC and Multicore Association Agenda Why Multicore? Standards and issues in the multicore community What is Multicore Association?
More informationHigh-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
More informationMasters in Advanced Computer Science
Masters in Advanced Computer Science Programme Requirements Taught Element, and PG Diploma in Advanced Computer Science: 120 credits: IS5101 CS5001 up to 30 credits from CS4100 - CS4450, subject to appropriate
More informationProduct Development Flow Including Model- Based Design and System-Level Functional Verification
Product Development Flow Including Model- Based Design and System-Level Functional Verification 2006 The MathWorks, Inc. Ascension Vizinho-Coutry, avizinho@mathworks.fr Agenda Introduction to Model-Based-Design
More informationMasters in Artificial Intelligence
Masters in Artificial Intelligence Programme Requirements Taught Element, and PG Diploma in Artificial Intelligence: 120 credits: IS5101 CS5001 CS5010 CS5011 CS4402 or CS5012 in total, up to 30 credits
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 4717 Computer Architecture TEST 2 for Fall Semester, 2006 Section
More informationExtending the Power of FPGAs. Salil Raje, Xilinx
Extending the Power of FPGAs Salil Raje, Xilinx Extending the Power of FPGAs The Journey has Begun Salil Raje Xilinx Corporate Vice President Software and IP Products Development Agenda The Evolution of
More informationTLM-2.0 in Action: An Example-based Approach to Transaction-level Modeling and the New World of Model Interoperability
DVCon 2009 TLM-2.0 in Action: An Example-based Approach to Transaction-level Modeling and the New World of Model Interoperability John Aynsley, Doulos TLM Introduction CONTENTS What is TLM and SystemC?
More informationTopics. Introduction. Java History CS 146. Introduction to Programming and Algorithms Module 1. Module Objectives
Introduction to Programming and Algorithms Module 1 CS 146 Sam Houston State University Dr. Tim McGuire Module Objectives To understand: the necessity of programming, differences between hardware and software,
More informationBachelor of Games and Virtual Worlds (Programming) Subject and Course Summaries
First Semester Development 1A On completion of this subject students will be able to apply basic programming and problem solving skills in a 3 rd generation object-oriented programming language (such as
More informationOutline. Introduction. Multiprocessor Systems on Chip. A MPSoC Example: Nexperia DVP. A New Paradigm: Network on Chip
Outline Modeling, simulation and optimization of Multi-Processor SoCs (MPSoCs) Università of Verona Dipartimento di Informatica MPSoCs: Multi-Processor Systems on Chip A simulation platform for a MPSoC
More informationECE 156A - Syllabus. Lecture 0 ECE 156A 1
ECE 156A - Syllabus Lecture 0 ECE 156A 1 Description Introduction to HDL basic elements, HDL simulation concepts, HDL concurrent statements with examples and applications, writing HDL for synthesis, and
More informationElectronic systems prototyping: Tools and methodologies for a better observability.
Electronic systems prototyping: Tools and methodologies for a better observability. In an electronic system development flow, a prototyping phase is very diversely valued by the electronic system engineer
More informationEmbedded Systems. introduction. Jan Madsen
Embedded Systems introduction Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard Petersens Plads, Building 321 DK2800 Lyngby, Denmark jan@imm.dtu.dk Wireless Sensor
More informationDecomposition into Parts. Software Engineering, Lecture 4. Data and Function Cohesion. Allocation of Functions and Data. Component Interfaces
Software Engineering, Lecture 4 Decomposition into suitable parts Cross cutting concerns Design patterns I will also give an example scenario that you are supposed to analyse and make synthesis from The
More informationChapter 1 Computer System Overview
Operating Systems: Internals and Design Principles Chapter 1 Computer System Overview Eighth Edition By William Stallings Operating System Exploits the hardware resources of one or more processors Provides
More informationSeeking Opportunities for Hardware Acceleration in Big Data Analytics
Seeking Opportunities for Hardware Acceleration in Big Data Analytics Paul Chow High-Performance Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Toronto Who
More informationCHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
More informationNew Methodologies in Smart Card Security Design. Y.GRESSUS Methodology and Secure ASIC development manager, Bull CP8
New Methodologies in Smart Card Security Design Y.GRESSUS Methodology and Secure ASIC development manager, Bull CP8 Japan Security Conference Page 2 Trends Opportunities New methodologies Summary Concurrent
More informationINTRODUCTION TO DIGITAL SYSTEMS. IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE
INTRODUCTION TO DIGITAL SYSTEMS 1 DESCRIPTION AND DESIGN OF DIGITAL SYSTEMS FORMAL BASIS: SWITCHING ALGEBRA IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE COURSE EMPHASIS:
More informationSoftware Engineering
Software Engineering Lecture 06: Design an Overview Peter Thiemann University of Freiburg, Germany SS 2013 Peter Thiemann (Univ. Freiburg) Software Engineering SWT 1 / 35 The Design Phase Programming in
More informationMICROPROCESSOR AND MICROCOMPUTER BASICS
Introduction MICROPROCESSOR AND MICROCOMPUTER BASICS At present there are many types and sizes of computers available. These computers are designed and constructed based on digital and Integrated Circuit
More informationIn-Memory Databases Algorithms and Data Structures on Modern Hardware. Martin Faust David Schwalb Jens Krüger Jürgen Müller
In-Memory Databases Algorithms and Data Structures on Modern Hardware Martin Faust David Schwalb Jens Krüger Jürgen Müller The Free Lunch Is Over 2 Number of transistors per CPU increases Clock frequency
More informationIEC 61131-3. The Fast Guide to Open Control Software
IEC 61131-3 The Fast Guide to Open Control Software 1 IEC 61131-3 The Fast Guide to Open Control Software Introduction IEC 61131-3 is the first vendor-independent standardized programming language for
More informationA Generic Network Interface Architecture for a Networked Processor Array (NePA)
A Generic Network Interface Architecture for a Networked Processor Array (NePA) Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, and Nader Bagherzadeh EECS @ University of California, Irvine Outline Introduction
More informationESE566 REPORT3. Design Methodologies for Core-based System-on-Chip HUA TANG OVIDIU CARNU
ESE566 REPORT3 Design Methodologies for Core-based System-on-Chip HUA TANG OVIDIU CARNU Nov 19th, 2002 ABSTRACT: In this report, we discuss several recent published papers on design methodologies of core-based
More informationDigital Design Verification
Digital Design Verification Course Instructor: Debdeep Mukhopadhyay Dept of Computer Sc. and Engg. Indian Institute of Technology Madras, Even Semester Course No: CS 676 1 Verification??? What is meant
More informationIntel CoFluent Methodology for SysML *
Intel CoFluent Methodology for SysML * UML* SysML* MARTE* Flow for Intel CoFluent Studio An Intel CoFluent Design White Paper By Thomas Robert and Vincent Perrier www.cofluent.intel.com Acronyms and abbreviations
More informationARM Microprocessor and ARM-Based Microcontrollers
ARM Microprocessor and ARM-Based Microcontrollers Nguatem William 24th May 2006 A Microcontroller-Based Embedded System Roadmap 1 Introduction ARM ARM Basics 2 ARM Extensions Thumb Jazelle NEON & DSP Enhancement
More informationCS 3530 Operating Systems. L02 OS Intro Part 1 Dr. Ken Hoganson
CS 3530 Operating Systems L02 OS Intro Part 1 Dr. Ken Hoganson Chapter 1 Basic Concepts of Operating Systems Computer Systems A computer system consists of two basic types of components: Hardware components,
More informationEastern Washington University Department of Computer Science. Questionnaire for Prospective Masters in Computer Science Students
Eastern Washington University Department of Computer Science Questionnaire for Prospective Masters in Computer Science Students I. Personal Information Name: Last First M.I. Mailing Address: Permanent
More informationSoftware-Programmable FPGA IoT Platform. Kam Chuen Mak (Lattice Semiconductor) Andrew Canis (LegUp Computing) July 13, 2016
Software-Programmable FPGA IoT Platform Kam Chuen Mak (Lattice Semiconductor) Andrew Canis (LegUp Computing) July 13, 2016 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform
More informationLesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
More informationUniversity of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design
University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents
More information(Refer Slide Time: 02:39)
Computer Architecture Prof. Anshul Kumar Department of Computer Science and Engineering, Indian Institute of Technology, Delhi Lecture - 1 Introduction Welcome to this course on computer architecture.
More informationAn Introduction to Computer Science and Computer Organization Comp 150 Fall 2008
An Introduction to Computer Science and Computer Organization Comp 150 Fall 2008 Computer Science the study of algorithms, including Their formal and mathematical properties Their hardware realizations
More informationDesigning Real-Time and Embedded Systems with the COMET/UML method
By Hassan Gomaa, Department of Information and Software Engineering, George Mason University. Designing Real-Time and Embedded Systems with the COMET/UML method Most object-oriented analysis and design
More informationDesign of a High Speed Communications Link Using Field Programmable Gate Arrays
Customer-Authored Application Note AC103 Design of a High Speed Communications Link Using Field Programmable Gate Arrays Amy Lovelace, Technical Staff Engineer Alcatel Network Systems Introduction A communication
More informationSoftware Engineering for Real- Time Systems.
Software Engineering for Real- Time Systems. Presented by Andrew Dyer-Smith and Jamie McClelland Overview What are Real-Time Systems. Requirements of Real-Time Systems Current Technology Construction 1
More informationContents. Introduction. Introduction and Motivation Embedded Systems (ES) Content of Lecture Organisational
Introduction Dipl.-Inf. Mirko Caspar Version: 10.01.V.r-1.0-100928 Contents Introduction and Motivation Embedded Systems (ES) characterisation mechatronics requirements classification Content of Lecture
More information