BORANG PENGESAHAN STATUS TESIS υ JUDUL:

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1 PSZ 19:16 (Pind. 1/97) UNIVERSITI TEKNOLOGI MALAYSIA BORANG PENGESAHAN STATUS TESIS υ JUDUL: VLSI IMPLEMENTATION OF PHASE LOCKED LOOP FOR PHYSICAL LAYER 10MBPS ETHERNET SESI PENGAJIAN: 2007 / 2008 Saya MUHAMAD HANIF BIN HASHIM (HURUF BESAR) mengaku membenarkan tesis (PSM/Sarjana/Doktor Falsafah)* ini disimpan di Perpustakaan Universiti Teknologi Malaysia dengan syarat-syarat kegunaan seperti berikut: 1. Tesis adalah hakmilik Universiti Teknologi Malaysia. 2. Perpustakaan Universiti Teknologi Malaysia dibenarkan membuat salinan untuk tujuan pengajian sahaja. 3. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi. 4. **Sila tandakan ( ) SULIT (Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972) TERHAD (Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan) TIDAK TERHAD Disahkan oleh (TANDATANGAN PENULIS) (TANDATANGAN PENYELIA) Alamat Tetap: NO 20B, KAMPUNG CABANG LIMA TANJUNG MALIM PERAK ISMAHANI BINTI ISMAIL Nama Penyelia Tarikh: 03 DISEMBER 2007 Tarikh: 03 DISEMBER 2007 CATATAN: * Potong yang tidak berkenaan. ** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini perlu dikelaskan sebagai SULIT atau TERHAD. υ Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah dan Sarjana secara penyelidikan, atau disertasi bagi pengajian secara kerja kursus dan penyelidikan, atau Laporan Projek Sarjana Muda (PSM).

2 I declare that I have read this thesis and in my opinion, it is suitable in terms of scope and quality for the purpose of awarding a Bachelor Degree in Electrical (Computer) Engineering. Signature : Name of Supervisor : PUAN ISMAHANI BINTI ISMAIL Date : 03 DECEMBER 2007

3 VLSI Implementation of Phase Locked Loop for Physical Layer 10Mbps Ethernet MUHAMAD HANIF BIN HASHIM A thesis submitted for the degree of Bachelor of Computer Engineering Faculty of Electrical Engineering Universiti Teknologi Malaysia DECEMBER 2007

4 ii Hereby, I declare that this thesis entitled, VLSI Implementation of Phase Locked Loop for Physical Layer 10Mbps Ethernet is a result of my own research and idea except for the works that have been early cited in the reference. Signature :. Name : MUHAMAD HANIF BIN HASHIM Date : 03 DECEMBER 2007

5 iii Dedicated in thankful appreciation for support, encouragement and understandings to my beloved father, brothers and sister.

6 iv ACKNOWLEDGEMENT First and foremost, my special thanks goes to all people who have provide me with the input, suggestion, technical knowleged and support to carry out this project. This is especially to my supervisor, Puan Ismahani binti Ismail, for her patient, effort and guide. I also grab this opportunity to thank En.Zulfakar bin Aspar for giving the advices, knowledge and sharing his experiences. Your helps are greatly appreciated. Through this great chance, I am really grateful to my family for their support and understanding. I would like to wish thank you for all members for their encouragement and supports. Thanks for always being there when I need help. Indeed, without their everlasting support, I cannot independently survive with this new environment. Thank you very much. Your sincere help will be remembered for life.

7 v ABSTRACT Phase locked loop (PLL) is one of the important circuit elements in communications. For Ethernet physical layer, PLL is used in the clock and data recovery to recover clock for data stream. In this project, a 2.5MHZ phase locked loop that be implemented in 0.25µm CMOS process technology is presented. This PLL consists of phase detector (PD), loop filter and voltage controlled oscillator as its functional building blocks. An exclusive-or phase detector is used as the phase detector in this project. Overall, the PLL implementation is only needs about 259 transistors which require less area and less power consumption. The circuit simulation for this project is carried out using Tanner Tool.

8 vi ABSTRAK Gelung fasa terkunci merupakan salah satu elemen litar yang penting di dalam bidang perhubungan. Untuk Ethernet physical layer, gelung fasa terkunci digunakan di dalam blok pemulihan jam/masa dan data untuk memulihkan masa bagi arus data. Di dalam projek ini, sebuah 2.5MHz gelung fasa terkunci yang diimplementasikan berdasarkan proses teknologi CMOS 0.25µm telah ditunjukkan. Gelung fasa terkunci ini mengandungi pengesan fasa, penapis gelung dan pengayun kawalan voltan yang berfungsi sebagai blok teras. Sebuah pengesan fasa jenis esklusif-atau digunakan sebagai.pengesan fasa di dalam projek ini. Secara keseluruhan implementasi gelung fasa terkunci ini hanya memerlukan kira-kira 254 buah transistor yang memerlukan keluasan yang kecil dan penggunaan kuasa yang rendah. Simulasi litar bagi projek ini dilakukan menggunakan Tanner Tool.

9 vii TABLE OF CONTENTS CHAPTER TITLE PAGE DECLARATION DEDICATION ACKNOWLEDGEMENT ABSTRACT ABSTRAK TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS LIST OF APPENDICES ii iii iv v vi vii x xi xii xiii CHAPTER 1 INTRODUCTION Project Introduction Project Objectives Scope of Project Problem Statement Project Plan 5

10 viii CHAPTER 2 LITERATURE REVIEW History of PLL Description of Functionality PLL 8 Components 2.3 Purpose of PLL PLL Sub Blocks Review Phase Detector Exclusive-OR 10 Type Loop Filter Passive Low Pass 11 Filter Voltage Controlled Oscillator 13 (VCO) Ring Oscillator Multistage Oscillator PLL Basic Concept Classification of PLL Types Software Used Tanner Tool Professional S-EDIT T-SPICE W-EDIT 21 CHAPTER 3 METHODOLOGY Research and Study Methodology Design Methodology Simulation Methodology 30

11 ix CHAPTER 4 SIMULATION RESULT Introduction Exclusive-OR Type Phase Detector Phase Locked Loop Simulation Result 33 CHAPTER 5 CONCLUSION AND FUTURE WORK Conclusion Recommendation Future Work 37 REFERENCES 38 APPENDIX A-C 39

12 x LIST OF TABLES NO. OF TABLES TITLE PAGE Table 2.2 Exclusive-OR phase detector truth table 11 Table 4.1 Truth table for Exclusive-OR gate 33

13 xi LIST OF FIGURES NO. OF FIGURES TITLE PAGE Figure 1.1 The physical layer block diagram 4 Figure 1.2 Gantt chart for PSM 1 5 Figure 1.3 Gantt chart for PSM 2 6 Figure 2.1 A general PLL block diagram 8 Figure 2.2 Exclusive-OR gates 11 Figure 2.3 Passive loop filter 12 Figure 2.4 Bode diagram for a passive loop filter 12 Figure 2.5 Ring oscillator 14 Figure 2.6 VCO delay cell 16 Figure 3.1 The overall methodology steps for the project 22 Figure 3.2 Exclusive-OR phase detector at transistor level 24 Figure 3.3 SPICE NETLIST of Exclusive-OR Phase Detector 25 Figure 3.4 Passive low pass filter schematic 26 Figure 3.5 VCO in transistor level 28 Figure 3.6 Part of SPICE NETLIST for VCO 29 Figure 4.1 Exclusive-OR phase detector simulation result 32 Figure 4.2 Block diagram of PLL 33 Figure 4.3 Simulation result for PLL 33 Figure 4.4 Part of the output signal for the PLL 35

14 xii LIST OF ABBREVIATIONS VLSI - Very Large Scale Integration MOS - Metal-oxide semiconductor CMOS - Complementary-MOS NMOS - Negative-MOS PMOS - Positive-MOS PLL - Phase Locked Loop PD - Phase Detector VCO - Voltage Controlled Oscillator

15 xiii LIST OF APPENDICES APPENDIX TITLE PAGE A Model File of 0.25microns CMOS 39 Technology B SPICE NETLIST for VCO 41 C SPICE NETLIST for Phase Locked Loop 51

16 1 CHAPTER 1 INTRODUCTION 1.1 Project Introduction This project is to design a Phase Locked Loop (PLL) for physical layer 10Mbps Ethernet using VLSI implementation. The physical layer is level one in the seven level OSI model of computer networking. It performs services requested by the data link layer. This level refers to network hardware, physical cabling or a wireless electromagnetic connection. The physical layer is the most basic network layer, providing only the means of transmitting raw bits. The shapes of the electrical connectors, which frequencies to broadcast on, and similar low-level things are specified here. In physical layer, the PLL is used in clock and data recovery to recover the data clock. In this project, the PLL that will be design is a digital phase locked loop.

17 2 1.2 Project Objectives The main objective of this project is to design and simulate a PLL using VLSI implementation. To complete the main objective, another some smaller objectives must accomplish. These smaller objectives are: 1. To design a phase detector using Tanner Tool. 2. To design a loop filter using Tanner Tool. 3. To design a voltage controlled oscillator (VCO) using Tanner Tool. 1.3 Scope of Project This project is to design a PLL that can generate a clock signal which is locked at 2.5MHz. This because for physical layer 10Mbps Ethernet, the recovered clock is 2.5MHz. Beside that, the 0.25µm CMOS technology is used to implement the design. The circuit is simulates using Tanner Tool, but only S-EDIT, T-SPICE and W-EDIT are used.

18 3 1.4 Problem Statement The block diagram of physical layer is shown in Figure 1.1 below. It is the physical layer that operates in the 10BASE-T mode at 10 Mbits/s.10 Mbits/s mode uses two of category 3 or better UTP or STP twisted-pair cable with Manchester encoded 10 MHz binary data. This physical layer is using the Ethernet communication specification. In the block diagram, there is a block called Clock and Data Recovery (Manchester Decoder) block. In this block, it used a PLL to recover the data clock. The PLL for this block has to generate the clock signal which locked at 2.5MHz. The problem statement for this project is the previous projects that design a PLL using an old model file like 1.2micron CMOS technology. Beside that, the previous PLL cannot be implemented to the physical layer 10Mbps because of the operating frequency is too large. To overcome these problems, in this project, the design will be implemented in 0.25µm CMOS process technology and also can operate at the desired frequency that the physical layer wants which is 2.5 MHz.

19 4 Phase locked loop Figure 1.1: The physical layer block diagram

20 5 1.5 Project Plan For the project plan, it is divided for two semesters. Figures below show the Gantt chart for PSM 1 and PSM 2. Figure 1.2: Gantt chart for PSM 1

21 Figure 1.3: Gantt chart for PSM 2 6