Video and Image Processing Component Library

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1 Video and Image Processing Component Library AN-654 Application Note This application note describes the Video and Image Processing Component Library. Altera uses these components to make the 4K Format Conversion Reference Design and the Multioutput Scalar Reference Design. The Video and Image Processing Component Library is a collection of IP cores that simplify developing complex video processing algorithms or systems. The Video and Image Processing Component Library is available in the Qsys tool in the Quartus II software version 11.0 and later and includes the following IP cores: Avalon-MM Control Slave Packet Duplicator Packet Multiplexer Packet Reader Packet Writer Scaler Algorithmic Core Scaler Kernel Creator Video Input Bridge Video Line Buffer Video Output Bridge The IP cores in the Video and Image Processing Component Library have standardized interface protocols for control and data transfer that you can connect together to form individual IP cores or complex processor-controlled systems that use the algorithmic processors as hardware accelerators. Altera uses the IP cores in the Video and Image Processing Components Library to build the IP cores in the Video and Image Processing Suite. This document only describes the Video and Image Processing Component IP cores. f f For more information about the Video and Image Processing Suite, refer to the Video and Image Processing Suite User Guide. For more information about the video reference designs that use the Video and Image Processing Suite IP cores, refer to AN 627: High Definition Video Reference Design. 101 Innovation Drive San Jose, CA Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered January 2012 Altera Corporation Subscribe

2 Page 2 Table 1 lists the advantages and disadvantages for video reference designs that use IP cores from the Video and Image Processing Suite. Table 1. Video Framework Advantages and Disadvantages Feature Advantage Disadvantage Distributed control Point-to-point dataflow Frame-based granularity Pipeline per video stream Each algorithmic processor has a control port, which you can use to start, stop, and configure the IP core. When the IP core runs, it autonomously takes in frames of video from its input, processes and outputs them. The connections between the algorithmic processors are mainly fixed. Video streams progress through the system along set paths. Each algorithmic processor processes a full frame of video before checking the configuration. Some IP cores require the following frames to be from the same video source. Therefore, you cannot use a single IP core to process multiple video streams. Each video stream has its own processing functions (Figure 1). Simplifies control software (no scheduling) Low processor overhead Simplifies system design Minimal connection overhead Simplifies algorithm design Lowers control overhead Easy to create a pipeline for each video stream to process. Difficult to perform complex on-screen display (OSD) synchronization, which requires control blocks inserted into datapath Difficult to share buffers or algorithmic processors Difficult to implement time-division multiplexed (TDM) designs, which use one function running at a higher f MAX to process multiple video streams Requires more external memory Limited flexibility. Does not allow an array of algorithmic processors and buffers to process multiple video streams more efficiently Video and Image Processing Component Library January 2012 Altera Corporation

3 Features Page 3 Figure 1. Video Stream Processing Functions Figure 1 shows video stream processing functions. Buffer 1 Buffer 2 Video Input 1 Controller Controller Video Output 1 Algorithmic Processor 1 Algorithmic Processor 2 Buffer 1 Buffer 2 Video Input 2 Controller Controller Video Output 2 Algorithmic Processor 1 Algorithmic Processor 2 Features The IP cores in the video and image processing component library do not have the disadvantages listed in Table 1. The IP cores in the video and image processing component library offer the following features: Flexible systems that ease complex synchronization, sharing of buffers and TDM designs, while still allowing you to create simple point-to-point systems. Improved scalability of video designs to achieve the faster frame rates and higher resolutions of emerging video standards while maintaining a simple architecture. Rapid design and implementation of algorithmic processors by removing the duplication of common components, for example, buffering and control. By using standard interfaces and a library of prewritten components, the algorithm designer can focus on the unique parts of the algorithm and create those parts to be reusable by other algorithms. Standard interfaces and tools for debugging video systems. All of these features are enabled by separating the functions of the Altera IP cores into the following components: Algorithmic processors. The main function of the system is to process video in some way, for example, scaling or deinterlacing. You can implement the algorithm processor in software or with hardware accelerating IP cores. January 2012 Altera Corporation Video and Image Processing Component Library

4 Page 4 Design Example Buffers. Most algorithmic processors require some buffers, either on-chip or in external memory, for example line buffers, frame buffers, or simple FIFO buffers. Separating these buffers from the algorithmic processors allows you to share buffers between IP cores and reuse common components. Controllers, which manage the following different parts of the system: Schedulers Algorithmic processors Buffers Routers Routers. A router enables you to transfer video packets between algorithmic processors and buffers. You can use static point-to-point transfers, which restrict the flow of data to a fixed path, or you can create a more flexible system by adding destination IDs to the packets and use a packet router to connect IP cores to multiple source and sink interfaces. Reducing the granularity of the video packets from a frame to a line or in some cases pixels increases the scheduling options and, in some cases, reduces the need for large external frame buffers. Figure 2 shows the video stream processing functions. Figure 2. Video Stream Processing Functions with Router Buffer Buffer Video Input Video Input Routers Video Output Video Output Controller Algorithmic Processor Algorithmic Processor Design Example Figure 3 shows a design example that scales a video stream. The example uses the Avalon Streaming (Avalon-ST) Video protocol for inputs and outputs. Video and Image Processing Component Library January 2012 Altera Corporation

5 Design Example Page 5 f For more information about the Avalon-ST Video protocol, refer to the Video and Image Processing Suite User Guide. Figure 3. Design Example Video Line Buffer 1 Video Line Buffer 2 Data Input 1 Data Input 2 Video Input Bridge 1 Video Input Bridge 2 Packet Router Video Output Bridge 1 Video Output Bridge 2 Video Output Bridge 3 Data Output 1 Data Output 2 Data Output 3 Scaler Kernel Creator Scheduler Scaler Algorithmic Core 1 Scaler Algorithmic Core 2 The design example includes the following components from the Video and Image Processing Component Library: Packet Router Scaler Algorithmic Core Scaler Kernel Creator Scheduler Video Input Bridge and Video Output Bridge Video Line Buffer f For full information about each component, refer to Component List on page 15. Packet Router You can use the Packet Duplicator and the Packet Multiplexer to create a packet router. Alternatively, use a generic packet switch that handles the routing of packets between components. Packets have a control word that includes a destination ID that the packet router can decode, to route the packet to the correct destination. January 2012 Altera Corporation Video and Image Processing Component Library

6 Page 6 Design Example The Packet Multiplexer services one of its two or more sink interfaces on a first-come-first-served or command-driven basis. It applies backpressure to hold off the other interfaces. The Packet Multiplexer next processes the pending packets on the sink interface that it is currently holding off. The Packet Multiplexer allows two or more components to connect a source interface to a shared sink interface (for example a Video Line Buffer and a Scalar Algorithmic Core each connect a source interface to one Video Output Bridge). The Packet Duplicator receives incoming packets on sink interfaces and transmits them to two or more independent source outputs. A small FIFO buffer drives each source interface to allow you to backpressure the Packet Duplicator's source interface. Scaler Algorithmic Core The Scalar Algorithmic Core streams in video data kernels and a command packet for configuration, processes the video data kernels, and streams out a new video data kernel (with a new header on the front to route the data to the correct place). The processing granularity should be less than a frame, typically a line or a part of a line. Scaler Kernel Creator Scheduler This component assists the scheduler to create commands that need to be sent to the Scaler Algorithmic Core to create an output line. All systems with video and image processing component library IP cores require a scheduler. The scheduler controls the system, instructing the other components to transfer or process data packets. The scheduler can be an HDL finite state machine (FSM), Nios II processor, or any other processor. However, it must be able to use the Avalon-ST Message protocol to send and receive messages. Typically, complex systems use a software schedule running on a processor. to allow you to create different systems without rewriting the scheduler. Video Input Bridge and Video Output Bridge The Video Input Bridge and the Video Output Bridge convert between the Avalon-ST Video and Avalon-ST Message protocols. Video Line Buffer Dataflow The Video Line Buffer allows the design to store one or more lines, to be forwarded together. The Video Line Buffer has data outputs that you can configure and use to transfer line data to other components, when requested. It has one data input to receive line data. This section describes the flow of data and control packets through the design example. Video and Image Processing Component Library January 2012 Altera Corporation

7 Design Example Page 7 1. When a new video frame begins at input 1 or input 2 the relevant Video Input Bridge sends a message to the scheduler to indicate the start of frame. The scheduler sends three messages to the Scaler Kernel Creator to initialize a new output frame for each of the three outputs. It also sends a message to each of the three Video Output Bridges instructing them to each start a new output frame. The scheduler sends three additional messages to the Scaler Kernel Creator to query which input lines are required in the Video Line Buffers for the first line of each output. The Scaler Kernel Creator generates three responses to provide this information to the scheduler. 2. For every new line each Video Input Bridge receives, it sends a message to the scheduler to indicate that a new line is pending. The incoming video data is held off until the scheduler sends a message back to the Video Input Bridge to instruct it where to send the data. The scheduler instructs Video Input Bridge 1 to send the new line data to Video Line Buffer 1, and instructs Video Line Buffer 1 to receive the data. The scheduler instructs Video Input Bridge 2 to send the new line data to Video Line Buffer 2, and instructs Video Line Buffer 2 to receive the data. 3. The scheduler keeps a count of which lines are in each Video Line Buffer. When Video Line Buffer 1 contains the correct lines required to generate the next line of output 1, the scheduler sends a message to Video Line Buffer 1 to tell it to send its stored data to Scaler Algorithmic Core 1. The scheduler sends a message to Scaler Algorithmic Core 1, telling it to downscale the data by 2x and send the result to Video Output Bridge 1. The scheduler instructs Video Output Bridge 1 to stream the data out as part of the current frame. The scheduler also sends a message to the Scaler Kernel Creator to request information about which lines are required in Video Line Buffer 1, to create the next line of output 1. The Scaler Kernel Creator replies with the requested information, and this process repeats when Video Line Buffer 1 again contains the required lines. 4. When Video Line Buffer 2 constrains the lines required for output 3 the scheduler performs the following actions: a. If Video Line Buffer 2 contains the correct lines for output 3 but not output 2, the scheduler instructs Video Line Buffer 2 to send its current data to Scaler Algorithmic Core 2. It also instructs Scaler Algorithmic Core 2 to upscale the incoming data and send the result to Video Output Bridge 3. The scheduler instructs Video Output Bridge 3 to stream the data out as part of the existing frame. The scheduler sends a message to the Scaler Kernel Creator to request information about which lines are required in Video Line Buffer 2 to create the next line of output 3. The Scaler Kernel Creator replies with the requested information. b. If Video Line Buffer 2 contains the correct lines for output 3 and output 2 and Scaler Algorithmic Core 1 is not generating a line for output 1, the scheduler instructs Video Line Buffer 2 to send its current data to Scaler Algorithmic Core 2 and Scaler Algorithmic Core 1. It instructs Scaler Algorithmic Core 2 to upscale the incoming data and send the result to Video Output Bridge 3. The scheduler instructs Video Output Bridge 3 to stream the data out as part of the existing frame. It also instructs Scaler Algorithmic Core 1 to downscale the incoming data by 2x and send the result to Video Output Bridge 2. The January 2012 Altera Corporation Video and Image Processing Component Library

8 Page 8 Design Example Advantages scheduler instructs Video Output Bridge 2 to stream the data out as part of the existing frame. The scheduler then sends messages to the Scaler Kernel Creator to request information about which lines are required in Video Line Buffer 2, to create the next line of output 2 and output 3. The Scaler Kernel Creator replies with the requested information. c. If Video Line Buffer 2 contains the correct lines for output 3 and output 2 and Scaler Algorithmic Core 1 generates a line for output 1, the scheduler acts as in the paragraph a. When Video Line Buffer 2 contains the correct data to generate the following line of output 3, the scheduler knows that generating a new line for output 2 is still pending. Scaler Algorithmic Core 1 is now free, because output 1 is a 2x downscale. The scheduler does not require Scaler Algorithmic Core 1 on successive input lines, so the scheduler behaves as in paragraph b. This design example shows the following advantages over Video and Image Processing Suite-based designs: You can share Video Line Buffers between the Scaler Algorithmic Cores (Figure 4). You can build a TDM design for multiple video streams through one or more Scaler Algorithmic Cores (Figure 5). You have flexibility with buffer location either on chip or in external memory. The Scaler Algorithmic Cores do not know the source or destination of the video packets, so you can easily move the location of the Video Line Buffers (or even add more or fewer Video Line Buffers) without changing the algorithm. You can also maintain a centralized buffer store that manages all Video Line Buffers and arbitrates between different requests. You can use a standard trace and debugging infrastructure to debug the data that flows into and out of the Scaler Algorithmic Cores, get performance statistics on the usage of the Scaler Algorithmic Cores and Video Line Buffers, and control the blocks. For example, you can single step through the video packet, without modifying the Scaler Algorithmic Core. You can use a central scheduler to control the system and use software scheduling, running on a processor, which you can easily modify to change the system performance. You can change the system without a hardware recompilation. You can scale the design based on the performance statistics, and add more Scaler Algorithmic Cores or Video Line Buffers as needed, to provide greater performance. Scaling the design does not change the functionality of the system and you do not need to rewrite the Scaler Algorithmic Cores. Figure 4. Video Line Buffer Sharing Video Line Buffer Scaler Algorithmic Core 2 Scaler Algorithmic Core 1 Video Output Bridge 2 Video Output Bridge 1 Video and Image Processing Component Library January 2012 Altera Corporation

9 Getting Started Page 9 Figure 5. Using a TDM Design Between Video Streams Video Line Buffer Video Line Buffer Scaler Algorithmic Core Video Output Bridge 2 Video Output Bridge 1 Getting Started Interfaces and Protocols To view the video and image processing component library, perform the following steps: 1. Open the Command Prompt and change to the <Quartus II installation>\quartus\sopc_builder\bin directory. 2. Type the following command to open Qsys in debug mode: qsys-edit --debug 3. On the Component Library tab, right-click on Library and click Show Hidden Components. Expand Video and Image Processing, and expand Component Library to see all video and image processing library components. This section describes the interfaces and protocols of the IP cores in the Video and Image Processing Component Library. Avalon-ST source and sink interfaces transmit all packets between components. Regardless of how you use a packet, the format of the packet (control or data) is the same and includes a control word (which describes destination and source addresses) and a payload. This format can be a set of message arguments (for control) or a data set to be processed. You can use standard packet switches to transfer control data between components and use standard modules to encode or decode them. You can use simple point-to-point connections, where the destination address is always fixed, or a global packet switch, which can route any packet to any component. Every component sink interface has a unique ID, which allows any other component source interface to route a packet to it. In the global packet switch, the routing table of the packet defines the ID of each interface and you can change the flow of packets around the system by updating the routing table. January 2012 Altera Corporation Video and Image Processing Component Library

10 Page 10 Interfaces and Protocols Each component must have a command interface to receive commands from the scheduler and can optionally have a response interface to send responses to the scheduler. Components can have multiple data source and sink interfaces (Figure 6). Figure 6. Component with Function Specific interfaces Component Command Response Data Source Scheduler Scaler Algorithmic Core Packet Format The packet format is based on the Avalon-ST Message protocol, which combines control information with the actual data payload in the Avalon-ST data signal. The Avalon-ST Message protocol strictly limits the Avalon-ST data signal to one symbol per beat, with a symbol width equal to the combined data payload and control word width. The default Avalon-ST Message protocol defines four control fields: Destination ID: component ID to which the source component sends the packet. The component ignores it for point-to-point connections. Source ID: component ID that produced the packet. The component ignores it for point-to-point connections. Task ID: opcode to identify how the design should process a packet. The component ignores it for data packets. Context ID: identifies the context of the current packet. Components that save states use this ID. Most components ignore this ID, unless the component description states otherwise. The width of each control field is variable (and may be 0), and the protocol allows you to add additional control fields. The video and image processing component library defines three sub-classes of the Avalon-ST Message protocol: Avalon-ST Message data: sends generic data from one component to another. In this mode the data payload is typically pixel data. Avalon-ST Message command: sends commands from a scheduler to a component. In this mode the data payload is argument data. The arguments combine with the task ID to determine how the component should process subsequent packets. Avalon-ST Message response: sends responses from a component to a scheduler. In this mode the data payload is argument data. The arguments combine with the task ID to inform the scheduler of key messages in the system. For example, receiving a new line of video at the input. Video and Image Processing Component Library January 2012 Altera Corporation

11 Interfaces and Protocols Page 11 For command and response interfaces the argument data has a width of 32 bits per argument. For data interfaces the pixel data width is determined by the number of color planes per pixel, the color plane width and the transmission format (planes in sequence or in parallel). For general discussions of Avalon-ST Message interfaces, (without specifying whether they are command, response, or data) a single argument or pixel is referred to as an element of data. The Avalon-ST Message protocol allows interfaces to transmit elements of data in parallel. When interfaces transmit elements of data in parallel, they pack the N elements into the Avalon-ST data signal with element 0 in the MSB, and element N 1 in the LSB. Interfaces add an additional empty field (similar to the standard Avalon-ST empty signal) between the data payload and the control word. This empty field indicates which elements are empty on the last beat of each packet. Figure 7 shows an example of the command and response message format for one element per beat. Figure 8 shows an example of the command and response message format with three elements per beat for a packet with seven arguments. Figure 7. Example of the Command and Response Message Format with One Element per Beat SOP EOP Data MSB context id task id source id destination id Arg 0 Arg 1 Arg 2 32 bits LSB January 2012 Altera Corporation Video and Image Processing Component Library

12 Page 12 Interfaces and Protocols Figure 8. Example of the Command and Response Message Format with Three Elements per Beat SOP EOP MSB context id task id source id Data x destination id x 2 Indicates empty fields Arg 0 Arg 3 Arg 6 Arg 1 Arg 4 X 32 bits LSB Arg 2 Arg 5 X Figure 9, Figure 10, and Figure 11 show the various formats that the data message interfaces can use. Figure 9 shows an interface with color planes in sequence. Figure 10 shows an interface with color planes in parallel, three color planes, and one element per beat. Figure 11 shows an interface with color planes in parallel, three color planes, and three elements per beat. Altera does not allow multiple elements per beat with color planes in sequence as this overlaps with color planes in parallel with one element per beat. Figure 9. Example of the Data Message Format for Colors in Sequence SOP EOP Data MSB context id task id source id destination id LSB R G B R G B Video and Image Processing Component Library January 2012 Altera Corporation

13 Interfaces and Protocols Page 13 Figure 10. Example of the Data Message Format for Colors in Parallel with 1 Element per Beat SOP EOP MSB context id task id source id Data R R destination id R R R R G G G G G G LSB B B B B B B Figure 11. Example of the Data Message format with Three Elements per Beat SOP EOP MSB 2 Data context id task id source id destination id x x x x x 1 x pixel 1 pixel 4 pixel 7 pixel 10 pixel 13 x pixel 2 pixel 5 pixel 8 pixel 11 pixel 14 Indicates empty fields LSB pixel 0 pixel 3 pixel 6 pixel 9 pixel 12 x Figure 11 shows an additional control field added to the control word of the message in the MSB and with a value of 2. This extra field uses the control field to define the number of parallel pixels that are empty on the first beat of the packet. This start of packet (SOP) empty field uses the same semantics as the standard Avalon-ST empty signal, except it is active on the first beat of the packet, as opposed to the final beat. Also, it indicates that lower numbered elements are empty, as opposed to the higher elements. Because the SOP empty field is part of the control word, and the Avalon-ST Message specification states that the control word must remain constant through the duration of a packet, it too must hold its value, even though it is only read on the first beat. January 2012 Altera Corporation Video and Image Processing Component Library

14 Page 14 Interfaces and Protocols Video Data Format Interfaces transmit video data in a format that allows them to efficiently transmit overlapping kernels. For example a 3 x 3 tap Scaler Algorithmic Core requires a kernel of pixels three lines deep and three columns wide that moves along the lines. Because the interface transmits the lines in parallel and transfers a column of video data each beat of the burst, it can efficiently transmit overlapping kernels to the Scaler Algorithmic Core. Figure 11 shows an interface transferring a three vertical tap kernel. Typically the length of the burst is the line length of the image that the component processes, but it can be only as long as the number of horizontal taps you require. As the Avalon-ST Video protocol specifies, each sample within the kernel has a fixed format, configured at compile-time for number of colors, parallel or sequential, and bits per color. Figure 12. Example Video Data Format SOP EOP Control Word Ln 0 Col 0 Ln 0 Col 0 Ln 0 Col 0 Ln 0 Col 0 Ln 1 Col 0 Ln 1 Col 0 Ln 1 Col 0 Ln 1 Col 0 Three Vertical Taps Ln 2 Col 0 Ln 2 Col 0 Ln 2 Col 0 Ln 2 Col 0 Burst Length = 4 Routing In all systems the scheduler must send Avalon-ST Message packets to different destinations and those destinations may need to send packets back to the scheduler. Some components may need to send and receive packets from multiple destinations and sources. Because the Avalon-ST protocol is a point-to-point protocol, designs with complex routing need a packet switch, which allows the components in the system to route packets to different destinations and to arbitrate those transfers. The packet switch supports the Avalon-ST Message format, has a configurable number of inputs and outputs, and can route a packet from any input to any output based on the destination ID in the control word. The packet switch also supports compile-time configuration of the number of symbols per beat and bits per symbol. Video and Image Processing Component Library January 2012 Altera Corporation

15 Component List Page 15 External Memory Component List The memory controller and multiport front end use the Avalon-MM interface protocol to allow access to external memory. Most systems buffer video data in external memory. The Packet Writer and Packet Reader allow you to store and retrieve the video data content of Avalon-ST Message packets to and from external memory. This section describes the following IP cores, which are in the Video and Image Processing Component Library: Avalon-MM Control Slave Packet Duplicator Packet Multiplexer Packet Reader Packet Writer Scaler Algorithmic Core Scaler Kernel Creator Video Input Bridge Video Line Buffer Video Output Bridge Avalon-MM Control Slave The Avalon-MM Control Slave acts as a bridge that converts Avalon-MM writes to internal registers into Avalon-ST Message data packets. The Avalon-MM Control Slave also allows the flow of data in the opposite direction, and can update internal registers with data from Avalon-ST Message packets. You can use the Avalon-MM slave interface to read the data. All configurations of the Avalon-MM Control Slave feature an Avalon-MM slave interface, an Avalon-ST Message command interface, and an Avalon-ST Message response interface. Depending on the parameters, the Avalon-MM Control Slave may also include an Avalon-ST Message data input interface and an Avalon-ST Message data output interface. The parameters also determine the register map of the Avalon-MM Control Slave. Table 2, Table 3, and Table 4 list the signals, parameters and register map of the Avalon-MM Control Slave. Table 5 and Table 6 list the command and response messages, respectively. January 2012 Altera Corporation Video and Image Processing Component Library

16 Page 16 Component List Table 2. Avalon-MM Control Slave Signals Signal av_mm_control_address av_mm_control_byteenable av_mm_control_read av_mm_control_readdata av_mm_control_readdatavalid av_mm_control_write av_mm_control_waitrequest av_mm_control_writedata av_mm_control_irq av_st_cmd_data av_st_cmd_endofpacket av_st_cmd_ready av_st_cmd_startofpacket av_st_cmd_valid av_st_resp_data av_st_resp_endofpacket av_st_resp_ready av_st_resp_startofpacket av_st_resp_valid av_st_din_data av_st_din_endofpacket av_st_din_ready av_st_din_startofpacket av_st_din_valid av_st_dout_data av_st_dout_endofpacket av_st_dout_ready av_st_dout_startofpacket av_st_dout_valid Standard Avalon-MM slave signals. Optional. Standard Avalon interrupt flag. Standard Avalon-ST sink signals for the command interface. This interface conforms to the Avalon-ST Message protocol. Standard Avalon-ST sink signals for the response output interface. This interface conforms to the Avalon-ST Message protocol. Optional. Standard Avalon-ST sink signals for the data input interface. This interface conforms to the Avalon-ST Message protocol. Optional. Standard Avalon-ST source signals for the data output interface. This interface conforms to the Avalon-ST Message protocol. Table 3. Avalon-MM Control Slave Parameters Parameter Number of read-only registers Number of trigger registers Number of command trigger registers Number of read/write registers Number of interrupts Control register bytes Read-only register bytes Number of registers that the command interface may write to and the slave interface reads from. Number of registers that the slave interface reads from and writes to. Each write generates a response. Number of registers that the slave interface may read from and write to. Each write generates a response and requires a command in reply. Number of registers that the slave and data interfaces may read from and write to. Number of interrupts supported. Number of (8-bit) bytes per register for the control, status, and interrupt registers. Number of (8-bit) bytes per register for the read-only registers (ignored if there are no read-only registers). Video and Image Processing Component Library January 2012 Altera Corporation

17 Component List Page 17 Table 3. Avalon-MM Control Slave Parameters Parameter Trigger and command trigger register bytes Read/write register bytes Slave port address width Add data input interface Add data output interface Fast register update responses Implement registers in memory Pipeline slave read data Pipeline response interface Pipeline dout interface Source address width Destination address width Context ID width Task ID width Response Source ID Response Destination ID Response Context ID Data out source address Number of (8-bit) bytes per register for the trigger and command trigger registers (ignored if there are no trigger or command trigger registers). Number of (8-bit) bytes per register for the read and write registers (ignored if there are no read and write registers). The width of address signal for the Avalon-MM slave interface. Adds a data input interface. Adds a data output interface. Turn on to remove all register stages from the command and response interfaces and to send and receive all command and response arguments in parallel (two arguments per beat). Implements the Avalon-MM Control Slave registers in a memory. Adds a pipeline register to the read data signal on the Avalon-MM slave interface. Adds a pipeline register to the response interface. Adds a pipeline register to the data-out interface. The width of the source ID signal. The width of the destination ID signal. The width of the context ID signal. The width of the task ID signal. Source ID that the response interface uses. Destination ID that the response interface uses. Context ID that the response interface uses. Source address that the data-out interface uses. Table 4. Avalon-MM Control Slave Register Map Group Name Address Range Control registers Read-only registers Trigger registers 0 Control. 1 Status. 2 Interrupt. 3 to 2 + Number of read-only registers 3 + Number of read-only registers to 2 + Number of read-only registers + Number of trigger registers Optional. Use the command interface to update these registers, only the Avalon-MM slave interface can read them. Optional. The Avalon-MM slave interface can read from or write to these registers. Use the command interface to alter their values. For every write to one of these registers by the Avalon-MM slave interface, the IP core generates a response. January 2012 Altera Corporation Video and Image Processing Component Library

18 Page 18 Component List Table 4. Avalon-MM Control Slave Register Map Group Name Address Range Command trigger registers Read-write registers 3 + Number of read-only registers + Number of trigger registers to 2 + Number of read-only registers + Number of trigger registers + Number of command trigger registers 3 + Number of read-only registers + Number of trigger registers + Number of command trigger registers to 2 + Number of read-only registers + Number of trigger registers + Number of command trigger registers + Number of read/write registers Optional. The Avalon-MM slave interface can read from or write to these registers. Use the command interface to alter their values. For every write to one of these registers by the Avalon-MM slave interface, the IP core generates a response. A write to any of these registers also blocks any reads or writes to the read-write registers by the Avalon-MM slave interface until a command message is received though the command interface to either send or receive a data packet through the data input or output interfaces. Optional. The Avalon-MM slave interface can read from or write to these registers. Data from packets received through the Avalon-ST Message data input interface may also update their values. A command triggers receiving and storing a packet of data. You may send out the values stored in these registers as an Avalon-ST Message data packet through the data output interface. A command triggers sending such a packet. Table 5. Avalon-MM Control Slave Command Messages Message ID Arguments Arg 0 bits 15:0 is register address Instructs the Avalon-MM Control Slave to update the Update Register (0) Arg 0 bits 31:0 is new register value specified register to the specified value. Send Packet (1) Receive Packet (2) Arg 0 bits 15:0 is destination ID Arg 0 bits 23:16 is register start address Arg 0 bits 31:24 is register end address Arg 1 bits 7:0 is packet task ID Arg 0 bits 7:0 is register start address Instructs the Avalon-MM Control Slave to send an Avalon-ST Message data packet to the data output interface. The data included in the packet is the data in the registers from the specified register start address to the specified register end address (inclusive). Both the start and end address should be within the read-write registers. Argument 1 specifies the task ID for the packet. Instructs the Avalon-MM Control Slave to receive an Avalon-ST Message data packet from the data input interface. The component writes the data into successive registers, starting at the specified start address. The start address should be within the read-write registers. If the data packet continues after the component writes to the last register in the register map, the component discards any additional data. Video and Image Processing Component Library January 2012 Altera Corporation

19 Component List Page 19 Table 6. Avalon-MM Control Slave Response Messages Message ID Arguments Register Write (5) Arg 0 bits 31:16 is byte enables Arg 0 bits 15:0 is register address Arg 1 bits 31:0 is new register value Instructs the scheduler that the Avalon-MM master interface has written the value in argument 1 to the specified register with the specified byte enables. The scheduler must combine the new value of the register, the old value of the register and the byte enables to get the final value of the register to store and reference internally. The Avalon-MM Control Slave offers the following four main functions: Avalon-ST Message data packet generation. If you turn on the Add data output interface parameter, the component includes the Avalon-ST Message data output interface. This interface allows data that the read-write registers contain to stream out though the data output interface as an Avalon-ST Message data packet. This process involves the following typical steps: The Avalon-MM master interface writes data to the read-write registers in the Avalon-MM Control Slave. Then the Avalon-MM master interface writes a new value to one of the blocking trigger registers, which in turn blocks any further reads or writes to the read-write registers and generates a response to the scheduler. The scheduler uses the command interface to issue a send packet command and the Avalon-MM Control Slave places the selected data as a packet on the output. As the packet streams out, the component unlocks the read-write registers for read-write access by the Avalon-MM slave interface. Avalon-ST Message data packet reading. If you turn on the Add data input interface parameter, the component includes the Avalon-ST Message data input interface. This interface allows the Avalon-MM Control Slave to store data from an Avalon-ST Message data packet in internal registers and the Avalon-MM slave interface to read them. This process involves the following typical steps: The Avalon-MM master interface writes a new value to a blocking trigger register, which generates a response to the scheduler. This action also locks the read-write registers and prevents any further reads or writes to them with the Avalon-MM slave interface. The scheduler then sends a receive packet command to the Avalon-MM Control Slave, which instructs it to accept a new packet at the data input interface and store the data in the read-write registers. As the component receives the packet, it unlocks the read-write registers so the Avalon-MM slave interface can read the updated values. Interrupts. The Avalon-MM Control Slave optionally supports up to eight interrupts. Register 2 is the interrupt register and bits 15:8 of this register indicate which interrupts are active. Use the update register command to set any of bits 15:8 to 1, which raises an interrupt. Bits 15:8 of the control register (register 0) are the interrupt enable bits. Each of these bits enables the corresponding interrupt in register 2. Enable or disable each interrupt by writing to register 0 through the Avalon-MM slave interface. If the command interface sets any of bits 15:8 of January 2012 Altera Corporation Video and Image Processing Component Library

20 Page 20 Component List register 2 and the corresponding bits in register 0 is set high, the av_mm_control_irq output is set high to alert the system to the interrupt. The system can then read the value of register 2 to see which interrupts are active. You should then acknowledge and reset the interrupt by writing a 1 to the active bits of register 2. Single register updates. This functionality is included in all parameterizations of the Avalon-MM Control Slave and it allows an Avalon-MM master interface to update and control various functions of a component-based IP core or system. The three control registers exist in all parameterizations: Register 0 is the control register. Nominally bit 0 of this register is the go bit and stops and starts the system or IP core. Use bits 7:1 of this register as flags to enable or disable any user specific functionality. If you parameterize the Avalon-MM Control Slave to include interrupts, bits 15:8 enable and disable each interrupt (the component supports a maximum of eight). If you include more than two bytes in the control registers, you can use the bits above bit 15 for any purpose. The Avalon-MM master interface may read from or write to the control register. The command interface cannot alter the value of this register. Every write to this register triggers a slave write response that alerts the scheduler to the new value of the control register. Register 1 is the status register. Nominally bit 0 is the status bit and it indicates whether the connected IP core or system is running (processing video data) or waiting, either because you set the go bit low or because it is waiting for the start of a new video frame at the input. You can use bits 7:1 of this register to indicate the status of any user specific functionality. You can use any bits above bit 7 for any generic purpose. You can only update the status register by an update register command through the command interface. The Avalon-MM slave interface may only read the value of this register. Register 2 is the interrupt register. 1 The read-only registers only exist if you assign a non-zero value to the Number of read only registers parameter. Use the command interface update register command to write to these registers and the Avalon-MM slave interface to read them. These registers allow information to pass from the IP core or system to an Avalon-MM master interface. 1 The trigger registers only exist if you assign a non-zero value to the Number of trigger registers parameter. Use the update register command in the command interface to update these registers or use the Avalon-MM Control Slave to write to and read from them. For every write to one of these registers, the Avalon-MM Control Slave generates a slave write response to inform the scheduler of the updated register value. These registers update specific functionality of an IP core. For example, enabling or disabling mixer layers, scaler output resolutions, and so on. Video and Image Processing Component Library January 2012 Altera Corporation

21 Component List Page 21 Packet Duplicator The Packet Duplicator sink input receives incoming packets and places them on (up to) sixteen independent source outputs. It works autonomously, requiring no command interface. You can route the current input packet to one or more source outputs, the destination address of the input packet determines the routing. For a Packet Duplicator with N source outputs, the component reads the N LSBs of the destination address as an enable for each output source. If bit n of the destination address is high, the Packet Duplicator routes the packet to source n. The n LSBs of the destination address control the Packet Duplicator and may optionally (compile time option) be removed from the destination address at the output. You may configure the Packet Duplicator in demultiplex-only mode, where you guarantee that you route each packet to only one output source. If the destination address fails to comply with this restriction, the output is undefined. You can include optional FIFO buffers to drive each source output, which allows some amount of backpressure to be absorbed from the Packet Duplicator's sink inputs before the Packet Duplicator's source output needs to be back-pressured. Table 7 and Table 8 list the signals and parameters for the Packet Duplicator. Table 7. Packet Duplicator Signals Signal av_st_din_data av_st_din_endofpacket av_st_din_ready av_st_din_startofpacket av_st_din_valid av_st_dout_data av_st_dout_endofpacket av_st_dout_ready av_st_dout_startofpacket av_st_dout_valid Standard Avalon-ST sink signals for the data input interface. This interface conforms to the Avalon-ST Message protocol. Standard Avalon-ST source signals for the data output interface. This interface conforms to the Avalon-ST Message protocol. Each signal is an array port with the signals for all source outputs merged to form a single bus (N is the number of sources that you select). Table 8. Packet Duplicator Parameters Parameter Number of color planes Color planes transmitted in parallel Bits per pixel per color plane Number of output ports Demux mode (only one output active at once) The number of color planes per pixel. Turn on to transmit color planes in parallel. The number of bits per color plane. Number of sources. Turn on to configure the Duplicator in demultiplex-only mode. Clip address bits Turn on to remove the LSBs of the destination address that control the duplication before sending to the outputs. FIFO depth Depth of FIFO buffer added to each source (may be 0). Register data out interfaces Pipeline data in ready signal Turn on to add a register stage to the valid and data signals on the data-out interface. Turn on to add a register stage to the ready signals on the data-in interfaces. Setting this parameter to 1 also forces the component to add a register stage to the data out signals, regardless of the value of Register data out interface parameter. January 2012 Altera Corporation Video and Image Processing Component Library

22 Page 22 Component List Table 8. Packet Duplicator Parameters Parameter Source address width Destination address width Context ID width Task ID width The width of the source ID signal. The width of the destination ID signal. The width of the context ID signal. The width of the task ID signal. Packet Multiplexer Table 9. Packet Multiplexer Signals The Packet Multiplexer forwards data from one of (up to) sixteen sink interfaces while applying backpressure to hold off the others. The packet multiplexer decides which sink to select on either a first-come-first-serve basis, or based on directions from an optional command interface. You select between the command-driven and first-come-first-serve modes at compile time. Table 9 and Table 10 list the signals and parameters for the Packet Multiplexer. Signal av_st_cmd_data av_st_cmd_endofpacket av_st_cmd_ready av_st_cmd_startofpacket av_st_cmd_valid av_st_din_data av_st_din_endofpacket av_st_din_ready av_st_din_startofpacket av_st_din_valid av_st_dout_data av_st_dout_endofpacket av_st_dout_ready av_st_dout_startofpacket av_st_dout_valid Standard Avalon-ST sink signals for the command input interface. This interface conforms to the Avalon-ST Message protocol. Standard Avalon-ST sink signals for the data input interface. Each signal is an array port with the signals for all N sink inputs merged to form a single bus (N is the number of sink input that you select). This interface conforms to the Avalon-ST Message protocol. Standard Avalon-ST source signals for the data output interface. This interface conforms to the Avalon-ST Message protocol. Table 10. Packet Mutliplexer Parameters Parameter Number of color planes Color planes transmitted in parallel Bits per pixel per color plane Use command port Number of inputs Register data out Pipeline data in ready Output port for code 0 The number of color planes per pixel. Turn on to transmit color planes in parallel. The number of bits the design uses per pixel, per color plane. Turn on to use command port; turn off to limit to two inputs. Number of sink inputs. Turn on to add a register stage to the valid and data signals on the data-out interface. Turn on to add a register stage to the ready signals on the data-in interfaces. Turning on forces the component to add a register stage to the data out signals, regardless of the register output. 16 parameters to define the contents of a lookup table that determines which sink input is selected for each command in command-driven mode. Video and Image Processing Component Library January 2012 Altera Corporation

23 Component List Page 23 Table 10. Packet Mutliplexer Parameters Parameter Source address width Destination address width Context ID width Task ID width The width of the source ID signal. The width of the destination ID signal. The width of the context ID signal. The width of the task ID signal. Packet Reader When you turn on Use command port, you must supply a command to select a sink input to supply each output packet. The Packet Multiplexer applies backpressure to all inputs until it receives a command. Table 11 lists the command format for the Packet Multiplexer. The command contains a 4-bit routing code that the component feeds into a compile time defined look-up table to determine which sink input it should output next. When you turn off Use command port, the Packet Multiplexer is limited to only two inputs. Table 11. Command Format for Packet Multiplexer Task ID Arguments Select Sink (0) Arg 0 bits 3:0 is routing code Instructs the Packet Multiplexer to receive the next output packet from the sink input defined by the routing code. The component feeds the routing code into a look-up table to determine the sink number. The Packet Reader efficiently reads data from memory and outputs it as Avalon-ST Message data packets. 1 The Packet Reader and the Packet Writer have the same command structure and the same approach for FIFO buffers, data packing, and data unpacking. Table 12, Table 13, and Table 14 list the signals, parameters, and command messages for the Packet Reader. Table 12. Packet Reader Signals Signal av_st_dout_data av_st_dout_endofpacket av_st_dout_ready av_st_dout_startofpacket av_st_dout_valid Standard Avalon-ST source signals for the data output interface. This interface conforms to the Avalon-ST Message protocol. January 2012 Altera Corporation Video and Image Processing Component Library

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