From COSIDE to Cadence. Andreas Schröck Infineon Technologies AG
|
|
|
- Job Grant
- 7 years ago
- Views:
Transcription
1 From COSIDE to Cadence Andreas Schröck Infineon Technologies AG
2 Agenda 1 History project background 2 Conversion from Coside to Cadence WHY? 3 Problems and Shortcomings 4 The brighter future 2
3 Agenda 1 History project background 2 Conversion from Coside to Cadence WHY? 3 Problems and Shortcomings 4 The brighter future 3
4 History project background (1/2) Infineon s Radar Success Story 2009: series Product (Porsche Panamera) 2012: SiGe:C & CMOS Companion 2014: BiCMOS Integration 2016: Full Integration of RF-IF-ADC- Digital Interface : 77GHz 2RX 2TRX + VCO Prototype 4
5 History project background (2/2) Radar Gen4 dev(rcc1010) Radar Gen4 TO(RCC1010) Radar Gen5 predev(ptrx***) Radar Gen5 dev(ptrx***) Radar Gen5 predev(rxs***) First SystemC modeling based on Fraunhofer IDE First co-simulation with Cadence (coupling) Change to Coside 1.x Coside 2.x First co-simulation with Cadence (export) TODAY 2013 pure SystemC modelling without any co-simulation 2014 black box cosimulation of more complex models black box testing and co-simulation of complete System (high-level) extended cosimulation of complete System (Cadence netlist based / low-level) first tests for export feature (first white box testing) white box cosimulation (export) first draft of Coside- Cadence-Bridge 5
6 Agenda 1 History project background 2 Conversion from Coside to Cadence WHY? 3 Problems and Shortcomings 4 The brighter future 6
7 From Coside to Cadence WHY? (1/4) 7
8 From Coside to Cadence WHY? (2/4) Increased complexity Demanding customers Faster time to market 8
9 From Coside to Cadence WHY? (3/4) Enabling transient co-simulations on system level 9
10 From Coside to Cadence WHY? (4/4) Reduction of simulation time Simulation of PLL SystemC Cadence Spectre Matlab VCO = 2.6GHz; resolution 83ps; 700us sim time 5 Minutes Not possible in closed loop out of memory Higher quality of design Use SystemVerilog UVM methodology on System-Level with SystemC models for analog and real RTL for digital 10
11 Agenda 1 History project background 2 Conversion from Coside to Cadence WHY? 3 Problems and Shortcomings 4 The brighter future 11
12 Debugging of SystemC Models in Cadence Using the coupling method to export SystemC models from Coside leads to a BLACK-BOX DUT No internals of model visible in Cadence Multiple instances not easily possible with shared-objects Bug fixing needs many iterations Conversion issues within connect modules (CMs) are hard to find 12
13 Problems with Cadence and SystemC / Coside Keep the design data between Cadence and Coside consistent Cadence uses OA database ClearCase is also not helpful Analog design data is schematic based Changes hard to find 13
14 Interaction between different domains (1/2) Data exchange between analog and digital is only possible with special conversion cells connect modules (CM) Insertion shall be / is done automatically no schematic changes / manual insertion allowed Analog domain CM CM digital domain 14
15 Interaction between different domains (2/2) More problems with multi-voltage designs How to define voltages for CMs? Handwritten VAMS wrapper necessary (supply aware) 3V3 1V5 CM CM digital domain Analog domain CM CM digital domain 15
16 Problems with complex designs Interaction between different languages Digital: Verilog / VHDL Analog Models: SystemC / C++ / Verilog-A / Verilog-AMS Top-Level TB: SystemVerilog / Specman Analog: spice Interaction between different simulators Digital: INCISIVE / NC-SIM Analog: Spectre / Ultrasim / P-Spice SystemC Kernel: C++ 16
17 Agenda 1 History project background 2 Conversion from Coside to Cadence WHY? 3 Problems and Shortcomings 4 The brighter future 17
18 White-Box integration in Cadence Use Cadence gcc + kernel to integrate SystemC models in the AMS co-simulation Coside offers a make based solution to generate a white-box module for Cadence make Compiles modules using Cadence Generates a irun-scripts & resource files irun Compiles a module to.pak &.so Additional.res file can be used in AMS-Simuation DUT ncsim Loads.res file to identify available modules Simulates SysC modules a white-box instances 18
19 From hand-made to generated (1/3) Supply aware VAMS wrapper must be generated based on available design information Needed Information: Block / module supplies Related supplies for ports Custom defines for AMS- Simulator Solution from Coseda: Add all necessary information as port / schematic VAMS-attributes Attributes are inherited through hierarchies Drawback: Data insertion in Coside might become a little tricky for bigger designs. Is there a better way? YES 19
20 From hand-made to generated (2/3) The better way to insert power supply information Use the export / inport feature from Coside to exchange data and attributes between Coside and Cadence (Coside-Cadence- Bridge) Create core modules / blocks in Coside Import blocks & schematics in Coside Create core schematics in Coside Extend blocks / schematics in Cadence (including supply information) Export schematics & blocks to Cadence 20
21 From hand-made to generated (3/3) Schematic & block conversion from / to Coside / Cadence to keep data in sync 21
22 Q&A Questions? 22
23
24 Conclusion Coside / SystemC helps us during the development of bigger designs to achieve Better quality of the system Faster development cycle There is still room for improvement 24
Solutions for Mixed-Signal SoC Verification New techniques that are making advanced SoC verification possible
New techniques that are making advanced SoC verification possible By Kishore Karnane and Sathishkumar Balasubramanian, Cadence esign Systems Performing full-chip verification of large mixed-signal systems
Product Development Flow Including Model- Based Design and System-Level Functional Verification
Product Development Flow Including Model- Based Design and System-Level Functional Verification 2006 The MathWorks, Inc. Ascension Vizinho-Coutry, avizinho@mathworks.fr Agenda Introduction to Model-Based-Design
AMS Verification at SoC Level: A practical approach for using VAMS vs SPICE views
AMS Verification at SoC Level: A practical approach for using VAMS vs SPICE views Nitin Pant, Gautham Harinarayan, Manmohan Rana Accellera Systems Initiative 1 Agenda Need for SoC AMS Verification Mixed
A Methodology and the Tool for Testing SpaceWire Routing Switches Session: SpaceWire test and verification
A Methodology and the Tool for Testing SpaceWire Routing Switches Session: SpaceWire test and verification Elena Suvorova Saint-Petersburg University of Aerospace Instrumentation. 67, B. Morskaya, Saint-
ADS Ptolemy in AMSD-ADE
ADS Ptolemy in AMSD-ADE August 2007 Notice The information contained in this document is subject to change without notice. Agilent Technologies makes no warranty of any kind with regard to this material,
Design-Kits, Libraries & IPs
Design-Kits, Libraries & IPs Supported CAD tools Design-kits overview Digital, Analog, and RF Libraries IPs Supported CAD tools Design-kits overview ST 65nm Tanner PDK Standard cell Libraries IPs austriamicrosystems
Virtuoso Analog Design Environment Family Advanced design simulation for fast and accurate verification
Advanced design simulation for fast and accurate verification The Cadence Virtuoso Analog Design Environment family of products provides a comprehensive array of capabilities for the electrical analysis
Quartus II Handbook Volume 3: Verification
Quartus II Handbook Volume 3: Verification Subscribe QII5V3 2015.05.04 101 Innovation Drive San Jose, CA 95134 www.altera.com Simulating Altera Designs 1 2015.05.04 QII5V3 Subscribe This document describes
Introduction to Functional Verification. Niels Burkhardt
Introduction to Functional Verification Overview Verification issues Verification technologies Verification approaches Universal Verification Methodology Conclusion Functional Verification issues Hardware
Quartus Prime Standard Edition Handbook Volume 3: Verification
Quartus Prime Standard Edition Handbook Volume 3: Verification Subscribe QPS5V3 101 Innovation Drive San Jose, CA 95134 www.altera.com Simulating Altera Designs 1 QPS5V3 Subscribe This document describes
Abstract. Cycle Domain Simulator for Phase-Locked Loops
Abstract Cycle Domain Simulator for Phase-Locked Loops Norman James December 1999 As computers become faster and more complex, clock synthesis becomes critical. Due to the relatively slower bus clocks
Designing a System-on-Chip (SoC) with an ARM Cortex -M Processor
Designing a System-on-Chip (SoC) with an ARM Cortex -M Processor A Starter Guide Joseph Yiu November 2014 version 1.02 27 Nov 2014 1 - Background Since the ARM Cortex -M0 Processor was released a few years
Digital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
System Architecture Performance Modeling with SystemC
System Architecture Performance Modeling with SystemC 9 th European SystemC Users Group Meeting February 17 th, 2004 Raimar Thudt Tino Bertram Infineon Präsentation November 2003 Seite 1 Copyright Infineon
Automating Root-Cause Analysis to Reduce Time to Find Bugs by Up to 50%
Automating Root-Cause Analysis to Reduce Time to Find Bugs by Up to 50% By Kishore Karnane and Corey Goss, Cadence Design Systems If you re spending more than 50% of your verification effort in debug,
High-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm Computer Technology /99 Overview Ultra-Low-Power
Modeling a GPS Receiver Using SystemC
Modeling a GPS Receiver using SystemC Modeling a GPS Receiver Using SystemC Bernhard Niemann Reiner Büttner Martin Speitel http://www.iis.fhg.de http://www.iis.fhg.de/kursbuch/kurse/systemc.html The e
Wireless Communication and RF System Design Using MATLAB and Simulink Giorgia Zucchelli Technical Marketing RF & Mixed-Signal
Wireless Communication and RF System Design Using MATLAB and Simulink Giorgia Zucchelli Technical Marketing RF & Mixed-Signal 2013 The MathWorks, Inc. 1 Outline of Today s Presentation Introduction to
Testing & Verification of Digital Circuits ECE/CS 5745/6745. Hardware Verification using Symbolic Computation
Testing & Verification of Digital Circuits ECE/CS 5745/6745 Hardware Verification using Symbolic Computation Instructor: Priyank Kalla (kalla@ece.utah.edu) 3 Credits Mon, Wed, 1:25-2:45pm, WEB L105 Office
Electronic system-level development: Finding the right mix of solutions for the right mix of engineers.
Electronic system-level development: Finding the right mix of solutions for the right mix of engineers. Nowadays, System Engineers are placed in the centre of two antagonist flows: microelectronic systems
which is responsible for CAD tools, libraries, technology data; customer support is shared with local CAD groups
ASCIA - A Multi-Vendor IC Design System Dr. Thomas Harriehausen CAD SYS Tel.: (89) 4144-4762 Internet email: harrie@hl.siemens.de Dr. Harriehausen, Siemens Halbleiter Objectives of this Presentation Present
System / Verification: Performance & Debug Track Abstracts
System / Verification: Performance & Debug Track Abstracts VER2.201 Reducing Snapshot Creation Turnaround for UVM- SV Based TB Using MSIE Approach STMicroelectronics Abhishek Jain - STMicroelectronics
DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS
DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS U. Pogliano, B. Trinchera, G.C. Bosco and D. Serazio INRIM Istituto Nazionale di Ricerca Metrologica Torino (Italia)
Accellera Systems Initiative completes SystemC AMS 2.0 standard for mixed-signal design of electronic systems
INDUSTRY QUOTE SHEET March 19, 2013 Accellera Systems Initiative completes SystemC AMS 2.0 standard for mixed-signal design of electronic systems ASTC With increasing systems integration, most embedded
Design Cycle for Microprocessors
Cycle for Microprocessors Raúl Martínez Intel Barcelona Research Center Cursos de Verano 2010 UCLM Intel Corporation, 2010 Agenda Introduction plan Architecture Microarchitecture Logic Silicon ramp Types
INF4420 Introduction
INF4420 Introduction Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Practical information about the course. Context (placing what we will learn in a larger context) Outline of the
9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
Engineering Change Order (ECO) Support in Programmable Logic Design
White Paper Engineering Change Order (ECO) Support in Programmable Logic Design A major benefit of programmable logic is that it accommodates changes to the system specification late in the design cycle.
ARM Webinar series. ARM Based SoC. Abey Thomas
ARM Webinar series ARM Based SoC Verification Abey Thomas Agenda About ARM and ARM IP ARM based SoC Verification challenges Verification planning and strategy IP Connectivity verification Performance verification
Model-based system-on-chip design on Altera and Xilinx platforms
CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT Model-based system-on-chip design on Altera and Xilinx platforms Ronald Grootelaar, System Architect RJA.Grootelaar@3t.nl Agenda 3T Company profile Technology
Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis
Cadence Tutorial C: Simulating DC and Timing Characteristics Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group rev S06 (convert to spectre simulator) Document Contents Introduction
Understanding DO-254 Compliance for the Verification of Airborne Digital Hardware
White Paper Understanding DO-254 Compliance for the of Airborne Digital Hardware October 2009 Authors Dr. Paul Marriott XtremeEDA Corporation Anthony D. Stone Synopsys, Inc Abstract This whitepaper is
Applications to Computational Financial and GPU Computing. May 16th. Dr. Daniel Egloff +41 44 520 01 17 +41 79 430 03 61
F# Applications to Computational Financial and GPU Computing May 16th Dr. Daniel Egloff +41 44 520 01 17 +41 79 430 03 61 Today! Why care about F#? Just another fashion?! Three success stories! How Alea.cuBase
Gate-Level Simulation Methodology
Improving Gate-Level Simulation Performance Author: Gagandeep Singh, Cadence Design Systems, Inc. The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is
Allegro Design Authoring
Create design intent with ease for simple to complex designs Systems companies looking to create new products at the lowest possible cost need a way to author their designs with ease in a shorter, more
VHDL Test Bench Tutorial
University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory VHDL Test Bench Tutorial Purpose The goal of this tutorial is to demonstrate how to automate
Vivado Design Suite Tutorial
Vivado Design Suite Tutorial High-Level Synthesis UG871 (v2012.2) August 20, 2012 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and
with Spectre Platform Comprehensive analyses for robust design and verification
Virtuoso Multi-Mode Simulation with Spectre Platform Comprehensive analyses for robust design and verification The Cadence Spectre circuit simulation platform, built on an advanced infrastructure, combines
Jitter Transfer Functions in Minutes
Jitter Transfer Functions in Minutes In this paper, we use the SV1C Personalized SerDes Tester to rapidly develop and execute PLL Jitter transfer function measurements. We leverage the integrated nature
Dataflow Programming with MaxCompiler
Dataflow Programming with MaCompiler Lecture Overview Programming DFEs MaCompiler Streaming Kernels Compile and build Java meta-programming 2 Reconfigurable Computing with DFEs Logic Cell (10 5 elements)
Software Implementation Technology report
Software Implementation Technology report Team: No Best 1 - Program Manager 2 - Developer 3- Tester 2007-8 Peking University Software Implementation Technology report 1 Problem & Plan 2 Design & Implementation
MSME TOOL ROOM, HYDERABAD CENTRAL INSTITUTE OF TOOL DESIGN
MSME TOOL ROOM, HYDERABAD CENTRAL INSTITUTE OF TOOL DESIGN (An ISO 9001:2008, ISO 29990; 2010, ISO 14001:2004 & ISO 50001:2011 Certified Institution) VES COURSES 2015-20162016 10 Months Full Time Courses
ESP-CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation
Datasheet -CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation Overview -CV is an equivalence checker for full custom designs. It enables efficient comparison of a reference design
State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop
Photos placed in horizontal position with even amount of white space between photos and header State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop Michael Holmes Manager, Mixed Signal ASIC/SoC
Digital Design Verification
Digital Design Verification Course Instructor: Debdeep Mukhopadhyay Dept of Computer Sc. and Engg. Indian Institute of Technology Madras, Even Semester Course No: CS 676 1 Verification??? What is meant
OpenSoC Fabric: On-Chip Network Generator
OpenSoC Fabric: On-Chip Network Generator Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf MODSIM 2014 Presentation
BY STEVE BROWN, CADENCE DESIGN SYSTEMS AND MICHEL GENARD, VIRTUTECH
WHITE PAPER METRIC-DRIVEN VERIFICATION ENSURES SOFTWARE DEVELOPMENT QUALITY BY STEVE BROWN, CADENCE DESIGN SYSTEMS AND MICHEL GENARD, VIRTUTECH INTRODUCTION The complexity of electronic systems is rapidly
A Verilog HDL Test Bench Primer Application Note
A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2
A Mixed-Signal System-on-Chip Audio Decoder Design for Education
A Mixed-Signal System-on-Chip Audio Decoder Design for Education R. Koenig, A. Thomas, M. Kuehnle, J. Becker, E.Crocoll, M. Siegel @itiv.uni-karlsruhe.de @ims.uni-karlsruhe.de
Digital IC Design Flow
Collège Militaire Royal du Canada (Cadence University Alliance Program Member) Department of Electrical and Computer Engineering Départment de Génie Electrique et Informatique RMC Microelectronics Lab
Forum R.F.& Wireless, Milano il 14 Febbraio 2008 Dr. Emmanuel Leroux Technical Sales Manager for Italy emmanuel.leroux@cst.com 0039 340 3768950
Simulazione 3D elettromagnetica Time e Frequency domain Forum R.F.& Wireless, Milano il 14 Febbraio 2008 Dr. Emmanuel Leroux Technical Sales Manager for Italy emmanuel.leroux@cst.com 0039 340 3768950 1
MAJORS: Computer Engineering, Computer Science, Electrical Engineering
Qualcomm MAJORS: Computer Engineering, Computer Science, Electrical Engineering TITLE: Intern - Software Engineer - Summer 2012 JOB DESCRIPTION: G1889814 Job Title Intern - Software Engineer - Summer 2012
Quality. Stages. Alun D. Jones
Quality - by Design Quality Design Review Stages Alun D. Jones Design Review Stages Design Review 0 (DR0) Pre-order & quotation stage Design Review 1 (DR1) Initial kick-off and preliminary specification
Eingebettete Systeme. 4: Entwurfsmethodik, HW/SW Co-Design. Technische Informatik T T T
Eingebettete Systeme 4: Entwurfsmethodik, HW/SW Co-Design echnische Informatik System Level Design: ools and Flow Refinement of HW/SW Systems ools for HW/SW Co-Design C-based design of HW/SW Systems echnische
The Click2NetFPGA Toolchain. Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai USENIX ATC 12, Boston, MA, 13 th of June, 2012
The Click2NetFPGA Toolchain Teemu Rinta-aho, Mika Karlstedt, Madhav P. Desai USENIX ATC 12, Boston, MA, 13 th of June, 2012 Click2NetFPGA We have explored the possibilities of High Level Synthesis (HLS)
Digital Systems. Role of the Digital Engineer
Digital Systems Role of the Digital Engineer Digital Design Engineers attempt to clearly define the problem(s) Possibly, break the problem into many smaller problems Engineers then develop a strategy for
Basics of Simulation Technology (SPICE), Virtual Instrumentation and Implications on Circuit and System Design
Basics of Simulation Technology (SPICE), Virtual Instrumentation and Implications on Circuit and System Design Patrick Noonan Business Development Manager National Instruments Electronics Workbench Group
Project Plan. Project Plan. May13-06. Logging DC Wattmeter. Team Member: Advisor : Ailing Mei. Collin Christy. Andrew Kom. Client: Chongli Cai
Project Plan May13-06 Logging DC Wattmeter Team Member: Ailing Mei Andrew Kom Chongli Cai Advisor : Collin Christy Client: Garmin International David Hoffman Qiaoya Cui Table of Contents Need Statement...
How To Design A Chip Layout
Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170) Course and contest Intermediate meeting 3 Prof. Dirk Timmermann, Claas Cornelius, Hagen Sämrow, Andreas Tockhorn, Philipp Gorski, Martin
RF Module Design: Requirements and Issues
unlicensed technology RF Module Design: Requirements and Issues RF module design and prototype development are hot industry topics. This article discusses the issues and solutions related to RF module
Rapid Software Development with OpenAccess. Dean Marvin Exec Director, Product Development
Rapid Software Development with OpenAccess Dean Marvin Exec Director, Product Development Presentation Overview Conditions for rapid OA development Discussion of development styles C++ object oriented
Electronic systems prototyping: Tools and methodologies for a better observability.
Electronic systems prototyping: Tools and methodologies for a better observability. In an electronic system development flow, a prototyping phase is very diversely valued by the electronic system engineer
High Performance or Cycle Accuracy?
CHIP DESIGN High Performance or Cycle Accuracy? You can have both! Bill Neifert, Carbon Design Systems Rob Kaye, ARM ATC-100 AGENDA Modelling 101 & Programmer s View (PV) Models Cycle Accurate Models Bringing
ASCIA - A Multi-Vendor IC Design System. Thomas Harriehausen
ASCIA - A Multi-Vendor IC Design System Thomas Harriehausen Siemens AG, Semiconductor Division P.O. Box 80 17 09, D-81617 Munich, Germany Phone: +49 89 4144-4762 September 9, 1996 INTERNATIONAL CADENCE
Verification & Design Techniques Used in a Graduate Level VHDL Course
Verification & Design Techniques Used in a Graduate Level VHDL Course Prof. Swati Agrawal, BE, MS (SUNY, Buffalo, NY USA) 1 Associate Professor, Department of Electronics & Telecommunication, Bhilai Institute
CAN & LIN Development Tool CLDT1004 HS CAN
HW Features : 1 x High Speed CAN Bus up to 1 Mbit/s 4 x digital Signal Output / Trigger Output easy synchronization between CAN Messages and physical HW Outputs SW Features : Can Bus Analyzing Tool Can
Software Version 10.0d. 1991-2011 Mentor Graphics Corporation All rights reserved.
ModelSim Tutorial Software Version 10.0d 1991-2011 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient
Altera Error Message Register Unloader IP Core User Guide
2015.06.12 Altera Error Message Register Unloader IP Core User Guide UG-01162 Subscribe The Error Message Register (EMR) Unloader IP core (altera unloader) reads and stores data from the hardened error
C O B A R 1 8R2 U s e r G u i d e P a g e 1. User Guide COBRA 18R2. Wireless Firing System. www.cobrafiringsystems.com
C O B A R 1 8R2 U s e r G u i d e P a g e 1 User Guide COBRA 18R2 Wireless Firing System C O B A R 1 8R2 U s e r G u i d e P a g e 2 TABLE OF CONTENTS 1. SYSTEM INTRO... 3 2. POWER ON... 4 3. REMOTE /
Using EDA Databases: Milkyway & OpenAccess
Using EDA Databases: Milkyway & OpenAccess Enabling and Using Scripting Languages with Milkyway and OpenAccess Don Amundson Khosro Khakzadi 2006 LSI Logic Corporation 1 Outline History Choice Of Scripting
Start Active-HDL by double clicking on the Active-HDL Icon (windows).
Getting Started Using Aldec s Active-HDL This guide will give you a short tutorial in using the project mode of Active-HDL. This tutorial is broken down into the following sections 1. Part 1: Compiling
SR. SIGNAL INTEGRITY ENGINEER
SR. SIGNAL INTEGRITY ENGINEER Specialist in electrical simulation of advanced package devices. This job requires an individual with outstanding electrical simulation and performance characterization skills
Jonathan C. Sevy. Software and Systems Engineering Experience
Jonathan C. Sevy jsevy@cs.drexel.edu http://gicl.cs.drexel.edu/people/sevy Software and Systems Engineering Experience Experienced in all phases of software development, including requirements, architecture
Introduction to the Quartus II Software. Version 10.0
Introduction to the Quartus II Software Version 10.0 Introduction to the Quartus II Software Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Introduction to the
IC-EMC Simulation of Electromagnetic Compatibility of Integrated Circuits
IC-EMC Simulation of Electromagnetic Compatibility of Integrated Circuits SUMMARY CONTENTS 1. CONTEXT 2. TECHNOLOGY TRENDS 3. MOTIVATION 4. WHAT IS IC-EMC 5. SUPPORTED STANDARD 6. EXAMPLES CONTEXT - WHY
High Performance Computing in CST STUDIO SUITE
High Performance Computing in CST STUDIO SUITE Felix Wolfheimer GPU Computing Performance Speedup 18 16 14 12 10 8 6 4 2 0 Promo offer for EUC participants: 25% discount for K40 cards Speedup of Solver
GnuRadio CONTACT INFORMATION: phone: +1.301.527.1629 fax: +1.301.527.1690 email: whitepaper@hsc.com web: www.hsc.com
GnuRadio CONTACT INFORMATION: phone: +1.301.527.1629 fax: +1.301.527.1690 email: whitepaper@hsc.com web: www.hsc.com PROPRIETARY NOTICE All rights reserved. This publication and its contents are proprietary
Serial port interface for microcontroller embedded into integrated power meter
Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia
Programmable Frequency Synthesizer
Sample Proposal Programmable Frequency Synthesizer Note from BF: This was submitted by a student in EE413 in a previous semester. The proposal has some shortcomings, but it will give you a good idea of
Installing HSPICE on UNIX, Linux or Windows Platforms
This document describes how to install the HSPICE product. Note: The installation instructions in this document are the most up-to-date available at the time of production. However, changes might have
Quartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
Getting off the ground when creating an RVM test-bench
Getting off the ground when creating an RVM test-bench Rich Musacchio, Ning Guo Paradigm Works rich.musacchio@paradigm-works.com,ning.guo@paradigm-works.com ABSTRACT RVM compliant environments provide
Optimizing VCO PLL Evaluations & PLL Synthesizer Designs
Optimizing VCO PLL Evaluations & PLL Synthesizer Designs Today s mobile communications systems demand higher communication quality, higher data rates, higher operation, and more channels per unit bandwidth.
ModelSim-Altera Software Simulation User Guide
ModelSim-Altera Software Simulation User Guide ModelSim-Altera Software Simulation User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01102-2.0 Document last updated for Altera Complete
A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design
A Faster, More Accurate Approach for System-Level Performance Verification of a Wireless RFIC Design By Nebabie Kebebew and Rich Davis, Cadence Wireless RFIC designs are growing more complex, increasing
Forum R.F.& Wireless, Roma il 21 Ottobre 2008 Dr. Emmanuel Leroux Country Manager for Italy emmanuel.leroux@cst.com 340 3768950
Simulazione 3D elettromagnetica Time e Frequency domain Forum R.F.& Wireless, Roma il 21 Ottobre 2008 Dr. Emmanuel Leroux Country Manager for Italy emmanuel.leroux@cst.com 340 3768950 1 Agenda CST company
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev. LAB 1 - Introduction to USRP
Department of Electrical and Computer Engineering Ben-Gurion University of the Negev LAB 1 - Introduction to USRP - 1-1 Introduction In this lab you will use software reconfigurable RF hardware from National
Below is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse:
PS-2 Mouse: The Protocol: For out mini project we designed a serial port transmitter receiver, which uses the Baud rate protocol. The PS-2 port is similar to the serial port (performs the function of transmitting
VHDL-Testbench as Executable Specification
VHDL- as Executable Specification Michael Pichler Zentrum für Mikroelektronik Aargau Fachhochschule Aargau, Steinackerstrasse 5, CH-5210 Windisch Web: www.zma.ch - E-mail: m.pichler@zma.ch Seite 1 Overview
Discrete event modeling: VHDL
12 Discrete event modeling: VHDL Peter Marwedel Informatik 12 Univ. Dortmund Germany Models of computation VHDL as a prominent example of discrete event modeling: Communication/ Computation FSM Data flow
Using Xbee 802.15.4 in Serial Communication
Using Xbee 802.15.4 in Serial Communication Jason Grimes April 2, 2010 Abstract Instances where wireless serial communication is required to connect devices, Xbee RF modules are effective in linking Universal
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
PADS PCB Design Solutions
start smarter D A T A S H E E T PADS PCB Design Solutions The standard in desktop PCB design FEATURES AND BENEFITS: Easy to learn and use Proven technology for PCB design, analysis, and verification Accurately
Tire pressure monitoring
Application Note AN601 Tire pressure monitoring 1 Purpose This document is intended to give hints on how to use the Intersema pressure sensors in a low cost tire pressure monitoring system (TPMS). 2 Introduction
SystemC Tutorial. John Moondanos. Strategic CAD Labs, INTEL Corp. & GSRC Visiting Fellow, UC Berkeley
SystemC Tutorial John Moondanos Strategic CAD Labs, INTEL Corp. & GSRC Visiting Fellow, UC Berkeley SystemC Introduction Why not leverage experience of C/C++ developers for H/W & System Level Design? But
Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc
Explore Efficient Test Approaches for PCIe at 16GT/s Kalev Sepp Principal Engineer Tektronix, Inc Copyright 2015, PCI-SIG, All Rights Reserved 1 Disclaimer Presentation Disclaimer: All opinions, judgments,
Reviving smart card analysis
Reviving smart card analysis Christopher Tarnovsky Karsten Nohl chris@flylogic.net nohl@srlabs.de Executive summary Modern smart cards should be analyzed 1. Smart card chips provide the trust base for
Concurrent Hardware/Software Development Platforms Speed System Integration and Bring-Up
Concurrent Hardware/Software Development Platforms Speed System Integration and Bring-Up Author: Ran Avinun, Cadence Design Systems, Inc. Hardware/software development platforms such as virtual prototyping,
Linux. Reverse Debugging. Target Communication Framework. Nexus. Intel Trace Hub GDB. PIL Simulation CONTENTS
Android NEWS 2016 AUTOSAR Linux Windows 10 Reverse ging Target Communication Framework ARM CoreSight Requirements Analysis Nexus Timing Tools Intel Trace Hub GDB Unit Testing PIL Simulation Infineon MCDS