Parallella: A Love Story Heterogeneous.. Parallel.. Efficient.. Open.. Andreas Olofsson MIT, Jan 7,2013

Transcription

1 Parallella: A Love Story Heterogeneous.. Parallel.. Efficient.. Open.. Andreas Olofsson MIT, Jan 7,2013 1

2 Adapteva Achieves 3 World Firsts 1. First processor company to reach 50 GFLOPS/W 3. First semiconductor company to successfully crowd source project 2. First open source OpenCL SDK in the mobile market OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. 2

3 Prologue 3

4 100,000,000 10,000,000 1,000,000 Why we need heterogeneous and parallel platforms 100,000 10,000 1, Von Neumann Saturation The Efficiency Gap System Processing Needs Legacy Processing Efficiency 4

5 ASIC, FPGA, DSP,? ASIC FPGA DSP Flexibility Poor Great Good Good Efficiency Great Good Good Fair Development Cost/Risk High Medium Medium Low Leverage Minimal Modest High Huge 5

6 A Practical Radar System Example Epiphany up FPGAs are great for front end DSP and connectivity. ADC/ DAC FPGA Storage Microprocessors are great for user interfacing, knowledge extraction, and system management. 1 Display DDR The missing piece: a math engine that is high performance, low-power and C-programmable. 6

7 Why SOC integration is so disruptive iphone4s ~58mm What if your smartphone disappears? A5X Chip ~16mm A5X die ~13mm 2X ARM A9 ~2mm FPU ~0.15mm 62 cm >1M X Volume Reduction cm 3 7

8 The Problem: SOCs are complex! $1,000,000,000 $100,000,000 $10,000,000 Per Product SOC R&D Costs What if you could do a 28nm chip for $100k? $1,000,000 $100,000 $10,000 8

9 Our Vision: True Heterogeneous Computing SYSTEM ON CHIP BIG BIG BIG BIG FPGA GPU Analog 1000 small Epiphany RISC s/dsps 9

10 Epiphany: Massive Task Parallelism Coprocessor to ARM/Intel 25mW per core C/C++ programmable 10

11 Programming Models MODEL#1 TASK QUEUE MODEL Up to 2 GFLOPS/core Supports standard C/C++ Cloud on a chip Task2 Task1 X86/ARM/FPGA Host Task4 Task3 MODEL #2 DATA PARALLEL MODEL opencl programmable Easy integration of C/C++ openmp/mpi roadmap Task1 X86/ARM/FPGA Host 11

12 Epiphany Silicon Devices elink I/O elink I/O elink I/O elink I/O Features: 16 RISC cores 512KB distributed memory IEEE Floating Point 32 distributed DMA engines 4 off-chip serial links 65nm Specifications: 1 GHz 32 GFLOPS 2 Watt Max Chip Power 512 GB/sec memory bandwidth 8GB/sec off chip BW Features: 64 RISC cores 2MB distributed memory IEEE Floating Point 128 distributed DMA engines 4 off-chip serial links 28nm Specifications: 800 MHz 100 GFLOPS 2 Watt Max Chip Power 1.6 TB/sec memory bandwidth 8GB/sec off chip BW 12

13 Parallella 13

14 Parallella Open Computing Open (and free ): Documentation Board design files Drivers Software Tools Accessible (NO NDAs!) $100 entry point ~4000 devs signed up in 4 weeks GPIO USB ZYNQ (ARM) E64 usd HDMI IO IO Rj45 1GB SDRAM GPIO USB 14

15 How cool is this? (1992) Connection Machine 5 (2012/2013) Parallella Board GPIO USB ZYNQ (ARM) E64 usd HDMI Rj45 1GB SDRAM GPIO USB 100 GFLOPS 100 KW $10M 100 GFLOPS 5 W (20k X) $200 (50k X) 15

16 Parallella Architecture SD CARD I2C UART Ethernet USB OTG USB 2.0 MIO Dual Core ARM A9 Zynq Hard Zynq FPGA Off Chip AXI BUS AXI MASTER AXI SLAVE AXI MASTER MEM CTRL elink Glue Logic DAC/ADC IF HDMI Controller O/S DRAM Epiphany Daughter Card Sandbox SHARED DRAM 16

17 Parallella Coprocessor Approach ARM runs Linux Epiphany accelerates key tasks Programmable logic makes anything possible Program Flow 1. ARM boots Linux. First stage boot loader from Flash, everything else from SD card. 2. Main application executes on ARM 3. Application sends critical tasks send to Epiphany using OpenCL or simple threads 4. ARM/Epiphany communication through shared DRAM buffer outside virtual memory of O/S. 17

18 Zedboard Introduction 18 18

19 The Future is Open Heterogeneous Massively Task-Parallel Efficient Grande Challenges Ahead Rebuild the computer ecosystem Rewrite billions of lines of code Retrain millions of programmers Rewrite the education curriculum 19