(T J ) range, but are tested and guaranteed at T A = +25 C. +Denotes lead-free package. V CC1 V CC2 V CC3 GNDIN+ IN+ 100Ω IN- MAX3970 MAX3971A

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1 ; Rev 2; 2/7 +3.3V, 1.7Gbps Limiting Amplifier General Description The is a compact 1.7Gbps limiting amplifier. It accepts signals over a wide range of input voltage levels and provides constant-level output voltages with controlled edge speeds. It functions as a data quantizer with a 24mV P-P differential CML output signal with a 1Ω differential termination. The has a disable function that allows the outputs to be squelched if required by the application. The is designed to work with the MAX397 transimpedance amplifier (TIA). The limiting amplifier operates on a single +3.3V supply and functions over a C to +8 C temperature range. The is offered in die form and in a compact 4mm 4mm 2-pin QFN and thin QFN package. VSR OC-192 Receivers 1Gbps Ethernet Optical Receivers 1Gbps Fibre Channel Receivers Pin Configurations appear at end of data sheet. Applications Features Single +3.3V Power Supply 2mV P-P Input Sensitivity 1.8ps Typical Deterministic Jitter (VIN = 8mV P-P ) Dice and 4mm 4mm QFN or Thin QFN Package Available Output Disable Feature Ordering Information PART TEMP RANGE PPACKAGE PKG CODE UGP C to +8 C 2 QFN-EP* G244-4 UTP C to +8 C 2 Thin QFN-EP* T244-3 UTP+ C to +8 C 2 Thin QFN-EP* T244-3 U/D C to +8 C Dice** *EP = Exposed pad. **Dice are designed to operate over a C to +11 C junctiontemperature (T J ) range, but are tested and guaranteed at T A = +2 C. +Denotes lead-free package. Typical Application Circuit +3.3V +3.3V.1μF SUPPLY FILTER CZ- CZ+ V CC1 V CC2 V CC3.1μF.1μF TIA.1μF 1Ω.1μF MAX397 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC1, V CC2, V CC3...-.V to +. V Voltage at,,, CZ+, CZ-,,...+.V to (V CC +.V) Differential Voltage Between CZ+ and CZ-...±1V Differential Voltage Between and...±2.v Continuous Power Dissipation (T A = +8 C) 2-Pin QFN (derate 2mW/ C above +8 C)...1.3W Operating Ambient Temperature Range...-4 C to +8 C Storage Temperature Range...- C to +1 C Die Attach Temperature...+4 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V CC = +3.V to +3.6V, output load = to V CC, T A = C to +8 C, unless otherwise noted. All AC parameters are measured with a PRBS pattern applied to the input at 1.7Gbps. Typical values are at V CC = +3.3V, T A = +2 C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current I CC 8 ma Small-Signal Bandwidth BW 1 GHz Input Sensitivity V min (Notes 1, 2) 2 mv P-P Input Overload V max (Note 1) 12 mv P-P Low-Frequency Cutoff CZ =.1µF (Note 1) 6 7 khz mv P-P input (Notes 1, 3) Deterministic Jitter 1mV P-P input (Notes 1, 3) mV P-P input (Notes 1, 3) ps 12mV P-P input (Notes 1, 3) Random Jitter 2mV P-P < input < 12mV P-P (Notes 1, 4) ps RMS Transition Time t r, t f 2% to 8%, differential output (Note 1) 2 3 ps Data Input Impedance Single ended 42 8 Ω Data Output-Voltage Swing Data Output Voltage when Disabled Differential signal amplitude between and Differential signal amplitude between and mv P-P.2 mv P-P Data Output Common-Mode Voltage Data Output Impedance Single ended 42 8 Ω Data Output Offset when is High V CC - 7 mv 7 2 mv Disable Input Current 3 6 µa High Voltage V IH 2 V Low Voltage V IL.8 V Disable Response Time 2 ns Note 1: Guaranteed by design and characterization. Note 2: The output signal amplitude at the sensitivity is >.9 the amplitude with large input. Note 3: Deterministic jitter is measured with K28. pattern ( ) at 1.7Gbps. It is the peak-to-peak deviation from the ideal time crossing, measured at the zero-level crossing of the differential output. Note 4: For a bit-error rate of 1-12, the peak-to-peak random jitter is 14.1 the RMS random jitter. 2

3 Typical Operating Characteristics (V CC = +3.3V, output load = to V CC, T A = +2 C, unless otherwise noted.) OUTPUT EYE DIAGRAM (INPUT SIGNAL = 1mV P-P, AT 1.7Gbps) PRBS toc1 OUTPUT EYE DIAGRAM (INPUT SIGNAL = mv P-P, AT 1.3Gbps) PRBS toc2 OUTPUT EYE DIAGRAM (INPUT SIGNAL = 12mV P-P, AT 1.3Gbps) PRBS toc3 4mV/div 4mV/div 4mV/div 2ps/div 2ps/div 2ps/div 4mV/div OUTPUT EYE DIAGRAM (INPUT SIGNAL = 8mV P-P, AT 1.7Gbps) PRBS toc4 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. AMBIENT TEMPERATURE toc GAIN (db) SMALL-SIGNAL GAIN UGP toc ps/div TEMPERATURE ( C) FREQUENCY (GHz) 27 2 OUTPUT VOLTAGE vs. INPUT VOLTAGE toc RANDOM JITTER vs. INPUT AMPLITUDE toc8 6 DETERMINISTIC JITTER vs. INPUT AMPLITUDE 1.7Gbps, K28., V CC = +3V, TEMP = 8 C MAX39971A toc9 VOUT (mvp-p) RANDOM JITTER (psrms) JITTER (psp-p) V IN (mv P-P ) , INPUT AMPLITUDE (mv P-P ) , INPUT AMPLITUDE (mv P-P ) 3

4 Typical Operating Characteristics (continued) (V CC = +3.3V, output load = to V CC, T A = +2 C, unless otherwise noted.) JITTER (psp-p) DETERMINISTIC JITTER vs. TEMPERATURE V IN = mv V IN = 8mV 1.7Gbps with K AMBIENT TEMPERATURE ( C) toc1 LOSS (db) INPUT RETURN LOSS (S11) (V CC = +3.3V) FREQUENCY (GHz) toc11 LOSS (db) OUTPUT RETURN LOSS (S22) (V CC = +3.3V) FREQUENCY (GHz) toc OUTPUT NOISE POWER (INPUT CONNECTED TO TO ) toc13 4 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY toc INPUT COMMON-MODE REJECTION RATIO vs. FREQUENCY V IN = V = V toc1 NOISE POWER (dbm) PSRR (db) 4 3 CMRR (db) TEMPERATURE ( C) 3 1k PSRR = -2log ΔV OUT /ΔV CC 1k 1M FREQUENCY (Hz) 1M 1M CMRR = -2log(V OUT /V IN ) 4 1 1M 1M 1M 1G 1G FREQUENCY (Hz) 4

5 PIN NAME FUNCTION 1 Input Ground for Shielding Input Signal. Not connected internally. 2 Noninverting Input Signal 3 Inverting Input Signal 4 Input Ground for Shielding Input Signal. Not connected internally., 7, 9, 1 No Connection. Leave unconnected. 6, 8, 11 Ground 12, 1 V CC3 Output Circuitry Power Supply 13 Inverting Output of Amplifier 14 Noninverting Output of Amplifier Pin Description 16 When is connected to V CC or left floating, outputs are disabled. When is connected to, outputs are enabled. 17 V CC2 Power Supply to Circuitry other than Input and Output Circuits 18 CZ+ Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed Description section. 19 CZ- Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed Description section. 2 V CC1 Input Circuitry Power Supply EP Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation. Detailed Description and Applications Information Figure 1 is a functional diagram of the limiting amplifier. The signal path consists of an input buffer followed by a gain stage and output amplifier. A feedback loop provides offset correction by driving the average value of the differential output to zero. 1Ω INPUT AMPLIFIER Figure 1. Functional Diagram OFFSET CORRECTION AMP GAIN 42dB CZ- CZ LOWPASS FILTER CZ+ OUTPUT AMPLIFIER Gain Stage and Offset Correction The limiting amplifier provides approximately 42dB gain. The large gain makes the amplifier susceptible to small DC offsets, which cause deterministic jitter. A low-frequency loop is integrated into the limiting amplifier to reduce output offset, typically to less than 2mV. The external capacitor (CZ) is required for stability and to set the low-frequency cutoff for the offset correction loop. The time constant of the loop is set by the product of an equivalent 2kΩ on-chip resistor and the value of the off-chip capacitor (CZ). For stable operation, the minimum value of CZ is.1µf. To minimize patterndependent jitter, CZ should be as large as possible. For 1Gbps ethernet and SONET applications, the typical value of CZ is.1µf. Keep CZ close to the package to reduce parasitic inductance. CML Input Circuit The input buffer is designed to accept CML input signals such as the output from the MAX397 transimpedance amplifier. An equivalent circuit for the input is shown in Figure 2. For lowest deterministic jitter in all operating conditions, AC-coupling capacitors are recommended on the input.

6 V CC1 1kΩ +3.3V ESD STRUCTURES Figure 2. CML Input Equivalent Circuit 2μA V CC3 Figure 4. TTL Input Stage DATA Q3 Q4 Q1 Q2 ESD STRUCTURES L +3.3V SUPPLY FILTER.1μF.1μF.1μF Figure 3. CML Output Equivalent Circuit V CC1 V CC2 V CC3 CML Output Circuit An equivalent circuit for the output network is shown in Figure 3. It consists of a pair of resistors connected to V CC driven by the collectors of an output differential transistor pair (Q1 and Q2). The differential output signals are clamped by transistors Q3 and Q4 when the input is high. Function A logic signal can be applied to the pin to squelch the output signal. When the output is disabled, an offset is added to the output, preventing the following stage from oscillating, if DC-coupled. See Figure 4 for the input stage of the function. Figure. Power-Supply Filter 6

7 Layout Considerations Circuit board layout and design can significantly affect the performance of the. Use good high-frequency techniques, including fixed-impedance transmission lines for the high-frequency data signal. Use a multilayer board with solid ground plane. Minimize the inductance between the and the ground plane. The uses three power-supply pins (V CC1, V CC2, and V CC3 ). The input circuitry of the is supplied by V CC1. The output drivers have a separate supply (V CC3 ), which usually has large pulsing currents. All other circuitry is powered by V CC2. It is possible to simply connect the three pins together. However, using a supply filter ensures better isolation of the input circuitry. For optimal isolation, Figure shows a possible supplyfiltering circuit. Element L, a ferrite bead, provides isolation between a noisy V CC3 and a sensitive V CC1. TRANSISTOR COUNT: 324 PROCESS: SiGe Bipolar SUBSTRATE: Electrically Isolated Chip Information TOP VIEW CZ VCC CZ VCC V CC V CC3 11 QFN 4mm x 4mm THE EXPOSED PAD MUST BE SOLDERED TO FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE VCC1 6 7 Pin Configurations CZ+ VCC V CC CZ- V CC3 THIN QFN 4mm x 4mm THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE. 7

8 V CC1 CZ- CZ+ V CC2 Chip Topography V CC3.2" (1.33mm) V CC3 NC (, ).42" (1.1mm) 8

9 PAD NUMBER X DIMENSION (µm) Y DIMENSION (µm) Chip Topography (continued) Pad dimensions: PASSIVATION OPENING: 94.4µm 94.4µm METAL: 12.4µm 12.4µm All measurements specify the lower left corner of the pad. Refer to Application Note H Fan-8.: Understanding Bonding Coordinates and Physical Die Size. Package Information For the latest package outline information, go to Revision History Rev ; 4/2: Initial data sheet release. Rev 1; /3: Added package code to Ordering Information and deleted EP references from Ordering Information (page 1); updated package drawing (page 1). Rev 2; 2/7: Added thin QFN package (pages 1 and 7); removed package drawing. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products.