MP W 802.3af PoE Powered Device (PD) Interface and PWM Controller

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1 MP W 802.3af PoE Powered Device (PD) Interface and PWM Controller DESCRIPTION The MP8005 is a complete integrated IEEE 802.3af POE compliant Powered Device (PD) power supply solution. It includes the PD control function and an isolated/non isolated synchronous regulator controller. Thermal protection is built in to accommodate both transient and/or overload conditions, shutting the part down and protecting the input source as well as the output load depending on the particular fault conditions. Inrush current limiting is included to slowly charge the input capacitor without interruption due to die heating, a problem encountered without the current limit foldback feature. The desired output voltage is user programmable through the selection of an external resistor divider. EVALUATION BOARD REFERENCE Board Number Dimensions EV8005DF-00A 5.33 x1.75 x0.8 ( LxWxH) FEATURES Meets IEEE 802.3af Specifications 100V, 1Ω Integrated switch 460mA max, Temperature Compensated Current Limit Isolated Synchronous Controller 20 pin TSSOP Package APPLICATIONS VoIP Telephones Network Cards Security Camera Systems Safety Backup Power Remote Internet Power All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. MPS and The Future of Analog IC Technology are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL ISOLATED APPLICATION MP8005 Rev

2 ORDERING INFORMATION Part Number* Package Top Marking Temperature MP8005DF TSSOP-20-EP MP8005DF 40 C to +85 C For Tape & Reel, add suffix Z (e.g. MP8005DF Z). For Lead Free, add suffix LF (e.g. MP8005DF LF Z) PACKAGE REFERENCE VCC MAINGATE SYNCGATE CSS ENABLE ILIM CLASS DET VSS NC AGND ISENSE RDELAY VFB COMP VDD PG RTN RTN NC ABSOLUTE MAXIMUM RATINGS (1) V DD, RTN V to +100V PG, DET V to +57V V CC, CLASS V to +10V I LIM, CSS, ENABLE V to +5V I SENSE V to +28V COMP V to +3V FB V to +1.3V Continuous Power Dissipation (T A = +25 C) (2) W Junction Temperature C Lead Temperature C Storage Temperature C to +150 C Recommended Operating Conditions (3) Supply Voltage V DD...0V to 57V Output Current I OUT... 0 to 0.4A Junction Temperature T J C to +125 C Thermal Resistance (4) θ JA θ JC TSSOP-20-EP C/W Notes: 1) Exceeding Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at or above these conditions is not implied Exposure to these conditions for extended periods may affect device reliability. 2) The maximum allowable power dissipation is a function of the maximum junction temperature. T J (MAX) the junction-toambient thermal resistance. θ JA and the ambient temperature, T A the maximum allowable power dissipation at any ambient temperature is calculated using: P D (MAX)=(T J (MAX)-T A )/ θ JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. MP8005 Rev

3 ELECTRICAL CHARACTERISTICS V DD = 48V, all voltages with respect to V SS, V SS = 0V; R DET = 26.1kΩ, R CLASS = 4.42KΩ, R ILIM = 178kΩ, T A = 25 C, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units VCC Undervoltage Lockout VCC On/Off Voltage Hysteresis Internal Divider (I Q ) V 1 V Shutdown Current I S EN/SS =0V, V IN =9V 50 μa Quiescent Current Main Gate Driver Impedance (Sourcing) Main Gate Driver Impedance (Sinking) Synchronous Gate Driver Impedance (Sourcing) Synchronous Gate Driver Impedance (Sinking) Delay after Synchronous Gate Error Amplifier Transconductance I Q Output not switching, no load, V FB =1V, V CC =9V μa V CC =9V, V GATE =5V 16 Ω V CC =9V, I GATE =5mA 5.0 Ω V CC =9V, V SYNCGATE =5V 16 Ω V CC =9V, I GATE =5mA 5.0 Ω R DELAY =100KΩ 50 ns V FB connected to V COMP/RUN. Force ± ± 10μA to V COMP/RUN ma/v Maximum comp Current Sourcing and Sinking 40 μa Error Amplifier Translator Gain (5) A ET V/V Switching Frequency f S khz Thermal Shutdown 150 C Maximum Duty Cycle % Minimum On Time t ON 200 ns ISENSE Limit mv FB Voltage V FB V FB Bias Current I FB Current flowing out of part 50 na ISENSE Bias Current I SENSE Current flowing out of part 50 na Enable On Threshold V EN High-to-Low V Enable Hystersis V EN 50 ma Soft Start Current I SS 4 μa MP8005 Rev

4 ELECTRICAL CHARACTERISTICS (continued) V DD = 48V, all voltages with respect to V SS, V SS = 0V; R DET = 26.1kΩ, R CLASS = 4.42KΩ, R ILIM = 178kΩ, T A = 25 C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units Detection Detection on V DET_ON V DD =V RTN =V PG =1.9V 1.9 V Detection off Detection on/off Hysteresis V DET_OFF V DET_H V DD =V RTN =V PG =11V 11 V Falling below 11V on Threshold 0.2 V DET Leakage Current V DET_LK V DET =V VDD =57V, Measure IDET μa Detection Current Classification I DET V VDD =V RTN R DET =26.1kΩ, Measure I VDD +I RTN +I DET V DD = 3V μa V DD = 10.1V μa V CLASS Output Voltage V CL Over a Load Range of 1mA to 41.2 ma V Classification Current Classification Lower Threshold Classification Upper Threshold IC Supply Current during Classification I CLASS R CLASS =4420Ω, 13 V VDD 21V (guar by V CL ) R CLASS =953Ω, 13 V VDD 21V (guar by V CL ) R CLASS =549Ω, 13 V VDD 21V (guar by V CL ) R CLASS =357Ω, 13 V VDD 21V (guar by V CL ) R CLASS =255Ω, 13 V VDD 21V (guar by V CL ) V CL_ON Regulator Turns on, V VDD Rising V V CU_OFF Regulator Turns off, V VDD Rising V V CU_H Hysteresis 0.4 V I IN_CLASS V DD = 17.5V, CLASS Floating, RTN Tied to VSS ma μa Leakage Current I LEAKAGE V CLASS = 0 V, V VDD = 57V 1 μa Pass Device On Resistance R DS(ON) I RTN= 300mA Ω Leakage Current I SW_LK V VDD =V RTN =57V 1 15 μa Current Limit I LIMIT V RTN =1V ma Inrush Limit I INRUSH V RTN =2V, R ILM =178kΩ ma Inrush Current Termination V RTN Falling, R IPEAK = 178kΩ, Inrush State Normal Operation % MP8005 Rev

5 ELECTRICAL CHARACTERISTICS (continued) V DD = 48V, all voltages with respect to V SS, V SS = 0V; R DET = 26.1kΩ, R CLASS = 4.42KΩ, R ILIM = 178kΩ, T A = 25 C, unless otherwise noted. Parameter Symbol Condition Min Typ Max Units PG Latchoff Voltage Threshold Rising Latchoff Voltage Threshold Falling V RTN Rising (5) V V RTN Falling 1.2 V PG Deglitch Delay Rising and Falling PDG (5) μs Output Low Voltage I PG = 400 μa V Leakage Current V PG = 57 V, V RTN = 0 V μa UVLO Voltage at V VDD V VDD Rising (including 1.4V Diode drop) V Thermal Shutdown Thermal Counter Reset Voltage Bias Current Operating Current Notes: 5) Guaranteed by Design. V VDD Falling (including 1.4V Diode drop) VCRST Must Drop below Classification Range 10.8 V I Q (VDD) VDD = 48V, Pins 5, 6 Floating Measure IVDD μa MP8005 Rev

6 PIN FUNCTIONS Pin # Name Description 1 VCC 10V Shunt Supply Voltage used for the switching regulator controller 2 MAINGATE Output drive to the Main Gate 3 SYNCGATE Output drive to the Synchronous Gate 4 CSS Soft-start ramping capacitor 5 ENABLE On/Off control input to the switching regulator 6 ILIM Startup I LIM Value Setting Resistor terminal (optional at this point). 7 CLASS Classification Resistor terminal. 8 DET 26.1kΩ Detection Resistor terminal 9 VSS Ground return to the Ethernet negative supply. 10 No Connection 11 No Connection 12 RTN Powered Device Negative Power Terminal. 13 RTN Powered Device Negative Power Terminal. 14 PG Active low power good indication. 15 VDD Positive Power Supply Terminal for the Ethernet PD control function. 16 COMP Switching regulator compensation terminal. 17 VFB Switching regulator voltage feedback terminal. 18 RDELAY Resistor programming for setting the delay from the Sync gate going low to the Main gate going high. 19 ISENSE Main Switch current sensing terminal. 20 AGND Switching regulator controller ground return; Returns to the RTN pin. MP8005 Rev

7 TYPICAL PERFORMANCE CHARACTERISTICS EFFICIENCY (%) Efficiency vs. Load Current V DD =40V V DD =60V LOAD CURRENT (A) DIFFERENCE (%) Output Voltage vs. Load Current V DD =40V LOAD CURRENT (A) V DD =60V I IN (ma) V CC Regulator Line Regulation V DD Increasing 25 V DD Decreasing V DD (V) Start Up V DD =48V, I LOAD =2.6A Shut Down V DD =48V, I LOAD Transient Response V DD =48V, I LOAD= 2.6A, 0 to 2.6A Load Slew:1.0A/1uS V RTN 50V/div V PG 5V/div V OUT /AC 200mV/div V PG 5V/div V OUT 5V/div I IN 0.5A/div 20ms/div V RTN 1V/div V DD 20V/div V PG -V RTN I RTN 0.5A/div 200ms/div I OUT 1A/div 200us/div Output Ripple V DD =60V, I LOAD =4A V OUT /AC 200mV/div V SW 5V/div 2us/div MP8005 Rev

8 BLOCK DIAGRAM VDD DET DETECTION MP8005 OSCILLATOR 1.2v PG VCC ENABLE CSS CLASS CLASSIFICATION COMP 1.2v Vfb ILIM STARTUP PWM CONTROL LOGIC DELAY RDELAY MAINGATE ISENSE CONTROL LOGIC SYNCGATE AGND VSS RTN Figure 1 Block Diagram MP8005 Rev

9 OPERATION The MP8005 operates in the manner described here and in the IEEE 802.3af Powered Device (PD) Specification. This device (along with the power sourcing element (PSE)) operates as a safety device to supply potentially lethal voltages only when the power sourcing element recognizes a unique, tightly specified resistance at the end of an unknown length of Ethernet cable. A 25kΩ resistance is presented as a load to the PSE in Detection Mode, when the PSE applies two safe voltages of less than 10.1V each while measuring the change in current drawn in order to determine the load resistance. If the PSE sees the correct load, then it may either further increase the applied voltage to enter the classification range of operation or switch on the nominal 48V power to the load. The classification mode can further specify to the PSE the expected load range of the device under power so that the PSE can intelligently distribute power to as many loads as possible (within its maximum current capabilities). If a classification resistance is not present, the PD load is assumed to be the maximum of approximately 13 Watts. The classification mode is active between 14.5V and 20.5V. The main power switch will pass a limited current above 31V, charging the external DC-to-DC converter s input capacitor in a controlled manner. The charging will continue until the controlled current drops below either an externally programmed limiting level or 450mA, depending upon the Rlim current setting resistor. The main power switch is internally thermally protected to 100V by reducing the output current using a foldback technique. The required power dissipation of the IC drops from the allowed peak value of 26W (450mA x 57V) to 0.16W ((450mA) 2 x R ON ) during the normal operation at turn-on. The minimum allowed capacitance of 5µF will charge in 500µs. A larger capacitor will take a proportionally longer time to charge due to the constant current charging method. A capacitor that is too large will overheat the part and force it into thermal shutdown. The IC will reattempt charging for a number of cycles but ultimately will be shut down until the input voltage from the PSE is recycled. This is the way the IC protects itself under overload and/or shorted conditions. Once the capacitor tied between Vdd, Ethernet input positive supply and the RTN pin is charged to within a volt of the applied Ethernet input supply potential, the PG output is driven low to enable the switching regulator controller. This delay prior to turning on the switching regulator is required in order to minimize the power dissipation incurred during the startup of the controller. The capacitance tied across the Vdd and RTN lines provide the inductor ripple current while maintaining a small voltage differential such that the average current flowing in the RTN line is under the current limit level. Without a storage capacitance at this point, instantaneous current peaks, required by the switching regulator during normal operation, would send the main PD switch (at the RTN pin) in and out of current limit resulting in high power dissipation due to the resultant voltage across the switch. A current greater than the current limit value would increase the voltage on the RTN pin to the Ehternet Input supply voltage immediately resulting in power dissipation levels that would immediately shut down the PD switch without the required storage capacitor. The soft-start capacitor, CSS, slows the rate of current delivery to the switching regulator to a value that can be delivered by the storage capacitor/pd switch. A resistor tied between the Rdelay pin and AGND sets a time delay between the falling edge of the synchronous gate and the rising edge of the main gate. This delay can be set to compensate for system delays caused by architectural structures of the circuit being used. An isolated secondary type power supply having a transformer in the feedback loop may require extra time due to the electrical path incurred. The delay time is adjustable from as little as 40nSec to over 200nSec through the choice of resistance value. A smaller resistance will result in a shorter delay. Nominal values range from kω for time delays from 40nSec to 200nSec. The delay MP8005 Rev

10 is very important in that it prevents cross conduction of the switching MOSFETS that either severely reduces efficiency or even worse, a switching MOSFET failure. The output drive levels of the main and synchronous gate are in the hundreds of ma through a 0 to 10V voltage potential. A normal threshold MOSFET (Vth typ. 3.5V) having low gate charge (less than 10 10V drive) is recommended. The nominal range of the ISENSE pin is set to a maximum of 200mV but should be designed such that 100mV across the sense resistor provides the maximum current that is expected for the nominal load. This will provide enough headroom for typical applications. MP8005 Rev

11 PACKAGE INFORMATION TSSOP-20F (EXPOSED PAD) 4.40 TYP TYP 0.40 TYP 0.65 BSC PIN 1 ID TYP 5.80 TYP 1 10 TOP VIEW RECOMMENDED LAND PATTERN BSC 1.20 MAX SEATING PLANE SEE DETAIL "A" SIDE VIEW FRONT VIEW GAUGE PLANE 0.25 BSC o -8 o DETAIL A BOTTOM VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION ACT. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP8005 Rev

12 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Monolithic Power Systems (MPS): MP8005DF-LF MP8005DF-LF-Z