Example of a high-end processor architecture: Intel Haswell

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1 Example of a high-end processor architecture: Intel Haswell 1 Instruction Set Architecture Intel64 Instruction Set Architecture Can run in both 64-bit and 32-bit mode binary compatible with 32-bit IA-32 ISA existing applications can directly be executed without recompilation Binary compatible with the 16-bit 8086 processor (from 1978) with some limitations Very large CISC-like instruction set instruction encoding is very complex and irregular The execution mechanism (the microarchitecture) is very RISC-like load-store architecture machine instructions are translated into micro-operations (µops) immediately after they are fetched 2 1

2 General purpouse registers In 64-bit mode, the processor has bit 63 general-purpose integer registers RAX RBX in 32-bit mode it has 8 32-bit registers RCX RDX RBP Instruction pointer, RIP RSI RDI points to the next instruction to be RSP R8 executed R9 R10 Stack pointer, RSP R11 R12 points to top of stack R13 R14 R15 Base pointer, RBP RFLAGS points to data on the stack RIP Status flags, RFLAGS consists of status bits describing the current status of the processor Carry, Parity, Auxiliary Carry, Zero, Sign, Overflow, EAX EBX ECX EDX EBP ESI EDI ESP EFLAGS EIP 3 General purpouse registers (cont.) Can also refer to 32,16-and 8-bit parts of the registers 32-bit registers: EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP EFLAGS, EIP 16-bit registers: AX, BX, CX, DX, SI, DI, BP, SP FLAGS, IP 8-bit registers: AH/AL, BH/BL, CH/CL, DH/DL EAX AX AH AL RAX EAX AX 4 2

3 Vector and floating-point registers bit registers for scalar floating-point and vector operations called YMM0 YMM15 The AVX2 extension is the latest vector extension, introduced in the Haswell microarchitecture AVX2 AVX SSE2 SSE MMX AVX-512 will further extend the vector registers to 512 bits There are also 8 80-bit floating-point registers in the x87 floating-point unit modern compilers do not use the x87 FPU for floating-point instructions instead uses scalar fp-operations on the vector registers 5 Floating point operation with the AVX unit The AVX vector unit is used for floating-point operations can operate on both scalar and vector data scalar operations are used for normal (non-vectorized) floating-point operations Scalar operation: x = x+y arithmetic instructions on one single floating-point value X3 Y3 X2 Y2 X1 Y1 X0 Y0 + Vector operation: X= X+Y X3 X2 X1 X0+Y0 arithmetic instructions on a short vector of 2, 4 or 8 floating-point values X3 X2 X1 X0 Y3 Y2 Y1 Y X3+Y3 X2+Y2 X1+Y1 X0+Y0 6 3

4 YMM registers bit YMM registers can hold scalar or vector values Independent of the general-purpose registers Can only be used for operations on data, not addresses Scalar floating-point instructions have a prefix that describes the size of the operand d = double-precision, s = single-precision Examples: YMM0 YMM1 YMM2 YMM3 YMM4 YMM5 YMM6 YMM7 YMM8 YMM9 YMM10 YMM11 YMM12 YMM13 YMM14 YMM15 mulss multiply scalar single-precision floating-point value mulsd multiply scalar double-precision floating-point value movss move scalar single-precision floating-point value Name of vector instructions have a byte p (stands for packed) Example: mulpd multiply packed double-precision floating point values Instruction set Very large CISC-like instruction set Instructions can roughly be divided into the following groups data transfer instructions (MOV, CMOV) copies data between registers or registers and memory data conversion (CBW, CWD) converts data between different formats arithmetic (ADD, SUB, MUL, IMUL, DIV, IDIV) rotate and shift (ROL, ROR, SAL, SAR) cyclic and non-cyclic shifts logical instructions (AND, OR, XOR, NOT) bitwise logical operations compare and test (CMP, TEST) compares values and sets bits in FLAGS control transfer instructions ( JMP, JZ, JNZ, CALL, RET) branches based on status bits i FLAGS miscellaneous instructions (NOP, CPUID, LEA) 8 4

5 Instruction format Instructions are encoded into binary opcodes of length between 1 and 15 bytes Prefixes Opcode ModR/M SIB Displacement Immediate up to four prefix bytes prefixes modify an instruction s default address or operand size, segment or invoke some special function of the operation 1 2 opcode bytes 1 byte optional ModRM (Mode-Register-Memory) and SIB (Scale-Index-Base) describes the registers and addressing mode used 1, 2 or 4 bytes displacement 1, 2 or 4 (or 8) bytes immediate Instructions can be between 1 and 15 bytes long commonly used instructions and instructions with fewer operands have a shorter encoding 9 Intel Haswell microarchitecture Introduced in 2013 designed to be scalable up to large numbers of cores highly flexible design that can support different market segments, including lowpower mobile devices Multicore design with 2-way hyper-threading available in versions with 2 to 18 cores 1.4 billion transistors, 22 nm process technology clock frequency up to 3.6 GHz advanced power management Can at most execute 8 µops each clock cycle however, typical pipeline throughput is 4 µops/cycle Improved memory bandwidth integrated on-chip memory controller 48 bit virtual addresses, 40 bit physical addresses L1 and L2 private for each core unified L3 cache shared by all cores 10 5

6 Pipeline organization stage pipeline depending on the instruction 4 instruction decoders µop cache holds decoded µops Reorder buffer, 192 µops Large register file 8 ports through which µops can be issued to the functional units 11 Instruction fetch and decode Instruction fetch unit can fetch 16 bytes of code per clock cycle from L1 instruction cache fetched x86 instructions are placed in 2 instruction queues of length 20 instructions, one for each thread 4 instruction decoders one for complex instructions (generating 1-4 fused µops / instruction) three for simple instructions (generating 1 µop / instruction) Instructions generating more than 4 µops are decoded from microcode Decoded instructions are placed in a queue of size 56 µops shared by both threads µop cache of size 1.5 K µops stores already decoded instruction acts like an additional L0 instruction cache, but holds decoded µops small loops can be executed without repeated decoding 12 6

7 Macro-op and micro-op fusion The instruction decoding uses two techniques that improve the instruction execution MacroOp-fusion commonly used sequences of two assembly-language instructions are decoded and combined into one single µop can be executed and retired as one single µop Example: CMP and Jcc (compare and branch conditionally) MicroOp-fusion two closely related µops are encoded into one micro-operation Example: ADD RAX, [MEM] # add the value in RAX to memory location MEM without micro-op fusion this would generate three µops: load [MEM], R10 add R10, RAX store RAX, [MEM] with micro-op fusion the load and add are combined into one single µop 13 Branch prediction The branch prediction mechanism has been improved in Haswell, but Intel does not publish any details about it Observations indicate that there are two branch prediction methods one that predicts branches for code executed from µop cache fast, but uses a rather small history buffer one for other branches, executed from instruction cache based on a larger branch target buffer, but slower the second-level predictor can handle much more complex patterns than the first level predictor Branch misprediction penalty is clock cycles The return address stack is of size

8 Register renaming The renaming mechanism maps architectural registers onto the physical register file renames physical registers to the internal register file also load/store operations are renamed eliminated name dependences some register-to-register moves can be executed by the renamer without using any functional unit Reorder buffer is of size 192 µops The Branch Order Buffer is used to resolve branch mispredictions contains information about last consistent architectural state Scheduler with 60 entries for all types of µops stores decoded and renamed operations that are waiting to be issued similar to the reservation stations when a µop is ready it is issued by the scheduler through a dispatch port to a functional unit 15 Execution ports Superscalar out-of-order instruction execution can issue at most 8 micro-ops in one clock cycle 4 µops can be retired per clock cycle The scheduler issues µops to the functional units through 8 execution ports Many operations with a long latency are pipelined to improve instruction throughput efficient support for vector execution (AVX2) most vector instructions have a throughput of one clock cycle Supports a new vectorized FMA instruction Fused Mutiply-Add: x = x + y*z 16 8

9 Execution units 8 execution ports some of the execution units are duplicated, can do two µops per clock cycle Two new ports added since the previous microarchitecture (Sandy Bridge) integer ALU and memory port The 8 oldest ready µops can be issued each clock cycle Both ports 0 and 1 can do a vector FMA each clock cycle doubles the number of fp operations per clock cycle, compared to Sandy Bridge can do 16 FLOPs per clock cycle 17 Load/store units Load and store buffers hold µops that do memory access issued by the scheduler to the load/store units 4 load/store units 3 address generation units (AGUs) for both load and store operatios 1 unit dedicated to store operations 2-level Translation Lookaside Buffer (TLB) L1 DTLB is only for data accesses (DTLB) can hold addresses for 4KB, 2MB and 1 GB pages 4-way set associative L2 TLB holds 1024 addresses 8-way set associative Improved access to unaligned data Advanced memory prefetch recognizes address patterns and prefetches both instructions and data into L1 or L2 cache 18 9

10 Cache hierarchy Private L1 cache for each core L1 instruction cache 32 KB, 8-way set associative L1 data cache, 32 KB, 8-way set associative, writeback latency 4 clock cycles Unified L2 cache for each core 256 KB, 8-way set associative, writeback access time 11 clock cycles Cache line size 64 bytes Up to 8 MB L3 cache, shared by all cores 16 way set associative access time about 30 clock cycles 19 Power management Advanced power control built-in real-time sensors for temperature, current and power also uses information about OS requests for each core uses this information to make decisions about when a core can be powered down individual cores can be shut down to save power Turbo boost technology automatically increases the clock frequency when the system detects that it is running below its power limit based on information about nr. of active cores, type of workload, current consumption, power consumption and temperature dynamic on-demand overclocking 20 10

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