NLAS :1 Mux/Demux Analog Switches

Transcription

1 NLAS : Mux/Demux Analog Switches The NLAS is an advanced CMOS analog switch fabricated with silicon gate CMOS technology. It achieves very high speed propagation delays and low ON resistances while maintaining CMOS low power dissipation. The device consists of a single : Mux/Demux (SPDT), similar to ON Semiconductor s NLAS analog and digital voltages that may vary across the full power supply range (from to GND). The inhibit and select input pins have over voltage protection that allows voltages above up to 7. to be present without damage or disruption of operation of the part, regardless of the operating voltage. Features High Speed: t PD = ns (Typ) at =. Low Power Dissipation: I CC = A (Max) at T A = C High Bandwidth, Improved Linearity, and Low RDS ON INH Pin Allows a Both Channels OFF Condition (With a High) RDS ON, Performance ery Similar to the NLAS Break Before Make Circuitry, Prevents Inadvertent Shorts Useful For Switching ideo Frequencies Beyond MHz Latchup Performance Exceeds ma ESD Performance: HBM > ; MM >, CDM > Tiny US Package, Only. X. mm These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant US US SUFFIX CASE 9 MARKING DIAGRAM AC M AC = Specific Device Code M = Date Code = Pb Free Package (Note: Microdot may be in either location) INH H L L FUNCTION TABLE Select X L H Ch OFF ON OFF Ch OFF OFF ON COM ORDERING INFORMATION INH 7 CH Device Package Shipping N/C CH NLASUSG US (Pb Free) / Tape & Reel GND Select Figure. Pin Assignment For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. Semiconductor Components Industries, LLC, July, Rev. Publication Order Number: NLAS/D

2 NLAS MAXIMUM RATINGS Parameter Symbol alue Unit Positive DC Supply oltage. to +7. Digital oltage (Select and Inhibit) IN. is +7. Analog oltage ( CH or COM ) IS. is +. DC Current, Into or Out of Any Pin I IK ma Storage Temperature Range T STG to + C Lead Temperature, mm from Case for Seconds T L C Junction Temperature under Bias T J + C Thermal Resistance JA C/W Power Dissipation in Still Air at C P D mw Moisture Sensitivity MSL Level Flammability Rating Oxygen Index: % % F R UL in ESD Withstand oltage Human Body Model (Note ) Machine Model (Note ) Charged Device Model (Note ) ESD > N/A Latchup Performance Above and Below GND at C (Note ) I Latchup ± ma Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Measured with minimum pad spacing on an FR board, using mm by inch, ounce copper trace with no air flow.. Tested to EIA/JESD A A.. Tested to EIA/JESD A A.. Tested to JESD C A.. Tested to EIA/JESD7. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit Positive DC Supply oltage.. Digital oltage (Select and Inhibit) IN GND. Static or Dynamic oltage Across an Off Switch IO GND Analog oltage (CH, COM) IS GND Operating Temperature Range, All Package Types T A + C Rise or Fall Time (Enable ) cc =. ±. cc =. ±. t r, t f Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DEICE JUNCTION TEMPERATURE ERSUS TIME TO.% BOND FAILURES Junction Temperature C Time, Hours Time, Years,, , 7.9 7,7. 79, 9. 7,. 7,.,9. NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR T J = C T J = C T J = C T J = C T J = 9 C T J = C ns/ TIME, YEARS Figure. Failure Rate versus Time Junction Temperature

3 NLAS DC CHARACTERISTICS Digital Section (oltages Referenced to GND) Parameter Condition Symbol Minimum High Level oltage, Select and Inhibit s IH..... Guaranteed Limit C to C C C Unit Maximum Low Level oltage, Select and Inhibit s Maximum Leakage Current, Select and Inhibit s Maximum Quiescent Supply Current IL IN =. or GND I IN to.... A Select and Inhibit = or GND I CC.... A DC ELECTRICAL CHARACTERISTICS Analog Section Parameter Condition Symbol Maximum ON Resistance (Figures 7 ) IN = IL or IH IS = GND to I IN I. ma R ON.... Guaranteed Limit to C C C 7 Unit ON Resistance Flatness (Figures 7 ) IN = IL or IH I IN I. ma IS =,,. R FLAT (ON). ON Resistance Match Between Channels IN = IL or IH I IN I. ma CH or CH =. R ON (ON). CH or CH Off Leakage Current (Figure 9) COM ON Leakage Current (Figure 9) IN = IL or IH CH or CH =. COM. IN = IL or IH CH. or. with CH floating or CH. or. with CH floating COM =. or. I CH. na I CH I COM(ON). na

4 NLAS AC ELECTRICAL CHARACTERISTICS ( t r = t f =. ns) Turn On Time (Figures and ) INH to Parameter Test Conditions Symbol R L = C L = pf (Figures and ) () t ON.... Guaranteed Max Limit to C C C Min Typ* Max Min Max Min Max 7 9 Unit ns Turn Off Time (Figures and ) INH to R L = C L = pf (Figures and ) t OFF ns Transition Time (Channel Selection Time) (Figure ) Select to R L = C L = pf (Figures and ) t trans ns Minimum Break Before Make Time IS =. (Figure ) R L = C L = pf t BBM.... ns CC =. Maximum Capacitance, Select/INH Analog I/O (switch off) Common I/O (switch off) Feedthrough (switch on) C IN C NO or C NC C COM C (ON) pf *Typical Characteristics are at C. ADDITIONAL APPLICATION CHARACTERISTICS (oltages Referenced to GND Unless Noted) Parameter Maximum On Channel db Bandwidth or Minimum Frequency Response (Figure ) Maximum Feedthrough On Loss Off Channel Isolation (Figure ) Charge Injection Select to Common I/O (Figure ) Total Harmonic Distortion THD + Noise (Figure ) Condition IN = dbm IN centered between and GND (Figure 7) IN = khz to MHz IN centered between and GND (Figure 7) f = khz; IS = RMS IN centered between and GND (Figure 7) IN = to GND, F IS = khz t r = t f = ns R IS =, C L = pf Q = C L * OUT (Figure ) F IS = Hz to khz, RL = Rgen = C L = pf IS =. PP sine wave Symbol Typical C Unit BW. 7.. ONL. db.. ISO. 9 db Q.. pc.. THD.. % MHz

5 NLAS. F DUT OUT pf GND 9% t BMM 9% of OH Switch Select Pin GND Figure. t BBM (Time Break Before Make) DUT % %. F Open OUT pf OH 9% 9% INH OL t ON t OFF Figure. t ON /t OFF DUT % % OUT OH Open pf INH OL t OFF % t ON % Figure. t ON /t OFF

6 NLAS. F GND OUT pf % % 9% Select Pin GND % t trans t trans Figure. t trans (Channel Selection Time) Reference DUT Generator Transmitted Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. ISO, Bandwidth and ONL are independent of the input signal direction. ISO = Off Channel Isolation = Log OUT for IN at khz IN ONL = On Channel Loss = Log OUT for IN at khz to MHz IN Bandwidth (BW) = the frequency db below ONL Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/ ONL DUT Open IN GND C L IN Off On Off OUT Figure. Charge Injection: (Q)

7 NLAS Bandwidth (ON RESPONSE) LEAKAGE (na).. I COM(ON) I COM(OFF) =. (db) Off Isolation =. T A = C. I CH(OFF) TEMPERATURE ( C) 7.. FREQUENCY (MHz) Figure 9. Switch Leakage versus Temperature Figure. Bandwidth and Off Channel Isolation PHASE (Degree) TIME (ns) t trans (ns) =. T A = C t ON /t OFF (ns).. FREQUENCY (MHz) Figure. Phase versus Frequency... (OLTS) Figure. t ON and t OFF versus at C =. INpp =. =. TIME (ns) t trans THD + NOISE (%). INpp =. =. t ON /t OFF Temperature ( C) Figure. t ON and t OFF versus Temp. FREQUENCY (khz) Figure. Total Harmonic Distortion Plus Noise versus Frequency 7

8 NLAS... = Q (pc)... = I CC (na)... =.. COM () Figure. Charge Injection versus COM oltage. =.. Temperature ( C) Figure. I CC versus Temp, = & =. 9 7 =. =. =. C C C C... Figure 7. R ON versus COM and (@ C Figure. R ON versus COM and Temperature,. 7 C C C C C C C C Figure 9. R ON versus COM and Temperature, =. Figure. R ON versus COM and Temperature, =.

9 NLAS C C C C C C C C Figure. R ON versus COM and Temperature, =. Figure. R ON versus COM and Temperature, =. C C C C Figure. R ON versus COM and Temperature, =. 9

10 NLAS PACKAGE DIMENSIONS X Y A B L G P C SEATING PLANE K D T. (.) M T X Y. (.) US US SUFFIX CASE 9 ISSUE D NOTES:. DIMENSIONING AND TOLERANCING PER ANSI J Y.M, 9.. CONTROLLING DIMENSION: MILLIMETERS.. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. MOLD FLASH. PROTRUSION AND GATE BURR SHALL NOT EXCEED.MM (. ) PER SIDE. DETAIL E. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL NOT EXCEED.MM (. ) PER SIDE.. LEAD FINISH IS SOLDER PLATING WITH THICKNESS OF.7.MM (.. ).. ALL TOLERANCE UNLESS OTHERWISE SPECIFIED ±.MM (. ). R MILLIMETERS INCHES S DIM MIN MAX MIN MAX A U B C..9.. D H F.... G. BSC. BSC T N H. REF. REF J....7 R. TYP K.... L.... M N M P.... R...9. S U.... F. BSC. BSC DETAIL E RECOMMENDED SOLDERING FOOTPRINT* X. X... PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box, Denver, Colorado 7 USA Phone: 7 7 or Toll Free USA/Canada Fax: 7 7 or 7 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 79 9 Japan Customer Focus Center Phone: 7 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NLAS/D