1.35V DDR3L-RS SDRAM SODIMM

Transcription

1 1.5V DDRL-RS SDRAM SODIMM MT16MTF51264HZ 4GB MT16MTF1G64HZ 8GB 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Features Features DDRL-RS functionality and operations supported as defined in the component data sheet 204-pin, small outline dual in-line memory module (SODIMM) Fast data transfer rates: PC-12800, PC-10600, PC-8500, or PC GB (512 Meg x 64), 8GB (1 Gig x 64) V DD = 1.5V ( V) V DD = 1.5V ( V) V DDSPD =.0.6V Backward compatible to V DD = 1.5V ±0.075V Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Dual rank Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) On-board I 2 C serial presence-detect (SPD) EEPROM Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command, and address bus Figure 1: 204-Pin SODIMM (MO-268 R/C F) Module height: 0mm (1.181in) Options Marking Operating temperature Commercial (0 C T A +70 C) None Package 240-pin DIMM (halogen-free) Z Frequency/CAS latency CL = 11 (DDR-1600) -1G6 CL = 9 (DDR-1) -1G4 CL = 7 (DDR-1066) -1G1 Table 1: Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5-1G6 PC G4 PC G1 PC G0 PC B PC t RCD (ns) t RP (ns) t RC (ns) mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 1 Products and specifications discussed herein are subject to change by Micron without notice.

2 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Features Table 2: Addressing Parameter 4GB 8GB Refresh count 8K 8K Row address 2K A[14:0] 64K A[15:0] Device bank address 8 BA[2:0] 8 BA[2:0] Device configuration 2Gb (256 Meg x 8) 4Gb (512 Meg x8) Column address 1K A[9:0] 1K A[9:0] Module rank address 2 S#[1:0] 2 S#[1:0] Table : Part s and Timing Parameters 4GB Modules Base device: MT41K256M8, 1 2Gb 1.5V DDRL-RS SDRAM Part 2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT16MTF51264HZ-1G6 4GB 512 Meg x GB/s 1.25ns/1600 MT/s MT16MTF51264HZ-1G6 4GB 512 Meg x GB/s 1.25ns/1600 MT/s MT16MTF51264HZ-1G4 4GB 512 Meg x GB/s 1.5ns/1 MT/s MT16MTF51264HZ-1G1 4GB 512 Meg x GB/s 1.87ns/1066 MT/s Table 4: Part s and Timing Parameters 8GB Modules Base device: MT41K512M8, 1 4Gb 1.5V DDRL-RS SDRAM Part 2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT16MTF1G64HZ-1G6 8GB 1 Gig x GB/s 1.25ns/1600 MT/s MT16MTF1G64HZ-1G4 8GB 1 Gig x GB/s 1.5ns/1 MT/s MT16MTF1G64HZ-1G1 8GB 1 Gig x GB/s 1.87ns/1066 MT/s Notes: 1. The data sheet for the base device can be found on Micron s web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16MTF1G64HZ-1G4E1. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 2

3 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Pin Assignments Pin Assignments Table 5: Pin Assignments 204-Pin DDR SODIMM Front 204-Pin DDR SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 V REF V DD V DD A BA BA RAS# V DD V DD WE# S0# 62 S# 114 S0# DM0 6 DM 115 CAS# S0 64 S 116 ODT V DD 169 S6# V DD 170 DM A1 171 S ODT S1# NC V DD V DD CKE0 125 NC CKE1 126 V REFCA V DD V DD NC NF/A S1# 79 BA DM1 80 A S1 81 V DD RESET# 82 V DD S7# 1 8 A12 15 S4# 187 DM A11 16 DM4 188 S A9 17 S A V DD V DD A A A A V DD SA V DD NF 4 95 A V DDSPD A SDA 45 S2# 97 A SA1 46 DM2 98 A SCL 47 S2 99 V DD V TT V DD 152 S5# 204 V TT CK0 15 DM CK1 154 S CK0# CK1# 156 Note: 1. Pin 78 is NF for 4GB; A15 for 8GB. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN

4 Pin Descriptions Table 6: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I 2 C bus. SCL Input Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I 2 C bus. CBx I/O Check bits: Used for system error detection and correction. x I/O Data input/output: Bidirectional data bus. Sx, Sx# I/O 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Pin Descriptions Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 4

5 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Pin Descriptions Table 6: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sensor/spd EEPROM on the I 2 C bus. TSx, TSx# Err_Out# EVENT# Output Output (open drain) Output (open drain) Redundant data strobe (x8 devices only): TS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TS is enabled, DM is disabled and TS and TS# provide termination resistance; otherwise, TS# are no function. Parity error output: Parity error found on the command and address bus. Temperature event: The EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. V DD Supply Power supply: 1.5V ( V) backward-compatible to 1.5V ( V). The component V DD and V D are connected to the module V DD. V DDSPD Supply Temperature sensor/spd EEPROM power supply:.0.6v. V REFCA Supply Reference voltage: Control, command, and address V DD /2. V REF Supply Reference voltage:, DM V DD /2. Supply Ground. V TT Supply Termination voltage: Used for control, command, and address V DD /2. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 5

6 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Map Map Table 7: -to-module Map (Front) Reference Module Module Pin Reference Module Module Pin U U U U U U U U mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 6

7 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Map Table 8: -to-module Map (Back) Reference Module Module Pin Reference Module Module Pin U U U U U U U U mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 7

8 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# S0# S0 DM0 S4# S4 DM S1# S1 DM1 DM CS# S# U1 DM CS# S# DM CS# S# DM CS# S# U16 S5# S5 DM U9 U S2# S2 DM S# S DM DM CS# S# U7 DM CS# S# U2 DM CS# S# U20 DM CS# S# U S6# S6 DM S7# S7 DM7 DM CS# S# DM CS# S# U12 U17 U5 DM CS# S# DM CS# S# U DM CS# S# U19 DM CS# S# U DM CS# S# DM CS# S# U11 U6 Rank 0 = U1, U2, U7, U9, U11, U12, U17, U19 Rank 1 = U5, U6, U8, U10, U15, U16, U18, U20 BA[2:0] A[15/14:0] RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# BA[2:0]: DDR SDRAM A[15/14:0]: DDR SDRAM RAS#: DDR SDRAM CAS#: DDR SDRAM WE#: DDR SDRAM CKE0: Rank 0 CKE1: Rank 1 ODT0: Rank 0 ODT1: Rank 1 RESET#: DDR SDRAM SCL U14 SPD EEPROM WP A0 A1 A2 SA0 SA1 V DDSPD V DD SDA CK0 CK0# CK1 CK1# SPD EEPROM DDR SDRAM Rank 0 Rank 1 CKE[1:0], A[15/14:0], RAS#, CAS#, WE#, S#[1:0], ODT[1:0], BA[2:0] CK[1:0] CK#[1:0] Command, address and clock line terminations DDR SDRAM DDR SDRAM V TT V DD V TT V REFCA V REF DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM Note: 1. The ball on each DDR component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component s ODT and output driver. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 8

9 General Description DDR SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR SDRAM devices. DDR SDRAM modules use DDR architecture to achieve high-speed operation. DDR architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR modules use two sets of differential signals: S, S# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Temperature-Compensated Self Refresh 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM General Description The DDR SDRAM on this module provides low-current self refresh via temperaturecompensated self refresh (TCSR) and substantially reduces self refresh current (I DD6 ) values. TCSR takes affect when component case temperature (T C ) is less than 45 C and auto self refresh (ASR) is enabled. ASR is required to utilize the TCSR function. A detailed description of TCSR is available in the 1.5V DDRL-RS SDRAM data sheet. Fly-By Topology DDR modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR. Serial Presence-Detect EEPROM Operation DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I 2 C bus using the DIMM s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect." mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 9

10 Electrical Specifications Table 9: Absolute Maximum Ratings 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD V DD supply voltage relative to V V IN, V OUT Voltage on any pin relative to V Table 10: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage V V 1 I VTT Termination reference current from V TT ma V TT I I I OZ I VREF T A T C Termination reference voltage (DC) command/address bus Input leakage current; Any input 0V V IN V DD ; V REF input 0V V IN 0.95V (All other pins not under test = 0V) Output leakage current; 0V V OUT V DD ; and ODT are disabled; ODT is HIGH V REF supply leakage current; V REF = V DD /2 or V REFCA = V DD /2 (All other pins not under test = 0V) Module ambient operating temperature DDR SDRAM component case operating temperature Address inputs, RAS#, CAS#, WE#, BA S#, CKE, ODT, CK, CK# 0.49 V DD - 20mV 0.5 V DD 0.51 V DD + 20mV V µa DM 4 0 4, S, S# µa µa Commercial 0 70 C, 4 Commercial 0 95 C, 4, 5 Notes: 1. Module is backward-compatible with 1.5V operation. Refer to device specification for details and operation guidance. 2. V TT termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins.. T A and T C are simultaneous requirements. 4. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron s web site. 5. The refresh rate is required to double when 85 C < T C 95 C. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 10

11 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. specifications are available on Micron s web site. Module speed grades correlate with component speed grades, as shown below. Table 11: Module and Speed Grades DDR components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Speed Grade -2G G G G4-15E -1G1-187E -1G C -25E -80B -25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 11

12 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM I DD Specifications I DD Specifications Table 12: DDR I DD Specifications and Conditions 4GB (Die Revision M) Values are for the MT41K256M8 SDRAM only and are computed from values specified in the 1.5V 2Gb DDRL-RS (256 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE 1 I DD ma Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE 1 I DD ma Precharge power-down current: Slow exit 2 I DD2P ma Precharge power-down current: Fast exit 2 I DD2P ma Precharge quiet standby current 2 I DD2Q ma Precharge standby current 2 I DD2N ma Precharge standby ODT current 1 I DD2NT ma Active power-down current 2 I DDP ma Active standby current 2 I DDN ma Burst read operating current 1 I DD4R ma Burst write operating current 1 I DD4W ma Burst refresh current 1 I DD ma Self refresh temperature current 2 I DD ma Self refresh temperature current 2 I DD ma Self refresh temperature current 2 I DD ma Self refresh temperature current 2 I DD ma Self refresh temperature current Extended Temperature 2 I DD6ET ma Self refresh temperature current Extended Temperature 2 I DD6ET ma All banks interleaved read current 1 I DD ma Reset current 2 I DD ma Notes: 1. One module rank in the active I DD ; the other rank in I DD2P0 (slow exit). 2. All ranks in this I DD condition.. T C = +80 C; SRT and ASR disabled (MAX) 4. T C T A ; SRT disabled, ASR enabled () 5. T C +45 C; SRT disabled, ASR enabled () 6. T C = +80 C; SRT disabled, ASR enabled () C < T C +80 C; SRT disabled, ASR enabled (MAX) 8. T C = +95 C; SRT disabled, ASR enabled () C < T C +95 C; SRT disabled, ASR enabled (MAX) mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 12

13 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM I DD Specifications Table 1: DDR I DD Specifications and Conditions 8GB (Die Revisions E) Values are for the MT41K512M8 DDRL SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8) component data sheet Parameter Symbol Units Operating current 0: One bank ACTIVATE-to-PRECHARGE 1 I DD ma Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE 1 I DD ma Precharge power-down current: Slow exit 2 I DD2P ma Precharge power-down current: Fast exit 2 I DD2P ma Precharge quiet standby current 2 I DD2Q ma Precharge standby current 2 I DD2N ma Precharge standby ODT current 1 I DD2NT ma Active power-down current 2 I DDP ma Active standby current 2 I DDN ma Burst read operating current 1 I DD4R ma Burst write operating current 1 I DD4W ma Burst refresh current 1 I DD ma Self refresh temperature current 1 I DD ma Self refresh temperature current 1 I DD ma Self refresh temperature current 1 I DD ma Self refresh temperature current 2 I DD ma Self refresh temperature current Extended Temperature 2 I DD6ET ma Self refresh temperature current Extended Temperature 2 I DD6ET ma All banks interleaved read current 1 I DD ma Reset current 2 I DD ma Notes: 1. One module rank in the active I DD ; the other rank in I DD2P0 (slow exit). 2. All ranks in this I DD condition.. T C = +80 C; SRT and ASR disabled (MAX) 4. T C T A ; SRT disabled, ASR enabled () 5. T C +45 C; SRT disabled, ASR enabled () 6. T C = +80 C; SRT disabled, ASR enabled () C < T C +80 C; SRT disabled, ASR enabled (MAX) 8. T C = +95 C; SRT disabled, ASR enabled () C < T C +95 C; SRT disabled, ASR enabled (MAX) mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 1

14 Serial Presence-Detect EEPROM For the latest SPD data, refer to Micron's SPD page: Table 14: Serial Presence-Detect EEPROM DC Operating Conditions 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Serial Presence-Detect EEPROM All voltages referenced to V DDSPD Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD.0.6 V Input low voltage: Logic 0; All inputs V IL 0.45 V DDSPD x 0. V Input high voltage: Logic 1; All inputs V IH V DDSPD x 0.7 V DDSPD V Output low voltage: I OUT = ma V OL 0.4 V Input leakage current: V IN = GND to V DD I LI µa Output leakage current: V OUT = GND to V DD I LO µa Table 15: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes Clock frequency t SCL khz Clock pulse width HIGH time t HIGH 0.6 µs Clock pulse width LOW time t LOW 1. µs SDA rise time t R 00 µs 1 SDA fall time t F ns 1 Data-in setup time t SU:DAT 100 ns Data-in hold time t HD:DI 0 µs Data-out hold time t HD:DAT ns Data out access time from SCL LOW t AA:DAT µs 2 Start condition setup time t SU:STA 0.6 µs Start condition hold time t HD:STA 0.6 µs Stop condition setup time t SU:STO 0.6 µs Time the bus must be free before a new transition can start t BUF 1. µs WRITE time t W 10 ms Notes: 1. Guaranteed by design and characterization, not necessarily tested. 2. To avoid spurious start and stop conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA.. For a restart condition, or following a WRITE cycle. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 14

15 4GB, 8GB (x64, DR) 204-Pin DDRL-RS SODIMM Module Dimensions Module Dimensions Figure : 204-Pin DDR SODIMM Front view (2.667) (2.656).8 (0.150) MAX 2.0 (0.079) R (2X) U1 U2 U5 U6 1.8 (0.071) (2X) U7 U8 U9 U (0.787) 0.15 (1.187) (1.175) 6.0 (0.26) 2.0 (0.079) 45 4X Pin (0.09) 6.6 (2.504) 0.45 (0.018) Back view 0.6 (0.024) Pin (0.04) 0.90 (0.05) U11 U12 U14 U15 U16 U17 U18 U19 U (0.10) 4.0 (0.157) Pin (0.12) Pin (1.55) 21.0 (0.827) 24.8 (0.976) Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical () where noted. 2. The dimensional diagram is for reference only S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. mtf16c512_1gx64hz.pdf - Rev. D 5/1 EN 15