Design for Power User Experience. David Hui AMD Fellow

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1 Design for Power User Experience David Hui AMD Fellow

2 Power optimization is holistic Architecture ASIC Technology CAD Physical Design IP 2

3 Design for power challenges Low power architectures Advance and efficient power management architecture Performance and power scalable architectures enable efficient cross product IPs System-level power profiling and optimization Power aware design flow Design closure flow in all three phases (Architecture, Design, and Implementation) of the product development cycle Power, performance, and area Hierarchical low power SOC design Predictable power metrics to allow power closure Power efficient silicon process and technologies Low power interconnect reduce capacitance Leakage power reduction technologies IPs and monitor technology enable aggressive DVFS Accurate and low overhead on die voltage and temperature sensors Power efficient clock distribution Low thermo resistance packaging Power efficient ASIC IPs Silicon characterization Performance and power balance process technologies STA analysis which correlates better to silicon 3

4 DFP Strategies Power prediction and budgeting Spreadsheet RTL power optimization Sequence PowerTheatre Analysis and optimization techniques using relative power Designer update RTL Synthesis with fine grain clock gate option Leakage power reduction Power island with CPF adaptation Mix VT 4

5 CPF adaptation Power Forward Initiative proof point project with GPU Collaboration with Cadence Develop front to back flow and insert CPF wherever possible to replace internal flow Wireless use CPF for simulation Both GPU and wireless chips use Conformal LP 5

6 CPF Challenges and expectations Many years invested in current P&R flow Mixed tool flow Can t rely on entire tool chain to be power intent aware Power gating solution must be area efficient Depending on product, minimal performance impact, power efficient rather than low power No impact to physical design schedule Critical product low risk implementation Our strategy was to rely extensively on Conformal LP to validate the correctness of the power gating solution How to prove correctness? 6

7 Key power island technology choices Need a single power specification for chip Common Power Format (CPF) Easily understood by everyone impacted by power Automatic checking of design against spec Simulation of power functionality in frontend (logical) Checking at every major stage of design flow Conformal Low Power + CPF + Netlist In addition to normal LVS and Logical Equiv Check PD place & fix all special power cells in block floorplan phase Then allow normal tool flow to run & complete IR and in-rush current analysis 7

8 CPF flow Single CPF is constructed for the entire chip Concise description of power strategy Which blocks are ONOFF, which are AON Isolation rules and the cells to implement them Power switch type (either header or footer) and switched power definition For complex GPU the CPF is about 200 lines Easily understood & reviewed Much simpler than timing constraint/exception files Push down block CPF using FE 8

9 Common CPF commands used in a single design define_isolation_cell define_always_on_cell define_power_switch_cell define_library create_isolation_rule update_isolation_rules create_power_mode create_global_connection create_power_nets create_nominal_condition update_nominal_condition create_power_domain Update_power_domain create_power_switch_rule update_power_switch_rule 9

10 Checkerboard power switches (highlighted) with taps and AON cells 10

11 CPF power island experience (1 of 2) CPF file Full chip CPF is about 200 lines and relatively easy to create. Ideally created should be created by frontend engineers but PD engineers needed involve because knowledge of PD libraries, PDonly cells and Encounter-only directives Block CPF push down using Encounter work relatively well, but the block CPF size is about 10K lines and a lot of name mapping. Some easy of use/readability lost Physical netlist also alter original chip CPF Use Conformal LP as golden CPF parser Need to be careful with global and internal (after PG) signals Need a way to check power sequencing and time reference for control signals Our strategy was to rely extensively on Conformal LP to validate the correctness of the power gating solution Since GPU use 3 rd party simulator, power gate can not be simulated. Power on sequence rules and signal polarity can not be checked 11

12 CPF power island experience (2 of 2) Placement of power island special cells and power switches needs a lot of internal scripting and optimization step can potentially break timing. Tools have issue with mix AON logic in power gated islands Tools have some problem with footer power switches Hard to access real area impact Difficult to do ECO Critical to run rule check at every step when netlist is changed and major flow stages (placement, CTS, IPO, etc) We did tapeout on schedule and silicon in working as intent 12

13 CLP Flows Block level flow Used extensively throughout APR flow Fast (45minutes), good diagnostics 1 False error due to top level clock pushdown/incomplete library spec Chip block flow Implemented but not used Full chip flow 24+hrs in full flat mode, 4hrs with specially created power ILMs Need additional directives to handle IO power Eg non-standard power rails 13

14 Future power challenges Process variation continue to increase in deep submicron Mode base IR drop analysis Need optimization techniques to reduce gate leakage HVT cells are not as effective (performance impact VS leakage reduction) Voltage scale limited More complex power island requirement 14

15 A wish list Power closure A consistent power analysis from ESL -> RTL -> PD -> silicon Power models PVT aware Sigma base for yield prediction Power mode aware IP Need statistical methods for stimulus generation Clock control aware Spatial and temporal CPF Translator between CPF/UPF A CPF linter A bi-directional GUI An API interface with other tools More consistent tool interpretation of CPF Better integration of tools that uses CPF Ability to code in technology rules, i.e. Level shifter requirement based on voltage domain voltage differential, special rules for switch type, or etc. Support bottom up CPF Heretical CPF methodology 15