NDF11N50Z, NDP11N50Z. N-Channel Power MOSFET. Low ON Resistance Low Gate Charge 100% Avalanche Tested These Devices are Pb Free and are RoHS Compliant

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1 N-Channel Power MOSFET V,.2 Features Low ON Resistance Low Gate Charge % Avalanche Tested These Devices are Pb Free and are RoHS Compliant ABSOLUTE MAXIMUM RATINGS (T C = 2 C unless otherwise noted) Rating Symbol NDFNZ NDPNZ Unit Drain to Source Voltage V DSS V Continuous Drain Current, I D. (Note R JC 2). A Continuous Drain Current I D 6.7 (Note 2) 6.7 A T A = C, R JC Pulsed Drain Current, V V Power Dissipation, R JC (Note ) I DM 42 (Note 2) 42 A P D 36 4 W Gate to Source Voltage V GS ±3 V Single Pulse Avalanche Energy, I D =. A ESD (HBM) (JESD22 A4) E AS 9 mj V esd 4 V V DSS R DS(ON) 4. A V.2 Ω TO 22FP CASE 22D STYLE G () N Channel D (2) MARKING DIAGRAM S (3) RMS Isolation Voltage (t =.3 sec., R.H. 3%, T A = 2 C) (Figure 4) V ISO 4 V Peak Diode Recovery dv/dt 4. (Note 3) V/ns Continuous Source Current (Body Diode) Maximum Temperature for Soldering Leads Operating Junction and Storage Temperature Range I S. A T L 26 C T J, T stg to C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Surface mounted on FR4 board using sq. pad size, (Cu area =.27 in sq [2 oz] including traces). 2. Limited by maximum junction temperature 3. I d. A, di/dt 2 A/ s, V DD BV DSS, T J C. TO 22 CASE 22A STYLE A Y WW G Gate NDFNZG or NDPNZG AYWW Drain = Location Code = Year = Work Week = Pb Free Package Source ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2 July, 2 Rev. Publication Order Number: NDFNZ/D

2 THERMAL RESISTANCE Parameter Symbol NDFNZ NDPNZ Unit Junction to Case (Drain) R JC C/W Junction to Ambient Steady State (Note 4) R JA ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Characteristic Test Conditions Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V GS = V, I D = ma BV DSS V Breakdown Voltage Temperature Coefficient Drain to Source Leakage Current Reference to 2 C, I D = ma V DS = V, V GS = V BV DSS /.6 V/ C T J 2 C I DSS A 2 C Gate to Source Forward Leakage V GS = ±2 V I GSS ± A ON CHARACTERISTICS (Note ) Static Drain to Source On Resistance V GS = V, I D = 4. A R DS(on).48.2 Gate Threshold Voltage V DS = V GS, I D = A V GS(th) V Forward Transconductance V DS = V, I D = 4. A g FS 7.7 S DYNAMIC CHARACTERISTICS Input Capacitance C iss 37 pf Output Capacitance V DS = 2 V, V GS = V, f =. MHz C oss 66 Reverse Transfer Capacitance C rss 4 Total Gate Charge Q g 46 nc Gate to Source Charge V DD = 2 V, I D =. A, Q gs 8.7 Gate to Drain ( Miller ) Charge V GS = V Q gd 2 Plateau Voltage V GP 6.2 V Gate Resistance R g.4 RESISTIVE SWITCHING CHARACTERISTICS Turn On Delay Time t d(on) ns Rise Time V DD = 2 V, I D =. A, t r 32 Turn Off Delay Time V GS = V, R G = Ω t d(off) 4 Fall Time t f 23 SOURCE DRAIN DIODE CHARACTERISTICS (T C = 2 C unless otherwise noted) Diode Forward Voltage I S =. A, V GS = V V SD.6 V Reverse Recovery Time V GS = V, V DD = 3 V t rr 3 ns Reverse Recovery Charge I S =. A, di/dt = A/ s Q rr 2. C 4. Insertion mounted. Pulse Width 38 s, Duty Cycle 2%. 2

3 TYPICAL CHARACTERISTICS 2 V GS = V 2 7. V 6. V 6. V. V. V 2 2 Figure. On Region Characteristics 2 V DS = 2 V 2 T J = C T J = C V GS, GATE TO SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I D = 4. A V GS, GATE TO SOURCE VOLTAGE (V) Figure 3. On Region versus Gate to Source Voltage R DS(on), DRAIN TO SOURCE RESISTANCE ( ) V GS = V Figure 4. On Resistance versus Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) I D = 4. A V GS = V T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature BV DSS, NORMALIZED BREAKDOWN VOLTAGE (V) I D = ma T J, JUNCTION TEMPERATURE ( C) Figure 6. BV DSS Variation with Temperature 3

4 TYPICAL CHARACTERISTICS I DSS, LEAKAGE ( A) T J = C Figure 7. Drain to Source Leakage Current versus Voltage C, CAPACITANCE (pf) C rss C oss C iss V GS = V f = MHz.. Figure 8. Capacitance Variation V GS, GATE TO SOURCE VOLTAGE (V) Q GS V DS Q T Q GD V GS V DS = 2 V I D =. A Q g, TOTAL GATE CHARGE (nc) Figure 9. Gate to Source Voltage and Drain to Source Voltage versus Total Charge t, TIME (ns) V DD = 2 V I D =. A V GS = V t d(off) t r t f t d(on) I S, SOURCE CURRENT (A) 2 T J = C 2 C 2 C C R G, GATE RESISTANCE ( ) Figure. Resistive Switching Time Variation versus Gate Resistance V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage versus Current 4

5 TYPICAL CHARACTERISTICS. V GS 3 V SINGLE PULSE T C = 2 C dc ms ms R DS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT s s.. Figure 2. Maximum Rated Forward Biased Safe Operating Area NDFNZ DUTY CYCLE =. R(t) (C/W) R JC = 3.4 C/W SINGLE PULSE Steady State. E 6 E E 4 E 3 E 2 E E+ E+ E+2 E+3 PULSE TIME (s) Figure 3. Thermal Impedance (Junction to Case) for NDFNZ LEADS HEATSINK. MIN Figure 4. Isolation Test Diagram Measurement made between leads and heatsink with all leads shorted together. *For additional mounting information, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

6 ORDERING INFORMATION Order Number Package Shipping NDFNZG NDPNZG TO 22FP (Pb Free) TO 22AB (Pb Free) Units / Rail Units / Rail (In Development) 6

7 PACKAGE DIMENSIONS TO 22FP CASE 22D 3 ISSUE K H Q Z L V G F Q A H K B N B 2 3 D A K G N L D 3 PL Y U.2 (.) M B M Y F T U S R J C T SEATING PLANE S J R TO 22 CASE 22A 9 ISSUE AF C T SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: INCH 3. 22D- THRU 22D-2 OBSOLETE, NEW STANDARD 22D-3. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G. BSC 2.4 BSC H J K L N.2 BSC.8 BSC Q R S U STYLE : PIN. GATE 2. DRAIN 3. SOURCE NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G H J K L N Q R S T U V Z STYLE : PIN. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/ Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NDFNZ/D