FEATURES DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO. LTC1040 Dual Micropower Comparator

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1 LTC0 Dual Micropower Comparator FEATRES Micropower.µW ( Sample/Second) Power Supply Flexibility Single Supply.V to V Split Supply ±.V to ±V Guaranteed Max Offset 0.7mV Guaranteed Max Tracking Error Between Input Pairs ± 0.% Input Common Mode Range to Both Supply Rails TTL/CMOS Compatible with ±V or Single V Supply Input Errors are Stable with Time and Temperature APPLICATIO S Battery-Powered Systems Remote Sensing Window Comparator BANG-BANG Controllers DESCRIPTIO The LTC 0 is a monolithic CMOS dual comparator manufactured using Linear Technology s enhanced LTCMOS TM silicon gate process. Extremely low operating power levels are achieved by internally switching the comparator ON for short periods of time. The CMOS output logic holds the output information continuously while not consuming any power. In addition to switching power ON, a switched output is provided to drive external loads during the comparator s active time. This allows not only low comparator power, but low total system power. Sampling is controlled by an external strobe input or an internal oscillator. The oscillator frequency is set by an external RC network. Each comparator has a unique input structure, giving two differential inputs. The output of the comparator will be high if the algebraic sum of the inputs is positive and low if the algebraic sum of the inputs is negative., LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO Window Comparator with Symmetric Window Limits Typical LTC0 Supply Current vs Sampling Frequency LTC0 00 V S = ±V V C COMP A COMP B A OT = WHEN > V C A B = WHEN V C V C B OT = WHEN < V C SPPLY CRRENT, I S (µa) 0 R EXT = M EXTERNALLY STROBED 0,000,000 SAMPLING FREQENCY, f S (Hz) LTC0 TA0 LTC0 TA0 0fa

2 LTC0 ABSOLTE AXI RATI GS (Note ) W W W Total Supply Voltage (V to V )... V lnput Voltage... (V 0.3V) to (V 0.3V) Operating Temperature Range LTC0C... 0 C T A C LTC0M (OBSOLETE)... C to C Storage Temperature Range... C to 0 C Lead Temperature (Soldering, sec) C Output Short-Circuit Duration...Continuous W PACKAGE/ORDER I FOR ATIO STROBE ON/OFF A B A OT A A A A GND 3 7 TOP VIEW 7 3 V V P-P OSC B OT B B B B V ORDER PART NMBER LTC0CN LTC0CSW N PACKAGE -LEAD PDIP SW PACKAGE -LEAD PLASTIC SO WIDE T JMAX = C, θ JA = 0 C/W (N) T JMAX = C, θ JA = C/W (SW) J PACKAGE -LEAD CERDIP T JMAX = 0 C, θ JA = 0 C/W OBSOLETE PACKAGE Consider the N Package as an Alternate Source LTC0MJ LTC0CJ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. Test conditions: V = V, V = V, unless otherwise noted. LTC0M/LTC0C SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V OS Offset Voltage (Note ) Split Supplies ±.V to ±V ±0.3 ± 0.7 mv Single Supply (V = GND).V to V Split Supplies ±V to ±V ± ±. mv Single Supply (V = GND) V to V Tracking Error Between Split Supplies ±.V to ±V % Input Pairs (Notes and 3) Single Supplies (V = GND). to V I BIAS Input Bias Current OSC = GND ±0.3 na R IN Average Input Resistance f S = khz (Note ) 0 30 MΩ CMR Common Mode Range V V V PSR Power Supply Range Split Supplies ±. ± V Single Supplies (V = GND). V I S(ON) Power Supply ON Current (Note ) V = V, V P-P On. 3 ma I S(OFF) Power Supply OFF Current (Note ) V = V, V P-P Off LTC0C µa LTC0M 0.00 µa t D Response Time (Note ) µs A, B, A B and ON/OFF Outputs (Note 7) V OH Logic Output Voltage V =.7V, l OT = 30µA.. V V OL Logic 0 Output Voltage V =.7V, l OT =.ma V 0fa

3 LTC0 ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range otherwise specifications are at T A = C. Test conditions: V = V, V = V, unless otherwise specified LTC0M/LTC0C SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS STROBE Input (Note 7) V IH Logic Input Voltage V =.V.0. V V IL Logic 0 Input Voltage V =.7V.0 0. V R EXT External Timing Resistor Resistor Tied Between V and OSC Pin 0,000 kω f S Sampling Frequency R EXT = M, C EXT = 0.µF Hz Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : Applies over input voltage range limit and includes gain uncertainty. Note 3: Tracking error = ( )/. Note : R IN is guaranteed by design and is not tested. R IN = /(f S 33pF). Note : Average supply current = t D l S(ON) f S ( t D x f S ) l S(OFF). Note : Response time is set by an internal oscillator and is independent of overdrive voltage. Note 7: Inputs and outputs also capable of meeting EIA/JEDEC B series CMOS specifications. TYPICAL PERFOR A CE CHARACTERISTICS W I S(ON) (ma) 0 0 Peak Supply Current vs Supply Voltage C C C SPPLY VOLTAGE, V (V) NORMALIZED SAMPLING FREQENCY (fs/fs AT V, C) Normalized Sampling Frequency vs Supply Voltage and Temperature T A = C T A = C R = M C = 0.µF T A = C SPPLY VOLTAGE, V (V) SAMPLE RATE, fs (Hz) k Sampling Rate vs R EXT, C EXT C EXT = 0.µF C EXT = µf C EXT = 0.0µF M R EXT (Ω) C EXT = 00pF C EXT = 0.0µF M LTC0 TPC0 LTC0 TPC0 LT0 TPC03 RESPONSE TIME, td (µs) Response Time vs Supply Voltage 0 T A = C SPPLY VOLTAGE, V (V) AVERAGE INPT RESISTANCE, R IN (/f S 33pF) (Ω) 7 Input Resistance vs Sampling Frequency 3 SAMPLING FREQENCY, f S (Hz) TYPICAL OTPT VOLTAGE DROP, V V P-P (V) V P-P Output Voltage vs Load Current V =.V V = V V = V V = V 3 7 LOAD CRRENT, I L (ma) LTL0 TPC0 LTC0 TPC0 LTC0 TPC0 0fa 3

4 LTC0 TYPICAL PERFOR A CE CHARACTERISTICS RESPONSE TIME, t D (µs) Response Time vs Temperature V = V W Self-Oscillating LTC0 7 Quick Hookup Guide V EXTERNAL V STROBE INPT 7 R EXT C EXT External Strobe LTC AMBIENT TEMPERATRE, T A ( C) LTC0 TPC07 LTC0 TPC0 TEST CIRCIT V () GND () OTPT V () ALL INPTS ON OPPOSITE COMPARATOR AT GROND LTC0 TA0 BLOCK DIAGRA W A A A A 7 COMP A V A OT ON/OFF B B 3 B B STROBE OSC TIMING GENERATOR COMP B SWITCH TIMING POWER ON V V P-P CIRCIT 3 7 A B B OT V P-P 0µs GND V LTC0 BD0 0fa

5 LTC0 APPLICATIO S I FOR ATIO W The LTC0 uses sampled data techniques to achieve its unique characteristics. Some of the experience acquired using classic linear comparators does not apply to this circuit, so a brief description of internal operation is essential to proper application. The most obvious difference between the LTC0 and other comparators is the dual differential input structure. Functionally, when the sum of inputs is positive, the comparator output is high and when the sum of the inputs is negative, the output is low. This unique input structure is achieved with CMOS switches and a precision capacitor array. Because of the switching nature of the inputs, the concept of input current and input impedance needs to be examined. The equivalent input circuit is shown in Figure. Here, the input is being driven by a resistive source, R S, with a bypass capacitor, C S. The bypass capacitor may or may not be needed, depending on the size of the source resistance and the magnitude of the input voltage,. R S C S S S V C IN 33pF LTC0 DIFFERENTIAL INPT Figure. Equivalent Input Circuit LTC0 AI0 For R S < Ok Assuming C S is zero, the input capacitor, C IN, charges to with a time constant of R S C IN. When R S is too large, C IN does not have a chance to fully charge during the sampling interval ( 0µs) and errors will result. If R S exceeds kω, a bypass capacitor is necessary to minimize errors. For R S > OkΩ For R S greater than kω, C IN cannot fully charge and a bypass capacitor, C S, is needed. When switch S closes, charge is shared between C S and C IN. The change in voltage on C S because of this charge sharing is: C IN V = C IN C S This represents an error and can be made arbitrarily small by increasing C S. With the addition of C S, a second error term caused by the finite input resistance of the LTC0 must be considered. Switches S and S alternately open and close, charging and discharging C IN between and ground. The alternate charge and discharge of C IN causes a current to flow into the positive input and out of the negative input. The magnitude of this current is: I IN = q f S = C IN f S where f S is the sampling frequency. Because the input current is directly proportional to input voltage, the LTC0 can be said to have an average input resistance of: R IN = I IN = f S C IN = f S 33pF (see typical curve of Input Resistance vs Sampling Frequency). A voltage divider is set up between R S and R IN causing error. The input voltage error caused by these two effects is: V ERROR = Example: f S = Hz, R S = MΩ, C S = µf, = V V ERROR = V C ( IN R S ) C IN C S R S R IN ( 33 ) 3 = 33µV 330µV = 33µV. Notice that most of the error is caused by R IN. If the sampling frequency is reduced to Hz, the voltage error is reduced to µv. 0fa

6 LTC0 APPLICATIO S I FOR ATIO Minimizing Comparison Errors The two differential input voltages, V and V, are converted to charge by the input capacitors C IN and C IN (see Figure ). The charge is summed at the virtual ground point; if the net charge is positive, the comparator output is high and if negative, it is low. There is an optimum way to connect these inputs, in a specific application, to minimize error. V V S W S LTC0 AI0 Ignoring internal offset, the LTC0 will be at its switching point when: V C IN V C IN = 0. Optimum error will be achieved when the differential voltages, V and V, are individually minimized. Figure 3 shows two ways to connect the LTC0 to compare an input voltage,, to a reference voltage, V REF. sing the above equation, each method will be at null when: (a) (V REF 0V) C IN (0V ) C IN = 0 or = V REF (C IN /C IN ) (b) (V REF ) C IN (0V 0V) C IN = 0 or = V REF. Notice that in method (a) the null point depends on the ratio of C IN /C IN, but method (b) is independent of this ratio. Also, because method (b) has zero differential input voltage, the errors due to finite input resistance are negligible. The LTC0 has a high accuracy capacitor array and even the non-optimum connection will only result in ± 0.% more error, worst-case compared to the optimum connection. C IN C IN VIRTAL GROND LTC0 DAL DIFFERENTIAL INPT Figure. Dual Differential Equivalent Input Circuit Tracking Error Tracking error is caused by the ratio error between C IN and C IN and is expressed as a percentage. For example, consider Figure 3a with V REF = V. Then at null, = V REF C IN C IN = V ± mv because C IN is guaranteed to equal C IN to within 0.%. V REF V REF Figure 3. Two Ways to Do It Common Mode Range The input switches of the LTC0 are capable of switching to either the V or V supply. This means that the input common mode range includes both supply rails. Many applications, not feasible with conventional comparators, are possible with the LTC0. In the load current detector shown in Figure, a 0.Ω resistor is used to sense the current in the V supply. This application requires the dual differential input and common mode capabilities of the LTC0. V S (a) OK I L 0.Ω 0mV / LTC0 (b) Optimum OT Figure. Load Current Detector LTC0 AI0 R L OT = HI IF I L > A OT = LO IF I L < A LTC0 TA03 0fa

7 LTC0 APPLICATIO S I FOR ATIO Offset Voltage Error W The errors due to offset, common mode, power supply variation, gain and temperature are all included in the offset voltage specification. This makes it easy to compute the error when using the LTC0. Example: error computation for Figure. Assume:.V V S V. Then total worst-case error is: A I L (ERROR) = ± (0mV mV) = ±ma 0mV Tracking Error V OS ma I L (ERROR) % = 0 = ± 0.%. A Note: If source resistance exceeds k, bypass capacitors should be used and the associated errors must be included. Pulsed Power (V P-P ) Output It is often desirable to use comparators with resistive networks such as bridges. Because of the extremely low power consumption of the LTC0, the power consumed by these resistive networks can far exceed that of the device itself. At low sample rates the LTC0 spends most of its time off. To take advantage of this, a pulsed power (V P-P ) output is provided. V P-P is switched to V when the comparator is on and to a high impedance (open circuit) when the comparator is off. The ON time is nominally 0µs. Figure shows the V P-P output circuit. V The V P-P output voltage is not precise (see V P-P Output Voltage versus Load Current curve). There are two ways V P-P can be used to power external networks without excessive errors: () ratiometric networks and () fast settling references. In a ratiometric network, the inputs are all proportional to V P-P (see Figure ). Consequently, for small changes, the absolute value of V P-P does not affect accuracy. It is critical that the inputs to the LTC0 completely settle within µs of the start of the comparison cycle and that they do not change during the 0µs ON time. When driving resistive networks with V P-P, capacitive loading on V TRIP Figure. Ratiometric Network Driven by V P-P the network should be minimized to meet the µs settling time requirement. It is not recommended that V P-P be used to drive networks with source impedances, as seen by the inputs, of greater than kω. In applications where an absolute reference is required, the V P-P output can be used to drive a fast settling reference. The LT0.V reference, ideal in this application, settles in approximately µs (see Figure 7). The current through R must be large enough to supply the LT0 minimum bias current ( ma) and the load current, I L. V P-P OTPT / LTC0 LTC0 AI0 V P-P OTPT OTPT 0µs COMPARATOR ON TIME Q P 7 GND V P-P R R I L LT0 R3 / LTC0 Figure. V P-P Output Switch LTC0 AI0 LTC0 AI07 Figure 7. Driving Reference with V P-P Output 0fa 7

8 LTC0 APPLICATIO S I FOR ATIO W Output Logic In addition to the normal outputs (A OT and B OT ), two additional outputs, A B and ON/0FF, are provided (see Figure and Table ). All logic is powered from V and ground, thus input and output logic levels are independent of the V supply. The LTC0 is directly compatible with CMOS logic and is TTL compatible for.7v V.V. No external pull-up resistors are required. Table. Output Logic Truth Table ΣA INPTS ΣB INPTS A OT B OT A B ON/OFF H H L L H L L L L H L H L L H I* *I = indeterminate. When both A and B outputs are low, the ON/OFF output remains in the state it was in prior to entering A OT = B OT = L. sing External Strobe A positive pulse on the strobe input, with the 0SC input tied to ground, will initiate a comparison cycle. The STROBE input is edge-sensitive and pulse widths of 0ns will typically trigger the device. Because of the sampling nature of the LTC0, some sensitivity exists between the offset voltage and the falling edge of the input strobe. When the falling edge of the strobe signal falls within the comparator s active time (0µs after rising edge), offset changes of as much as mv can occur. To eliminate this problem, make sure the strobe pulse width is greater than the response time, t D. sing Internal Strobe An internal oscillator allows the LTC0 to strobe itself. The frequency of oscillation, and hence sampling rate, is set by an external RC network (see typical curve of Sampling Rate vs R EXT, C EXT ). For self-oscillation, the STROBE pin must be tied to ground. The external RC network is connected as shown in Figure. To assure oscillation, R EXT must be between 0k and M. There is no limit to the size of C EXT. R EXT is very important in determining the power consumption. The average voltage at the oscillator pin is approximately V /. The power consumed by R EXT is then: P REXT = (V /) /R EXT. ON/OFF 7 V R EXT COMPARATOR A OTPT D C Q A OT LTC0 C EXT COMPARATOR B OTPT D 3 A B STROBE C Q B OT Figure. External RC Connection LTC0 AI0 0µs Figure. LTC0 Logic Diagram LTC0 AI0 Example: R EXT = M, V V, P REXT = (.) / =. W. This is about four times the power consumed by the LTC0 at V = V and f S = sample/second. Where power is a premium R EXT should be made as large as possible. Note that the power consumed by R EXT is not a function of f S or C EXT. 0fa

9 LTC0 TYPICAL APPLICATIO S Complete Heating/Cooling Automatic Thermostat V AT 0.µA 7.3k.k k* 0M 7 COMP A LTC0 k TEMP ADJST.k k* 3 COMP B 3 M HEAT COOL THERMISTOR # 007 YELLOW SPRINGS INSTRMENT CO., INC. 0.µF * k HYSTERESIS = V = 0mV 0M SEPARATION (0mV) 0M LTC0 TA03 TEMPERATRE C SEPARATION 7 C HEAT AIRCONDITIONING ON HYSTERESIS AIRCONDITIONING OFF HEATER OFF HYSTERESIS HEATER ON COOL TIME LTC0 TA0 Window Comparator with Independent Window Limits and Fully Floating Differential Input Hysteresis Comparator with Fully Floating Differential Input V V COMP A LTC0 A OT = WHEN > V V TRIP R k * / LTC0 OT V L COMP B AB = WHEN V V L B OT = WHEN < V L R.MΩ V OT = 0 WHEN > V = TRIP R (V) R = 0. V TRIP 0mV R R V OT = WHEN < V = TRIP R = 0.V TRIP R R LTC0 TA0 * TO CENTER HYSTERESIS ABOT V TRIP, FORCE THIS INPT TO HYSTERESIS/ (mv) LTC0 TA0 0fa

10 LTC0 TYPICAL APPLICATIO S The LTC0 as a Linear Amplifier With a simple RC filter, the LTC0 can be made to function as a linear amplifier. By filtering the logic output and feeding it back to the negative input, the loop forces the output duty cycle [t ON /(t ON t OFF )] so that V OT equals (Figure ). The RC time constant is set to keep the ripple on the output small. The maximum output ripple is: V = V /f S RC and should be set to 0.mV to mv for best results. Notice that the higher the sampling frequency, f S, the lower RC can be. This is important because the RC filter also sets the loop response. A convenient way to keep f S as high as possible under all conditions is to connect a 0k resistor to pin (OSC) with no capacitance to ground. V / LTC0 R V V OT 0V C t ON t t OFF V OT = V ON t ON t OFF LTC0 TA0 LTC0 TA07 Figure. The LTC0 as a Linear Amplifier -Wire 0 C to 0 C Temperature Transducer with ma to 0mA Output V V TO 0V 0 C = ma 0 C = 0mA LM3 R V 3 N 30Ω LT k k ZERO ADJST 7 0k / LTC0 M µf N7 0Ω YELLOW SPRINGS INSTRMENT PART NO. 0 µf k FLL-SCALE ADJST Ω RETRN ACCRACY = ±0. C ±0. C = ±0.3 C CIRCIT ERROR TRANSDCER AT C ERROR LTC0 TA0 0fa

11 LTC0 PACKAGE DESCRIPTIO J Package -Lead CERDIP (Narrow.300 Inch, Hermetic) (Reference LTC DWG # 0-0-).0.0 (.3.0) FLL LEAD OPTION CORNER LEADS OPTION ( PLCS).03.0 (0..3) HALF LEAD OPTION.00 (0.7) MIN.0 (0.3) RAD TYP 7.0 (.3) MAX ( ).300 BSC (7. BSC).00 (.00) MAX.0.00 (0.30.0).00.0 ( ) 0 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS. (3.7) MIN.0.0 (.3.).0.0 ( ) OBSOLETE PACKAGE.0 (.) BSC J 00 N Package -Lead PDIP (Narrow.300 Inch) (Reference LTC DWG # 0-0-).00* (.0) MAX 7 3. ±.0* (.77 ± 0.3) (7.0.).30 ±.00 (3.30 ± 0.7) (.3.).00.0 ( ) ( ).00 (0.0) MIN.0 (3.0) MIN.00 (0.7) MIN NOTE: INCHES. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.0 INCH (0.mm).0 (.) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights..0 (.) TYP.0 ±.003 (0.7 ± 0.07) N 0 0fa

12 LTC0 TYPICAL APPLICATIO S Analog Multiplier/Divider V Single V Voltage-to-Frequency Converter V REF (V) V V V 7 A 0k / LTC0 V C 3 V B * LTC3 3 k µf V OT 7 / LTC0 µf 0k / 7C00 / 7C00 f OT f IN 7 k µf V f OT (AVERAGE) = f IN IN ±0.% FS V REF LTC0 TA V OT = (V A V V) V C V B ACCRACY = ±mv NO TRIM *V B MST BE > V A (V V) LTC0 TA PACKAGE DESCRIPTIO SW Package -Lead Plastic Small Outline (Wide.300 Inch) (Reference LTC DWG # 0-0-0).030 ±.00 TYP N.00 BSC.0 ± (.3.70) NOTE 3.0 MIN.3 ±.00 N NOTE 3.3. (.007.3) 3 N/ N/ RECOMMENDED SOLDER PAD LAYOT.00 (0.7) RAD MIN.. (7.3 7.) NOTE.0.0 ( ) 0 TYP.03. (.3.) (0.0.3) (.70) ( ) NOTE 3 BSC (0.3 0.) (0.0.70) NOTE: TYP INCHES. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE 3. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.00" (0.mm) Linear Technology Corporation 30 McCarthy Blvd., Milpitas, CA (0) 3-00 FAX: (0) ( ) S (WIDE) 00 0fa LW/TP 0 K REV A PRINTED IN SA LINEAR TECHNOLOGY CORPORATION