CeraLink Capacitors. The revolution for fast switching inverters

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1 CeraLink Capacitors The revolution for fast switching inverters EPCOS AG Piezo and Protection Devices Business Group Munich, Germany September, 2016

2 CeraLink : Device Portfolio Nominal capacitance / rated voltage Designed for 650V semiconductors Designed for 900V semiconductors Designed for 1300V semiconductors Low Profile series LP (L leads) ESL = 2.5 nh 1µF / 500V 0.5µF / 700V 0.25µF / 900V Low profile series LP (J leads) ESL = 2.5 nh 1µF / 500V 0,5µF / 700V 0.25µF / 900V Solder Pin series SP ESL = 3.5 nh 20µF / 500V 10µF / 700V 5µF / 900V All products shown share the same ceramic material. Different voltage performance is adjusted by internal layer thickness. CC 2/15 2

3 CeraLink The next generation of capacitor technologies Key benefits High capacitance density Supports further miniaturization of power electronics on the system level Low ESL Supports fast-switching semiconductors and high switching frequencies Low losses at high frequencies and high temperatures Low ESR High current rating High operating temperature (150 C) MLSC Design, no metalization cap Low Volume High Frequency High Temperature High Reliability CC 2/15 3

4 Where to use CeraLink? DC-link capacitor or Snubber capacitor For Industry and for Automotive CC 2/15 4

5 A new approach to ceramic power capacitors Patented product solution for high DC voltage applications in power electronics based on multilayer components with Anti-ferroelectric ceramics Modified Pb La (Zr, Ti) O 3 Copper inner electrodes High-temperature stable ceramicmetal interconnects based on sintered silver to realize capacitance values up to 100 µf Dielectric constant 25 C, 1 khz, 1 V RMS Electric field [V/µm] V R >400 V LP-L LP-J SP CC 2/15 5

6 Highest current ratings CeraLink technology offers key benefits regarding the power losses in a capacitor: Low profile with short thermal path (h) High thermal conductivity (λλ ttt ) High permissible temperature increase ( TT) Low ESR PP llllllll = PP ttt 2 II CC,RRRRRR EEEEEE = 2 λλ ttt TT h 2 VV II CC,RRRRRR = 1 h 2 λλ ttt TT VV EEEEEE permissible current [Arms] Device under test: CeraLink LP 1 µf, 500 V Increase by 25% Measurement performed at +85 C ambient temperature heatsink Heatsink and and forced air air flow no heatsink and no forced air flow Frequency [khz] For CeraLink capacitors, the maximum temperature increase (ΔT) is only limited by the device temperature. For typical BTO MLCC ceramic capacitors, self-heating (ΔT) is limited to 20 K. Typical permissible current of 1 µf BTO MLCC: 1 2 A RMS. Permissible current [Arms] No heatsink and no forced air flow CC 2/15 6

7 Insulation properties at high temperatures CeraLink class Class C C rated rated MLCC MLCC film Film capacitor aluminum Aluminum capacitor capacitor Comparison between capacitors of nominal capacitance values and voltage ratings matching to the CeraLink capacitors series. tau [OhmF] τ [ΩF] Temperature temperature [ C] For CeraLink capacitors the discharging time constant ττ = RR iiiiii CC(TT) remains at high values even at high temperatures. For CeraLink capacitors, the loss of insulation resistance at high temperatures is much lower than with other capacitors. A low time constant results in a high leakage current which heats up the device additionally. The risk of irreversible damage or even thermal runaway increases with falling time constant. Therefore CeraLink capacitors are an optimal solution for high temperature applications. For CeraLink high current ratings and a high self-heating due to applied current are permissible. CC 2/15 7

8 Overcurrent robustness of parallel capacitors 2 CeraLink capacitors connected in parallel were tested at twice the specified ripple current. One capacitor was cooled, the other was uncooled A RMS (@100 khz, 105 C ambient temperature) per 1 µf, 500 V capacitor. Cooled side Uncooled side Capacitance [%] Temperature [ C] device temperature Device temperature [ C] [ C] C1 CeraLink large signal Ceralink small signal 150 Cooled capacitor Time time [min] The capacitance characteristic of CeraLink capacitors avoids thermal runaway Higher temperature leads to Lower capacitance Higher impedance Lowest current through the hottest capacitor I 1 Z 1 Uncooled capacitor I 2 Z 2 I tot I 3 Z 3 Z 4 I n = I tot Z / Z n 1/Z = Σ n (1/Z n ) I 4 CC 2/15 8

9 Improved robustness feature Multilayer serial capacitor design Arbitrary failure Serial connection of two MLCC geometries TWO failures must occur in the same layer of the chip to produce a short circuit Single localized failures do not immediately cause a short circuit of the device, because the breakdown voltage is >2 times higher than the operating voltage Crack Additionally, the lead frames of CeraLink capacitors minimize the mechanical stress to the chip and avoid cracks from occuring in the ceramics at all CC 2/15 9

10 Benefits of the new technology on a system level Device characteristics lead to a low inductive commutation loop Low self inductance (ESL) 2.5 to 4 nh High capacitance density 2 to 5.5 µf/cm³ High thermal robustness allows CeraLink capacitors to be placed very close to the semiconductor: operation up to +150 C permissible <<ESL <<L σ System enabled benefits lead to a miniaturization Lower voltage overshoot during semiconductor switching Faster switching with higher di/dt and dv/dt values decrease the switching losses Higher switching frequencies are achievable Low losses and high thermal robustness of the DC link capacitor allows reduction of cooling Less ringing at the DC link improves EMI Semiconductor Switching Voltage in V Semicon switching voltage [V] Principle Semiconductor Overshoot Principle semiconductor overshoot Time [ns] CeraLink Semicon Semicon collector Collector Current current in A [A] CC 2/15 10

11 New demands on DC link capacitors Today the package of a motor inverter is mainly driven by the size of the capacitor, the busbars, the terminal box and the filter components. Plikat, Mertens, Koch, Volkswagen AG, Corporate Research, 2013 CeraLink capacitors represent a major advance in technology Reduction of DC link capacitor size. Low-profile design (<10 mm) available. Support of distributed DC link capacitor topologies with low inductance components. High cooling efficiency due to high thermal conductivity. Support of different connection techniques SMD, welding, silver sintering, Through-hole technology, press fit technology, Screwing. CC 2/15 11

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