THE MULTI-DATAFLOW COMPOSER TOOL: A RUNTIME RECONFIGURABLE HDL PLATFORM COMPOSER
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1 Conference on Design and Architectures for Signal and Image Processing Electronic Chips & Systems design Initiative November 2nd-4th, 2011, Tampere, Finland THE MULTI-DATAFLOW COMPOSER TOOL: A RUNTIME RECONFIGURABLE HDL PLATFORM COMPOSER Francesca Palumbo, Nicola Carta and Luigi Raffo EOLAB - Microelectronics Lab DIEE - Dept. of Electrical and Electronic Eng. University of Cagliari - ITALY
2 Outline Introduction: Problem formulation Background Goals
3 Outline Introduction: Problem formulation Background Goals The Multi-Dataflow Composer tool
4 Outline Introduction: Problem formulation Background Goals The Multi-Dataflow Composer tool Performance assessment Use-case scenario Results
5 Outline Introduction: Problem formulation Background Goals The Multi-Dataflow Composer tool Performance assessment Use-case scenario Results Future research directions and conclusions RVC extension Applicable research hot topics Final remarks
6 Outline Introduction: Problem formulation, Background Goals The Multi-Dataflow Composer tool Performance assessment Use-case scenario Results Future research directions and conclusions RVC extension Applicable research hot topics Final remarks
![Scenario and Problem Statement Systems and applications on the market are becoming every day more complex. We will be called to face the the disappearing computer phenomenon [Streit2005] [i.e. implicit interfaces, users could be un aware].](/docs-images/58/42321132/images/7-0.png "APPLICATION TRENDS ICT TRENDS Ubiquitous access Personalized services Delocalized computing and storage Massive data processing systems High-quality virtual reality Intelligent sensing")
7 Scenario and Problem Statement Systems and applications on the market are becoming every day more complex. We will be called to face the the disappearing computer phenomenon [Streit2005] [i.e. implicit interfaces, users could be un aware]. APPLICATION TRENDS ICT TRENDS Ubiquitous access Personalized services Delocalized computing and storage Massive data processing systems High-quality virtual reality Intelligent sensing High-performance real-time embedded computing EXAMPLES Domestic robot Telepresence The car of the future Aerospace and avionics Human ++ Computational science Realistic games Smart camera networks SOURCE:
8 Scenario and Problem Statement Systems and applications on the market are becoming every day more complex. We will be called to face the the disappearing computer phenomenon [Streit2005] [i.e. implicit interfaces, users could be un aware]. APPLICATION TRENDS INTEGRATION, SPECIALIZATION and HIGH PERFORMANCE REQUIREMENTS in such COMPLEX COMPUTATIONAL HUNGRY ENVIRONMENTS threaten TRADITIONAL DESIGN FLOW. SOURCE:
9 Flexibility STEP1: Reconfigurable Paradigm Systems are required to be flexible and efficient. Reconfigurable Paradigm (RP) to hw design: specialized computing platforms, capable of changing configuration to serve the targeted computations. GPP DSP RP ASIC Performance
10 Flexibility STEP1: Reconfigurable Paradigm Systems are required to be flexible and efficient. Reconfigurable Paradigm (RP) to hw design: specialized computing platforms, capable of changing configuration to serve the targeted computations. GPP DSP RP FINE- GRAINED Bit-level COARSE- GRAINED Word-level Flexibility ASIC Reconf. Speed Performance Config. Storage
11 Flexibility STEP1: Reconfigurable Paradigm Systems are required to be flexible and efficient. Reconfigurable Paradigm (RP) to hw design: specialized computing platforms, capable of changing configuration to serve the targeted computations. GPP DSP RP FINE- GRAINED Bit-level COARSE- GRAINED Word-level Flexibility ASIC Reconf. Speed Performance Config. Storage HW-SW GAP: The more the hw is specialized the more is difficult to program it.
12 STEP 2: RVC Standard The MPEG group has addressed the problem of defining an efficient formalism for codecs specification: the Reconfigurable Video Coding (RVC) framework is part of the MPEG standard since may Decoder Description (FNL+BSDL) Decoder Composition Mechanism VTL (RVC-CAL FUs) Selection of FUs and Parameter Assignment Abstract Decoder Model (FNL+RVC-CAL) Exploiting the Dataflow Model of Computation (D-MoC), specifications are provided in the form of dataflow programs: networks of Functional Units (FUs) belonging to a standard Video Tool Library (VTL).
13 Goals and Research Evolution RVC modularity can be coupled with a coarse-grained RP map on a unique hw substrate multiple D-MoC models.
14 Goals and Research Evolution RVC modularity can be coupled with a coarse-grained RP map on a unique hw substrate multiple D-MoC models. High-level dataflow combination tool, front-end of the actual MDC tool. [DASIP 2010]
15 Goals and Research Evolution RVC modularity can be coupled with a coarse-grained RP map on a unique hw substrate multiple D-MoC models. High-level dataflow combination tool, front-end of the actual MDC tool. [DASIP 2010] Multi-Dataflow Composer (MDC) tool: concrete definition of the hardware template and of the D-MoC based mapping strategy. [DASIP 2011]
16 Goals and Research Evolution RVC modularity can be coupled with a coarse-grained RP map on a unique hw substrate multiple D-MoC models. High-level dataflow combination tool, front-end of the actual MDC tool. [DASIP 2010] Multi-Dataflow Composer (MDC) tool: concrete definition of the hardware template and of the D-MoC based mapping strategy. [DASIP 2011] Integration of the full high-level to hw composition and generation framework.
17 Outline Introduction: Problem formulation, Background Goals The Multi-Dataflow Composer tool Performance assessment Use-case scenario Results Future research directions and conclusions RVC extension Applicable research hot topics Final remarks
18 D-MoC and Coarse-Grained RP D-MoC-based Formalism HW Platform 1:1 [SOURCE:
19 D-MoC and Coarse-Grained RP D-MoC-based Formalism HW Platform 1:1 [SOURCE: D-MoC-based Formalism Coarse Grained Reconfigurable HW Platform 2:1
20 F. Palumbo et.al., RVC: A multi-decoder CAL composer tool, in Proc. DASIP 2010] Parallel and Serial MPEG-4 SP
21 Parallel and Serial MPEG-4 SP COMPLEX, ERROR PRONE AND TIME CONSUMING: PLATFORM COMPOSITION RECONFIGURATION MANAGEMENT F. Palumbo et.al., RVC: A multi-decoder CAL composer tool, in Proc. DASIP 2010]
22 Multi-Dataflow Composer Tool The Multi-Dataflow Composer (MDC) tool IS an automatic platform constructor, composing different Functional Units (FUs) on a coarse-grained reconfigurable template. The MDC IS responsible of providing runtime programmability of the hw substrate to switch among given the dataflows. The MDC IS NOT capable of High Level Synthesis from dataflow to hw.
23 MDC: Generalities The MDC tool, recognizing the similarities among different D-MoCs descriptions, automatically composes a unique reconfigurable multi-dataflow system: exploiting heterogeneous blocks, the FUs in the input networks described according D-MoC formalism, with homogeneous interfaces; integrating the minimum FUs set to correctly accomplish the provided dataflows. Reconfiguration is ensured by a couple of switching element, named switching box (Sbox): inserted by the MDC tool at the crossroads among different dataflows to merge/separate the path of the processed data. logically kept simple to provide high-speed reconfiguration (one clock cycle is sufficient).
24 (*) [F. Palumbo et.al., RVC: A multi-decoder CAL composer tool, in Proc. DASIP 2010] MDC: Front-End The MDC front-end: Elaborates the input D-MoC inputs to create atomic actors (only) networks; Translates the flattened networks into C++ Directed Acyclic Graphs (DAGs); Compares the DAGs and merges them into a unique C++ DAG; With respect to (*), it stores the information for the runtime reconfiguration, producing the configuration tables (CTs) of the Sbox IPs. (*)
25 MDC: Back-End The MDC back-end is responsible of assembling the HDL Verilog coarse-grained reconfigurable hw, corresponding to the multi-dataflow C++ DAG produced by the MDC front-end. Having originally N different networks in input, N-1 LUTs are inserted in the final hw substrate, one for each CT created by the MDC front-end. CONFIGURATION MANAGER
26 Outline Introduction: Problem formulation, Background Goals The Multi-Dataflow Composer tool Performance assessment Use-case scenario Results Future research directions and conclusions RVC extension Applicable research hot topics Final remarks
27 Assessment: Design Under Test
28 Assessment: Design Under Test
29 Assessment: Design Under Test
30 Assessment: Design Under Test
31 Assessment: Design Under Test
32 Assessment: Performance Results [UC1: Anti-Aliasing application, UC2: Zoom application, UC3: Anti-Aliasing and Zoom applications together]
33 Assessment: Performance Results [UC1: Anti-Aliasing application, UC2: Zoom application, UC3: Anti-Aliasing and Zoom applications together] Overhead
34 Assessment: Performance Results [UC1: Anti-Aliasing application, UC2: Zoom application, UC3: Anti-Aliasing and Zoom applications together] CMOS 90 nm technology, Synopsys Design Compiler
35 Assessment: Performance Results [UC1: Anti-Aliasing application, UC2: Zoom application, UC3: Anti-Aliasing and Zoom applications together] CMOS 90 nm technology, Synopsys Design Compiler The more are the provided inputs, the more could be the actors overlap and thus the area saving.
36 Outline Introduction: Problem formulation, Background Goals The Multi-Dataflow Composer tool Performance assessment Use-case scenario Results Future research directions and conclusions RVC extension Applicable research hot topics Final remarks
37 EOLAB/INSA Cooperation: RVC Extension The MDC tool is a N:1 platform builder. Orcc-VHDL is a 1:1 high level hardware compiler. Therefore, they can be integrated to compose a complete multi-purpose systems generation and composition framework. In the RVC domain, this integration will allow the creation of multi-standard codec platforms.
38 Power Management and Profiler Power Management: trough the Sbox we foresee the possibility of switching off large portion of the substrate belonging to currently unused dataflows. Complexity Management: the MDC tool could be coupled with a high level profiler to allow moving additional steps toward the hw-sw gap closure. Such a profiler operating at the graph level, combining lower level back-annotated information and higher level functional information, will be able for example to provide important directives for reconfiguration.
39 Final Remarks The Multi-Dataflow Composer tool is intended to close the gap between complex multi-purpose heterogeneous hw platforms and their sw programming: Leveraging on the combination of the Dataflow Model of Computation and the coarse-grained reconfigurable paradigm, it builds runtime reconfigurable multi-purpose systems, starting from the high level dataflow descriptions of the applications. Benefits: Automatic derivation of complex hw platforms, with a very small users intervention. Possibility of addressing any multi-purpose system, if described according to the RVC formalism. Runtime reconfigurability is provided without neither hw shut-down nor suspension. Concrete on-chip area saving.
40 Acknowledgements The research leading to these results has received funding from: the European Community's Seventh Framework Programme (FP7/ ) under grant agreement no , MADNESS Project the Region of Sardinia, Young Researchers Grant, PO Sardegna FSE , L.R.7/2007 Promotion of the scientific research and technological innovation in Sardinia under grant agreement CRP RPCT Project
41 Conference on Design and Architectures for Signal and Image Processing Electronic Chips & Systems design Initiative November 2nd-4th, 2011, Tampere, Finland THE MULTI-DATAFLOW COMPOSER TOOL: A RUNTIME RECONFIGURABLE HDL PLATFORM COMPOSER Francesca Palumbo, Ph.D. francesca.palumbo@diee.unica.it EOLAB - Microelectronics Lab Dept. of Electrical and Electronics Eng. University of Cagliari (ITALY)
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