To start off, let s take a look at how the RL78 s memory is organized. The RL78 comes equipped with 512kb of Flash, all of which can be addressed

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3 To start off, let s take a look at how the RL78 s memory is organized. The RL78 comes equipped with 512kb of Flash, all of which can be addressed linearly. This memory can expanded up to 960Kb. The full range is actually 1 Mb, however the upper 64K page is used by RAM, special function registers, as well as the dataflash. The data flash can be up to 8Kb in size and is able to be accessed by a dual operation. This Dual operation allows you to overwrite the data flash in parallel, which means that the data flash can be written to while the CPU executes instructions from flash memory. RL78 devices are offered with up to 30Kb of RAM, with the upper page supporting a theoretical maximum 64Kb. The entire RAM area is protected with parity bits and a RAM shield function is available, which means specific areas of the RAM can be secured against rewriting or read out. FLASH memory is segmented in blocks of 1K, which means that a 1K block is the minimum size that can be erased. The smallest write unit is just 32 bits. These 32 bits are secured by an additional ECC byte. There is also a general purpose register area, located in RAM, that can be directly accessed by the CPU. 3

4 The RL78 Code Flash Area contains two 4kb boot clusters; boot cluster zero, as well as an independent boot cluster; boot cluster one. This configuration allows for easy implementation of the self-programming functions using the included boot loader, which provides 3.8k of space per cluster for user code. Using the boot-swap feature, a new boot function including new interrupt vector tables, reset vectors and option byte settings, can be written to boot cluster one which can then be selected using the boot-swap command. Each boot cluster contains a vector table that accommodates up to 64 entries. The first entry, address zero, contains the reset vectors. This is followed by the interrupt vectors for each interrupt slot. When creating an interrupt, care must be taken as the 16bit addresses in this this range must be located in the lower 64kb page. Also included in each boot cluster are option bytes which can be used to control many of the RL78s features. These include control over the On-chip Oscillator frequency selectable as either 24 or 32Mhz - watchdog timer settings, low voltage settings and the debug interface. When controlling the debug interface, for example, the option bytes determine if the debug interface is opened or closed. If it is open, an additional 10byte ID can be stored within the option byte area. 4

5 Above the two boot clusters is where the normal program area starts. The second boot cluster can also be used as program memory if only one boot cluster is utilized. The program memory itself ranges in size from 16kb up to 512K on RL78 G13 devices. Above the normal program area are the SFR and RAM memory areas. As shown in the illustration, there are actually two SFR areas. In the past, only one was necessary; this first SFR area allows up to 256 special function registers. However due to the complexity of the newer devices, with more timer and security functions, the 2nd SFR area, which is 2kb in size, was inserted into the RAM area range. The RAM memory area itself is up to 30K including the CPU registers. The CPU registers that are not used by the application can also be used as standard RAM memory. Below the RAM area is the mirror area, which will be discussed in more detail later in this presentation. And finally we have the data flash area which can be up to 8k in size. 5

6 Now to the processor registers of the RL78 CPU core. The first one is the Program Status Word, which is an 8bit register with various flags. These flags are the carry flag, the Auxillary carry, and the zero flag. These three flags are directly accessed by the instruction set. For example, if an overflow is generated, the carry flag is set; or if the result of an operation is zero the zero flag is set. However you don t have to worry about these flags when coding in C, since they are handled automatically by the compiler when it generates the assembly language. The interrupt service priority flags ISP0 and ISP1 are also located inside the program status word and up to four different interrupt priority levels can be realized with these two flags. In addition to these interrupt service priority flags, are the register bank select flags RBS0 and RBS1. These flags can be accessed directly and are used to select RAM register banks. Perhaps the most important flag is the IE global interrupt enable flag, which is located in position 7 of the program status word. This flag can be accessed directly by an intrinsic function from the compiler which is referred to as disable or enable interrupt. Using this flag, the global interrupt service is enabled or disabled. 6

7 The next register is the Program Counter Register. The program counter is a 20bit wide register which holds the address information of the next instruction to be executed. The program counter is automatically incremented according to the number of bytes that have been fetched. It is automatically stored on the stack area in case of a call instruction or, for example, in the event that an interrupt service will be executed. It is restored by the return or the return-from-interrupt function. The reset signal causes the program counter to load the address which is located in the reset vector table, at addresses 0x00 and 0x01. 7

8 The next register is the stack pointer. The stack pointer is a 16bit wide register which holds the start address of the stack area which is part of the internal RAM area. The stack pointer is always decremented prior to a write to save to the stack memory, and is incremented after read to restore from the stack memory. This means, for example, with a PUSH instruction the register pair can be stored onto the stack. The register pair is typically 16bits wide, and so uses two addresses i.e. the stack pointer value will be decremented by two. With the POP instruction the data is restored from the stack, which means the data is popped from the stack into the register and the stack pointer is incremented by two. Additionally, the CALLT or CALL instructions and an interrupt or break instruction use the stack area for storing program counter information on the stack. Due to the fact that the stack access is only 16 bits wide, the 20 bit program counter information must be stored on the stack in 4 bytes. The stack area is also used by the compiler for storing local variables. This can be done with the PUSH and POP instructions or by direct addressing. For applications requiring less memory, for example 64kb, you can reduce the stack size by selecting the near memory model. In this case the program counter will be reduced to a 16bit wide access, which means the program counter information can be stored with just two bytes on the stack area. For each CALL instruction this saves two bytes of stack. 8

9 Here we can see the general purpose registers found on the RL78. The general purpose registers are mapped into the normal RAM area and consist of four register banks; each with 8x 8bit or 4x 16bit registers. The 8 bit registers are the X, A, C, B, E, D, L and H registers and the 16 bit registers are the AX, BC, DE or HL registers. The four register banks are assigned as banks 0 through 3. Switching of the register banks can be accomplished via software or by an interrupt service routine. This allows for very fast interrupt handling. For example, if the main processing is using interrupt bank 0 and if an interrupt occurs, it is automatically switched to the bank 1. In this case all the registers do not have to be saved on the stack and the interrupt service routine can be processed much more quickly. In this case, no push or pop instructions are needed. 9

10 The next register is the CS register, which is rather unique. First a little background; in general the program area of the RL78 devices can be addressed in a linear way. However, the device itself is a 16bit device which means the register set is 16bits wide. Conventionally, If register direct addressing is used by its instruction set, for example a BRANCH AX or a CALL AX instruction, the AX register can only hold 16bits of the final address. However, this leaves out the additional four bits needed to address the whole 20bit addressable range. This is where the CS register comes into play. The CS register holds the upper 4 bits of the 20bit address where the lower 16bits of the final address are held in the register itself. The CS allows branching to addresses higher than 0xFFFF. This is done automatically by the C compiler so no additional actions are necessary if the application code is written in C language. To bypass the CS addressing you can also select the small memory model. With this option, the CS register is always set to zero but the maximum addressable range is just 64Kb of code. 10

11 Similar to the CS register, which is used for addressing code flash, the ES register is used for register indirect addressing of data that has a more than 16bits wide address. For example, when using a data move instruction with a 20 bit address, the HL register, in this case, holds the lower 16bits of the 20bit address and the ES register holds the upper 4 bits. This is automatically done by the compiler so if a NEAR pointer is used - which is the typical way to address the upper 64K of RAM - the ES register is set to 0xF automatically and 16bit addressing is sufficient. Additionally you can use the ES register to access code flash memory when, for example, generating a CRC routine. In this case a FAR pointer must be used to set up the ES register where again, the upper 4bits of the 20bit address will be stored. 11

12 Normally constants which are allocated in the code flash memory must be addressed by FAR addressing which requires use of the ES register. One drawback to this method is that it slows down code execution. To overcome this issue the RL78 uses a mirror area which duplicates the special code flash memory area into the upper 64K page and allows fast 16bit RAM access to constants that are located in the code flash memory. The size of the mirror area depends on the RAM size. For example, in a device equipped with 1.8k of RAM, the maximum mirror area size is 58.25k. Generally speaking, the larger the RAM size, the smaller mirror area. 12

13 The mirror area itself can be selected by the PMC register. This register selects the flash memory space where the mirror area is stored. The PMC must only be set once during the initial settings, prior to the DMA controller. This can be done directly in the compiler environment by selecting either mirror area 0 or mirror area 1. 13

14 Now for a quick overview of the RL78 CPU core itself. It s a 16 bit CPU core with a three stage pipeline. Thanks to this architecture, the RL78 offers up to MHz, as measured by the IAR C compiler version4.61a. Furthermore this CPU core supports a wide operating voltage range. Speeds of 32MHz can be supported given a supply voltage of 2.7 to 5.0V. 16MHz operation is supported down to 2.4V, and an 8MHz operation speed is supported down to 1.8V. Below 1.8V, down to 1.6V the RL78 spports an operating speed of 4MHz. All these different speed modes and voltage ranges are supported, which means there are no special device grades or versions required, allowing the RL78 to be implemented in a wide variety of applications. The RL78 also features a DMA engine with up to 4 channels DMA, or direct memory access. That enables the movement of data from peripherals to the RAM area and vice versa. 14

15 The RL78 core also features a very efficient instruction set where 86% of the instructions are done in one or two cycles. More specifically, 56% are done within one cycle, 30% in two cycles, 9% in 3 cycles, which leaves only 5% of the overall instruction set executed in four cycles or more. In addition to these very efficient instruction sets, there are some hardware assist functions implemented in the core. First, there is a 16bit Barrel Shifter which is able to shift or rotate a 16 bit word by 1 to 15 bytes, all within one clock cycle. Second, the RL78 features a multiply unit that supports signed and unsigned multiplication. Using this feature, a 16x16bit multiplication with a 32bit result can be done within just one cycle. And finally a multiply and accumulate, or MAC is provided that can be used for signed and unsigned values. The RL78 s MAC feature can perform complex algorithms such as 16x16bit multiplications plus 32bits with a 32 bit result in only two clock cycles. 15

16 As mentioned earlier, the RL78 features a three stage pipeline. These stages are Instruction Fetch, or IF; Instruction Decode, or ID; and Memory Access, or MEM. This 3-stage pipeline enables the RL78 to execute most instructions in just one clock cycle. The actual time required to execute an instruction is dependent upon the main system clock. For example, if the device is running at 20MHz operation speed, one cycle is equal to 50 nano-seconds. This means that typical instructions, like set 1 p1.0, which is an access to a special function register for setting the port bit, are executed in only 50 nano-seconds. 16

17 The RL78 user s manual provides a table showing the number of clock cycles required for each instruction. This table can be found in the Instruction Set chapter. As stated earlier, most instructions can be carried out within one cycle due to the RL78 s 3 stage pipeline. However it should be noted that there are some instances where this is not the case. For example, when accessing RAM constants and flash memory, the pipeline must be stopped at the MEM stage because the same bus is used for accessing the data and fetching the next instruction. This is also true when fetching instructions from RAM while executing code form RAM. In this case, the instruction fetch and execution must both be done via the RAM buss. This increases the execution time because reading from RAM takes more time, which requires the CPU to wait until the data is sent to the instruction queue. 17

18 The Multiplier is a hardware module which is used like a peripheral for the core. There are different operation modes. The first one is multiplication for signed or unsigned values. This is 16x16bit multiplication with a 32 bit result. The multiplication result is available after one CPU clock, but before this multiplication can be done the two multiplicands must be written to the multiplication registers and after the multiplication, the result must be read back from the 32 bit result register after one CPU clock. An 8x8 bit multiplier is included in the CPU instruction set which can be executed in one CPU clock directly. As stated earlier, The RL78 also supports 16x16bit multiplication plus 32 bit addition MAC functions for signed or unsigned values. For this calculation the multiplier uses two CPU clock cycles. Divide functions are also supported for 32bit by 32 bit division with a 32 bit result and a 32 bit remainder. The division result itself is available after 16 CPU clocks. 18

19 Here you can see the block diagram for the multiplication division unit. The black arrows represent the flow during division mode and the light grey arrows show the flow during multiplication and multiplication/accumulation mode. The complete multiplier divider can be controlled using the multiply division con troll register or MDUC. With this register you can set up the mode - for example if you want to divide or multiply the data. You can also start or stop division operation with this register. If the division or multiplication is finished, an interrupt (INTMD) will be generated. 19

20 Due to the fact that this multiplier is implemented as a hardware peripheral on the G12 and G13 devices, normally a software library is used to do the multiplication. However this can be easily changed in the setup of the IAR embedded workbench by checking the use hardware multiplier/divider unit box in the library configuration located under general options. Using this option, instead of the software library, significantly increases the speed of the multiplication time. An example of this is shown on the following slide. 20

21 By using the functionality shown in this is hardware map, you can see how the calculation time of a mass calculation can be significantly sped up. This shows an example for a PI calculation implementing the hardware multiplication unit. This type of calculation can be completed within 12 clock cycles which is very fast compared to other MCUs. 21

22 Now we ll have a look at the functionality of the DMA or Direct Memory Access Controller. Direct memory access allows for automatic transfers between peripherals supporting the DMA and the internal RAM or vice versa without CPU intervention. In the RL78 products there can be up to 4 DMA channels that support transfers of either 8 or 16 bits. The maximum transfer unit can be up to 1024 times, which allows for easy batch transfers using, for example, the serial interface. The transfer time itself is two cycles, which means that if a DMA transfer is done from the special function register into the RAM area, the CPU core will be stopped for two cycles as the data bus is used to transfer the data. The transfer mode is a single transfer mode which means that, once triggered, for example by an interrupt from the A/D converter, one 8 or a 16bit transfer unit can be transferred from the SFR to RAM or vice versa. DMA transfer requests are selectable and can be initiated by several peripherals. The first is the serial interface which includes CSI00, CSI21, UART0 to UART2 or IIC00 to IIC21; timer channels 0, 1, 4 or 5; and the A/D converter. Given this, the DMA controller can be used, for example, for successive transfers from a serial interface if the user or an application needs to transfer a complete set of data like 16 8-bit units - into RAM. Using the UART in combination with the DMA allows this transfer to occur without CPU intervention. Furthermore, just two clocks cycles are used when the data is reloaded to the UART register. 22

23 Another example would be to use the DMA is to get the data from the A/D conversion result register. In this case the A/D converter triggers the DMA and the DMA itself copies the data from the A/D converter result register into the RAM area. 22

24 Now to the RL78 s interrupt functions. All the RL78 products support a very fast service interrupts which are controlled by various flags within separate three registers. The first is the Interrupt Mask flag register, or MK, which is enabling or disabling each interrupt. The second is the Interrupt Request Flag Register, or IF. Flags within this register will be set automatically if an interrupt occurs; for example if a timer overflows or a new A/D converter value is available. These flags can be set or cleared by software, for example for polling; or they can initiate an interrupt service routine directly. The third register is the Interrupt Priority, or PR register. With this register, each interrupt source can be assigned a specific priority. There are four priority levels from 0 to 3. These registers provide each interrupt source with its own set of flags. For example, for timer channel 0 there is one mask flag, one request flag and one priority flag. Each interrupt source is capable of initiating a standby release from halt mode or stop mode. The minimum service time to get into an interrupt service routine is 9 clock cycles and the maximum time is 14 clock cycles. 23

25 Here we can see the basic block diagrams for the different interrupt circuits. The first is the Internal Mask-able Interrupt. Here you will find the IF flag which is triggered either by software or by the interrupt itself. With this, the MK flag is used to enable or disable each interrupt. These are combined by an end gate that controls the flow to the priority controller. If the global interrupt enable, or flag IE flag is set, the priority controller starts working and the interrupt vector table address generator executes the interrupt service routine. The second example shows an External Mask-able Interrupt. This is very similar to the Internal Mask-able interrupt, however here you will find an edge detector which provides two additional flags; the EGP and EGN Flags. These flags are used to specify whether the external interrupt should occur; ie. on the rising or falling edge. The third example shows a Software Interrupt, also referred to as a break instruction. For this break instruction there is no IF flag and no mask flag available. This is a non-mask-able interrupt which directly jumps into the interrupt service routine independent of any settings. 24

26 These slide shows interrupt functionality where multiple interrupts are allowed. In this example, the global interrupt flag is set to 1 by the EI instruction. Here, if an internal interrupt XX occurs, it jumps directly into the interrupt service routine. In doing so, the global interrupt enable flag is set to 0 by default, which means that no nested interrupt servicing is possible. To enable a nested interrupt servicing inside the normal interrupt service routine, the IE instruction must be done again to set the IE flag again to one. Now, if a second interrupt occurs; in this case Internal Interrupt YY which is set to a lower priority, nothing happens. The interrupt xx is executed to the end and the program counter jumps back to the main processing once instruction execution is done. Then the second interrupt service yy is serviced. 25

27 On this slide you will see an example of multiple interrupt processing where nested interrupts are executed. This is more or less an expanded example of what we saw on the previous slide. First the interrupt INTxx is given a priority level, where PR=11, and is executed inside the first interrupt service routine. As before, the global interrupt enable flag is set to one again by the EI instruction. Now, if a second interrupt occurs; in this case INTyy which has been given a higher priority level where PR=10, the first service routine is interrupted and this second interrupt is serviced. If the global interrupt enable flag is again set to one and the third interrupt occurs, in this case INTzz which has been given yet an even higher priority level where PR=01, it jumps directly into the next interrupt service routine. Returning from the interrupts, simply followings the sequence in reverse - first from the INTzz back into the INTyy and then back into the INTxx and then back into the main processing. Caution should be used when implementing this type of functionality because a stack overflow can occur. This is because the return address and program status word are saved on the stack each time a new interrupt service routine is entered. 26

28 Wrapping up, we ll take a quick look at the RL78 s on-chip debug interface, which is resident on all RL78 products. This is a one wire, Tool0 interface which is the common interface for programming as well as debugging. So the same external connection can be used for on-chip debugging and for re-programming the device via an external programmer. With the on-chip debugging, standard debug functions are supported, including SW breakpoint settings such as Go & Go, Come to here, restart, Step execution, forced break and so on. There is also a conditional hardware break point that can occur when, for example, a specific variable reaches a specific value. Furthermore, up to 2000 software breakpoints can be set. The on-chip debug interface itself is enabled or disabled via the option byte, so if you want to disable the on-chip debug interface for security reasons, this can be easily done by setting the option byte accordingly. When enabled, an optional 10 byte security ID can be set to avoid unauthorized access to the device. 27

29 Finally, here you can see the hardware connections and memory resources used by the on-chip debugger. The on-chip debugger used in this example is the E1 emulator, offered by Renesas. This is connected directly to the PC without the need of an external power supply. From the MCU s perspective, only the following connections are required: VDD, VSS, the reset pin, and of course the one wire Tool0, interface. When using the on-chip debug interface some memory resources have to be allocated inside the device. In detail these are: a hidden interrupt vector of 2 bytes at address 02 H, the option byte setting, the 10 byte security ID, the short 10 byte debug monitor area which is located from address CE H to D7 H and 1K of RAM at the end of the device s program flash memory. Also an additional 6 byte of RAM stack area must be reserved for on-chip debugging with RL devices. 28

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