MC74HCT244A Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver with LSTTL-Compatible Inputs

Transcription

1 Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver with LSTTL-Compatible Inputs High Performance Silicon Gate CMOS The MC74HCT44A is identical in pinout to the LS44. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The HCT44A is an octal noninverting buffer line driver line receiver designed to be used with 3 state memory address drivers, clock drivers, and other bus oriented systems. The device has non inverted outputs and two active low output enables. The HCT44A is the non inverting version of the HCT40. See also HCT4. Features Output Drive Capability: 5 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: A In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Chip Complexity: FETs or 8 Equivalent Gates NL Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable These Devices are Pb Free and are RoHS Compliant DATA INPUTS ENABLES A A A3 A4 B B B B4 7 ENABLE A ENABLE B 8 9 Figure. Logic Diagram YA YA YA3 YA4 YB YB YB3 YB4 PIN 0 = CC PIN 0 = GND NONINERTING S 0 SOIC 0W DW SUFFIX CASE 75D ENABLE A A YB4 3 A 4 YB3 5 A3 6 YB YB GND PIN ASSIGNMENT A TSSOP 0 DT SUFFIX CASE 948E CC ENABLE B YA B4 YA B3 YA3 B YA4 B MARKING DIAGRAMS HCT44A AWLYYWWG SOIC 0W TSSOP 0 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Outputs Enable A, Enable B A, B YA, YB L L L L H H H X Z Z = high impedance, X = don t care ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. 0 HCT 44A ALYW Semiconductor Components Industries, LLC, 04 September, 04 Rev. 4 Publication Order Number: MC74HCT44A/D

2 MAXIMUM RATINGS Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) 0.5 to +7 in DC Input oltage (Referenced to GND) 0.5 to CC out DC Output oltage (Referenced to GND) 0.5 to CC I in DC Input Current, per Pin ±0 ma I out DC Output Current, per Pin ±35 ma I CC DC Supply Current, CC and GND Pins ±75 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package T stg Storage Temperature 65 to +50 C T L Lead Temperature, mm from Case for 0 Seconds (SOIC or TSSOP Package) 60 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOIC Package: 7 mw/ C from 65 to 5 C TSSOP Package: 6. mw/ C from 65 to 5 C mw C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure ) ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions CC 55 to 5 C 85 C 5 C Unit IH Minimum High Level Input oltage out = or CC I out 0 A IL Maximum Low Level Input oltage out = or CC I out 0 A OH Minimum High Level Output oltage in = IH or IL I out 0 A in = IH or IL I out 6 ma OL Maximum Low Level Output oltage in = IH or IL I out 0 A in = IH or IL I out 6 ma I in Maximum Input Leakage Current in = CC or GND ± ±.0 ±.0 A I OZ Maximum Three State Leakage Current Output in High Impedance State in = IL or IH; out = CC or GND ±0.5 ±5.0 ±0 A I CC Maximum Quiescent Supply Current (per Package) in = CC or GND I out = 0 A A ÎÎÎÎ I CC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Additional Quiescent Supply in ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ =.4, Any One Input 55 C 5 C to 5 C ÎÎÎÎÎÎÎÎÎÎÎÎÎ Current ÎÎÎÎÎÎÎÎÎ in = CC or GND, Other Inputs ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ. Total Supply Current = I CC + Σ I CC. l out = 0 A.9.4 ma

3 AC ELECTRICAL CHARACTERISTICS ( CC = 5.0 ±0%, C L = 50 pf, Input t r = t f = 6 ns) Symbol t PLH, t PHL t PLZ, t PHZ t PZL, t PZH t TLH, t THL Parameter Maximum Propagation Delay, A to YA or B to YB (Figures and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 3 and 5) Maximum Propagation Delay, Output Enable to YA or YB (Figures 3 and 5) Maximum Output Transition Time, Any Output (Figures and 4) Guaranteed Limit 55 to 5 C 85 C 5 C Unit ns ns 8 33 ns 5 8 ns C in Maximum Input Capacitance pf C out Maximum Three State Output Capacitance (Output in High Impedance State) pf 5 C, CC = 5.0 C PD Power Dissipation Capacitance (Per Enabled Output)* 55 * Used to determine the no load dynamic power consumption: P D = C PD CC f + I CC CC. pf SWITCHING WAEFORMS INPUT A OR B t r t f 3 GND YA OR YB t PLH 0%.3 90% t PHL t TLH t THL Figure. ENABLE A OR B Y Y.3 t PZL.3 t PZH.3 t PLZ t PHZ 0% 90% 3 GND HIGH IMPEDANCE OL OH HIGH IMPEDANCE Figure 3. 3

4 TEST CIRCUITS TEST POINT DEICE UNDER TEST C L * *Includes all probe and jig capacitance Figure 4. TEST POINT DEICE UNDER TEST k C L * CONNECT TO CC WHEN TESTING t PLZ AND t PZL. CONNECT TO GND WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance Figure 5. LOGIC DETAIL TO THREE OTHER A OR B INERTERS ONE OF 8 BUFFERS DATA INPUT A OR B CC YA OR YB ENABLE A OR ENABLE B 4

5 ORDERING INFORMATION MC74HCT44ADWG Device Package Shipping SOIC 0 38 Units / Rail MC74HCT44ADWRG MC74HCT44ADTRG SOIC 0 TSSOP / Tape & Reel 500 / Tape & Reel NLHCT44ADTRG* TSSOP / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *NL Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q00 Qualified and PPAP Capable. 5

6 PACKAGE DIMENSIONS TSSOP 0 DT SUFFIX CASE 948E 0 ISSUE C 5 (0.006) T L 5 (0.006) T U X L/ PIN IDENT U S S C 0 00 (0.004) T SEATING PLANE 0X K REF 0 (0.004) M T U S S 0 A D G H B U N J J N K K ÍÍÍÍ ÍÍÍÍ SOLDERING FOOTPRINT* 7.06 SECTION N N 0.5 (0.00) M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 98.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.5 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A B C W D F G 0.65 BSC 0.06 BSC H J DETAIL E J K K L 6.40 BSC 0.5 BSC M PITCH 6X X.6 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6

7 PACKAGE DIMENSIONS SOIC 0W DW SUFFIX CASE 75D 05 ISSUE G H 0X 0.5 M B M 0 D E A h X 45 NOTES:. DIMENSIONS ARE IN MILLIMETERS.. INTERPRET DIMENSIONS AND TOLERANCES PER ASME YM, DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 3 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 0X B 0.5 M T A S 8X e 0 B B S A A T SEATING PLANE C L MILLIMETERS DIM MIN MAX A A B C D E e.7 BSC H h L ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74HCT44A/D