MikloBit ul. Cyprysowa 7/ Jaworzno Poland. JTAG + ISP for AVR. rev

Transcription

1 MikloBit ul. Cyprysowa 7/ Jaworzno Poland JTAG + ISP for AVR rev

2 Content 1.Introduction JTAG mode JTAG header pinout Debugging with JTAG Firmware upgrade ISP mode ISP headers pinout ISP connection with target board ISP programming with ISP Firmware upgrade Disclaimer Contact... 14

3 3 Introduction 1. Introduction is a dual function development tool for programming, on-chip debugging and emulation all AVR microcontrollers equipped with JTAG and ISP interface. features: JTAG debugging ( AVR JTAG ICE protocol ) ISP programming ( STK500 v2 protocol ) Avr Studio compatible Automatic recognition between JTAG/ISP interface RS232 interface to PC JTAG 10 pin connector ISP 10-pin and 6-pin connector Full emulation of all digital and analog functions in real-time Registers and memory location view Program and data memory breakpoints Source level debugging in high level languages Powered from target circuit or external supply Operating voltage V JTAG firmware upgrade when new AvrStudio is available ISP firmware upgrade with Uploader tool Supported microcontrollers - JTAG mode : ATmega16, Atmega162, ATmega169, ATmega32, ATmega323, ATmega64, ATmega128, AT90CAN128 Supported microcontrollers - ISP mode : ATmega16, ATmega169, ATmega32, ATmega323, ATmega64, ATmega128, AT90CAN128, AT90CAN64, AT90CAN32, AT90PWM2, AT90PWM3, AT90S1200, AT90S2313, AT90S2323, AT90S2343, AT90S4414, AT90S4433, AT90S4434, AT90S8515, AT90S8535, Atmega103, Atmega161, Atmega162, ATmega165, ATmega168, ATmega2560, ATmega2561, ATmega325, ATmega3250, ATmega329, ATmega3290, ATmega406, ATmega48, Atmega640, Atmega644, ATmega645, ATmega649, ATmega6490, ATmega8, ATmega8515, Atmega8535, ATmega88, ATtiny11, ATtiny12, ATtiny13, Attiny15, ATtiny22, ATtiny2313, ATtiny24, ATtiny26, ATtiny28, Attiny45, AT86RF401, AT89S51, AT89S52, Contents of box: debugger-programmer 1m ribbon cable with 10-pin JTAG header Adapter with ISP headers (6/10-pin) and socket for power supply software/documentation CD

4 JTAG mode 4 2. JTAG mode JTAG is 4-bit interface compatible with IEEE standard. IEEE was designed for efective tests of connection quality in electronic circuits. JTAG in AVR family extends the standard with in system programming and real-time emulation and debugging. in JTAG mode can be used together with Windows ( Avr Studio ) and Linux ( AvaRICE ) software and is fully comatible with oryginal JTAG ICE hardware JTAG header pinout 1 2 TCK TDO TMS VTG TDI GND VTref RST NC GND 9 10 pin I/O identification description 1 I TCK Clock signal from 2 PWR GND Signal ground 3 O TDO Transmit data to 4 PWR VTref Reference voltage from target circuit 5 I TMS Mode select 6 I/O RST RESET signal from. Do zerowania uruchamianego układu 7 PWR VTG Power supply from target circuit ( V) 8 - NC Not connected 9 I TDI Receive data from 10 PWR GND Signal ground

5 5 JTAG mode 2.2. Debugging with Connecting to PC and target board We assume, that the user has general knowledge of how to use AvrStudio. For more information please refer to the help system supplied with AvrStudio. In this section we discuss specific topics only. should be connected to PC and target board with power switched off. From PC side, connect to free COM port. AvrStudio automatically search and detect COM used. The ribbon cable should be connected to target board. If JTAG connector on the board is not equipped with key, please be sure the connector is in right position ( the arrow sign on connector should be connected to pin 1). Reverse connection could damage and/or target board. If target board is able to supply at least 30mA (@ 2.7V 5.5V) to JTAG header, direct connection can be used: If there is no power supply available on JTAG header on target board, included adapter can be used to supply from external source: Once the system is correctly connected, PC computer and target board should be powered up. The LED 1-second blink indicate the is powered and running. Then AvrStudio should be launched.

6 JTAG mode Starting debug session When launched, AvrStudio displays dialog to select debug platform and device. There is example file led.cof on the MB-JTAG-ICE CD-rom (inside example folder ). Select JTAG ICE as debug platform, AVR device you are using and object file with debug informations. AvrStudio will programm the target microcontroller with selected file and go to trace mode displaing source code if available. LED will blink during this time. If no target board is connected to or JTAGEN fuse is not programmed, window with warnig will be displayed.

7 7 JTAG mode Debugger options To access the On-Chip Debugger Options while debugging use the menu option: Debug->JTAG ICE Options Connection dialog To ensure proper communication between the and the target AVR, the OCD communication frequency from the must be equal or less than 1/4 of the target AVR frequency Debug dialog "Run Timers in Stopped Mode". This mode allows the timers to continue running at their normal speed when single stepping through the code. When this box is not checked, the timers will be increased cycle accurate to the stepping through the code. There is also an option to change the actual state of the "preserve eeprom bit" setting on the target AVR before the JTAG ICE executes a Chip Erase. After executing a Chip Erase on the target AVR, the JTAG ICE will release the Reset line if it had previously tied it down. As can be seen above this feature can be disabled. The user can enable/disable breakpoint information to be viewed in the message output window. Program Startup "Entry function". AVR Studio tries to reach the start of this function when performing a high level reset. Default function is 'main', but the user can type in another name. "Warn & break if not found or not in section corresponding to boot reset fuses". AVR Studio can detect if the entry function remains in the section stated by the boot reset fuses. If this selection is made a warning will be generated and the program will break on a reset vector if: * entry function is not specified or does not exist. * entry function remains in the application section and the boot reset fuses are programmed or if * entry function remains in boot loader section and the boot reset fuses are not programmed. If the selection is turned off, no warning will be generated and Studio will try to reach the start of the entry function.

8 JTAG mode 8 In an AVR assembler project Studio will stop on a reset vector if code is located at that location. If not Studio will perform low level single stepping until source code is reached. Advanced options. Allows the user to select how often to re-program target. Note that for speed optimization reasons the flash programming is not verified Breakpoints dialog JTAG supports up to 4 general-purpose hardware breakpoints. One is reserved for single-step so giving the user 3 breakpoints for general use. This 3 general-purpose hardware breakpoints can be used as: 3 general-purpose breakpoints 2 general-purpose breakpoints and 1 data breakpoint 1 general-purpose breakpoint and 2 data breakpoints 1 general-purpose breakpoint and 1 masked SRAM breakpoint 1 general-purpose breakpoint and 1 masked Flash breakpoint Break on change of program flow can be enabled or disabled regardless of which other breakpoint options are used. Some AVR devices support break instructions. Using break instructions means that the actual instruction is replaced by a break instruction in the Flash memory during debugging. By using break instructions an unlimited number of breakpoints can be used. Since the actual instruction is replaced by a break instruction, the flash page has to be reprogrammed when adding or removing a breakpoint. The break instructions are slower than hardware breakpoints Three different options regarding breakpoints are available: Automatic, but prefer hardware breakpoints Only use hardware breakpoints Only use break instructions Also there are data breakpoints available. The data memory breakpoints can be set to one of three modes: data memory read, data memory write or data memory read or write. Data breakpoints will work in I/O memory and SRAM only. It is not possible to set breakpoints in the Register file. When using data breakpoints, the AVR will break after executing the instruction causing the break condition.

9 9 JTAG mode 2.3. JTAG Firmware upgrade The can upgrade JTAG firmware when new AvrStudio is installed. If AvrStudio display upgrade message: follow displayed instructions: When upgrade procedure is finished, switch off then on power supply for.

10 ISP mode ISP mode in ISP mode uses STK500 v2 protocol and can be used with any software working with STK500 development board, including Avr Studio, CodeVision, command-line stk500 programmer and others. Some functions provided for real STK500 hardware ( f.e. setting target voltage and clock frequency ) are not available when working with ISP headers pinout Adapter board with two headers is included for ISP programming MOSI PROG RST SCK MISO VTG GND GND GND GND MISO SCK RST 5 6 VTG MOSI GND header 6-header I/O Signal description 1 4 I/O MOSI Received data connect with target MOSI 2 2 PWR VTG Power voltage from target board: 2.7 v 5.5 v 3 - O PROG Low level during programming ( to control LED or multiplexer on target board ) 5 5 I/O RST Reset connect with target RESET 7 3 I/O SCK Clock connect with target SCK 9 1 I/O MISO Transmited data connect with target MISO 4,6,8,10 6 PWR GND Signal ground

11 11 ISP mode 3.2. ISP connection with target board The following schematics illustrate connection with target board for ISP programming. If there is no power supply available on ISP header on target board, the MB-JTAG- TWICE can be powered from external supply connected to adapter board. When poweron, the LED will blink for 1 second, indicating the device is ready for connection. When connected, the LED will blink during ISP operations ISP programming with To ISP programming with the AvrStudio software can be used. The STK500 platform should be selected.

12 ISP mode 12 The firmware is able to idenfity incoming connection type and switch to the mode requested by PC software. The recognition is performed only when device is powered up or reset. If JTAG mode was selected, poweroff/poweron sequence is required before ISP mode can be used (and vice versa). Detailed information about using and AvrStudio in ISP mode is located in AVR Tools User Guide ( Available in AvrStudio Help menu ). Information can be found under path: STK500 User Guide -> Frontend software ISP Firmware upgrade The can upgrade ISP firmware. Don't use firmware updates included with AvrStudio. If STK500 upgrade dialog will appear : press Cancel button and follow the steps: open registry with RegEdit, browse to HKEY_LOCAL_MACHINE\SOFTWARE\Atmel\AVRTools\STK500 Change DWORD values to major/minor version expected ( 2.04 in this example ): VersionMajor to 0x02 VersionMinor to 0x04 Restart AvrStudio

13 13 ISP mode The new firmware versions are available for download at MikloBit website ( goto Electronic/Download ). Uploader tool is provided for firmware upgrade ( can be found on the CD-rom ( inside folder ). To perform upgrade follow the steps: Download archive mb_jtag_twice_isp_vx.x.zip from MikloBit website and unpack.hex file Run Uploader.exe Connect with PC and power supply In Uploader dialog: select COM port used, location of unpacked.hex file and start upgrade with Program button. When upgrade procedure is finished, switch off then on power supply for.

14 Disclaimer Disclaimer MikloBit products are designed and assembled with care and all assembled products are tested before they are shipped. However, our products are not rated for use in medical, life support, or systems where failure could result in the loss of life or have serious life threatening or economic impact. MikloBit does not warrant merchantability for any purpose and shall not be liable for any direct, indirect, incidental, special, exemplary, or consequential damages of any kind, however incurred, through the use of our products. 5. Contact MikloBit ul. Cyprysowa 7/ Jaworzno Poland tel tel./fax