Thermal Behavior and Data Processing for Multi-Chip Packages: Lateral, Stacked, PoP, and PiP

Transcription

1 Thermal Behavior and Data Processing for Multi-Chip Packages: Lateral, Stacked, PoP, and PiP Dr. Roger Emigh STATS ChipPAC, Tempe, Arizona, USA February 15,

2 Outline Introduction MCP Types and Thermal Behavior Data Techniques/JEDEC Summary Page 2

3 Introduction Multi-Chip Package (MCP) is used to describe an increasingly wide variety of configurations that have in common the presence of more than 1 functional device Ram 2 Top PKG Ram 1 Ram 4 Ram 3 SDS part Bottom PKG Spacer Bottom Chip MCP thermal behavior is modified somewhat in each configuration, some changes are required in how we test and process thermal data. Page 3

4 MCP: lateral layout Distributes heat over larger package area, reducing the need for inner planes or spreaders Heat flow and temperatures no longer symmetric Die location over ball matrix can be important: 10% higher T Maintain space between higher power devices Page 4

5 MCP: stacked structures Pyramid Stacks no wirebonding problems low K paste or film between die Same Size and Overhang Stacks spacer (silicon) required between die requires 2 paste/film layers Spacer Normally, heat concentrated at package center Lower die have less thermal resistance to the substrate Die-to-Die adhesive (paste or film) normally low K- 0.40W/mK Page 5

6 MCP: PoP and PiP- similar in many ways PoP PiP Upper devices can be thermally isolated from PCB.. Top can provide another cooling path in some cases by adding a spreader or heat sink But upper heat normally passes through perimeter of lower substrate, so minimizes their effect... PCB Page 6

7 Single Die Thermal Data- JEDEC Standards Overall goal: predict device junction temperature under defined conditions of power dissipation and ambient temp. Define testing aspects to allow data comparison between labs/companies- PCB Design- 1s0p (2L), 1s2p (4L) Testing Environments Thermal Test Die Operation Test Procedures Data Processing/Reporting Coming: Compact Modeling and MCP Natural Convection- JEDEC Cube JEDEC 51-2: minimum 20 o C temperature increase -best to have 30 o C to 60 o C increase Page 7

8 Single Die Thermal Data- JEDEC Standards Package Thermal Resistance Θ JA or Θ JMA (or R JA ) = difference between ambient and die temperature at a given power R JA = (T J -T ambient ) / Power R JA is a good thermal figure of merit for the package, ---within reason, it is used to calculate die temp for any Power level and Ambient: T J = R JA * Power + T ambient Thermal Characterization Parameters: Ψ JT = difference between package top center and die temperature, divided by total power Ψ JB = difference between top of PCB at package perimeter and die temperature, divided by total power Top Thermocouple Package Under Test Board Thermocouple Page 8

9 MCP Thermal Calculations: Thermal Interactions Between Devices: - how much depends on thermal resistance (isolation) between them Ambient Die 3 Die 2 Ambient Each die causes a T increase in itself and in all other die Die 1 Ambient (reference: Bruce Guenin, JEDEC committee proposal and Electronics Cooling, August 2006) Page 9

10 MCP Thermal Data: Linear Superposition R JA is replaced by a matrix of Fij coefficients: Fij is the effect of i on j in o C/W P 1 F 11 F 12 F 13 T 11 T 12 T 13 P 2 * F 21 F 22 F 23 = T 21 T 22 T 23 P 3 F 31 F 32 F 33 T 31 T 32 T 33 Fij coefficients determined using a series of training tests: apply power to 1 device, measure temperature rise of all the devices. T 11 + T 21 + T 31 = T 1 Sum of all T to get total T Page 10

11 MCP Thermal Data Example: Stacked Die Top Die Middle Die Spacer Bottom Die Training Matrix Power F1i Power F2i Power F3i Top 0.25W 52.6 C/W C/W C/W Middle C/W 0.5W 38.5 C/W C/W Bottom C/W C/W 0.5W 34.3 C/W Stacked Die Application Data Top Power Middle Power Bottom Power Top Temp. Middle Temp. Bottom Temp. Calculation: 0.2 W 0.4 W 0.4 W Simulation % diff: 0.18% 0.15% 0.23% Calculation: 0.2 W 0.2 W 1.0 W Simulation % diff: 0.33% 0.27% 0.39% T total, Die i = F 1i * P 1 + F 2i * P 2 + F 3i * P 3 Page 11

12 MCP Thermal Data Example: PoP Training Matrix Power F1i Power F2i Power F3i Big 1.0W 29.0C/W C/W C/W Small C/W 1.0W 35.0C/W C/W Top C/W C/W 0.5W 48.9C/W Application Data Big Power Small Power Top Power Big Temp. Small Temp. Top Temp. Calculation: 0.5W 0.5W 0.5W 115.8C 118.8C 126.5C Simulation 115.5C 118.4C 126.1C % diff: 0.34% 0.31% 0.34% Calculation: 0.75W 0.75W 0.25W 122.8C 127.1C 122.9C Simulation 122.2C 126.6C 122.3C % diff: 0.45% 0.41% 0.44% Top package device is thermally isolated, high resistance to the PCB Page 12

13 MCP: Thermal Data: Issues with Ψ JT Ψ JT = difference between Tj and package top center, divided by total power Problem: top center might not be highest temp location Possible Solutions: Use top center anyway, might not be sensitive to changes in highest T J Use highest temperature at top of package, how do we locate that? IR imaging or best guess? Which Tj do we use? Highest? Page 13

14 MCP: Thermal Data: Issues with Ψ JB Ψ JB = difference between top of PCB at package perimeter and die temperature, divided by total power Problem: PCB temp might not be the same at all sides... Possible Solutions: Use average temperature from all 4 sides, requires 4 thermocouples, not a great solution Identify the hottest side and use that, maybe... Page 14

15 MCP: Thermal Data: Issues With Compact Models Top Rjc Junction 2-Resistor Side Delphi Rjb Bottom Problem: Compact Models for packages with multiple heat sources... Possible Solutions: Top Rjc Junctions? Rjb Bottom Keep single junction, apply total power? Not good, only gives one Tj, doesn t account for differences in devices. Junction for each device, add resistors between them and also to the surfaces? Page 15

16 MCP Thermal Behavior: Summary Incorporating multiple devices in a single package is not necessarily bad thing for thermal behavior. Unless it results in too much total power.. or isolates high power devices in thermally poor locations Thermal Testing and Data Processing/Reporting Move to matrix of thermal resistance coefficients (F ij ) Training test series: power up one device at a time Use F ij matrix to get temperature increase for each device under actual power Issues remain for other thermal parameters ( Ψ JT and Ψ JB ) Compact thermal models? Page 16