Chapter 5. Thermal Processes

Transcription

1 Chapter 5 Thermal Processes 2006/9/27 1 Objective List four thermal processes Describe thermal process in IC fabrication Describe thermal oxidation process Explain the advantage of RTP over furnace Relate your job or products to the processes 2006/9/27 2 1

2 Contents Definition Hardware Oxidation Diffusion Annealing Post-Implantation Alloying Reflow High Temp CVD Epi Poly Silicon Nitride RTP RTA RTP Future Trends 2006/9/27 3 Definition Thermal processes are the processes operate at high temperature (700 ~ 1200 C), which is usually higher than melting point of aluminum. They are performed in the front-end of the semiconductor process, usually in high temperature furnace commonly called diffusion furnace. Oxidation, diffusion, deposition, annealing and RTP (rapid thermal process) are included. Oxidation and Diffusion were the backbone processes in early-year IC fabrication. 2006/9/27 4 2

3 Hardware - Furnace The most commonly used tool for thermal processes in semiconductor fabrication. Consists of loading system, process tubes, gas delivery system, control system and exhaust system. Horizontal and vertical types, the latter equips with smaller footprint, low particle contamination, ability to handle larger wafers and better uniformity. Quartz and SiC are the main material to endure thermal process. Microcontrollers, mass flow controllers (MFCs), paddles are often employed. Multi-tube system (2 ~ 4 tubes) for oxidation, diffusion and low pressure CVD. 2006/9/27 5 Layout of a Horizontal Furnace Exhaust Gas Deliver System Process Tubes Loading System Control System 2006/9/27 6 3

4 Control System Computer Microcontroller Microcontroller Microcontroller Microcontroller Microcontroller Process Tube Interface Board Exhaust Interface Board Gas Panel Interface Board Loading Station Interface Board Vacuum System Interface Board 2006/9/27 7 Gas Deliver System MFC MFC MFC To Process Tube Regulator Control Valve Gas cylinders 2006/9/27 8 4

5 Source Gas Cabinet Source Gases Oxygen Water Vapor Nitrogen Hydrogen Gas control panel Gas flow controller Gas flow meter 2006/9/27 9 Oxidation Sources Dry Oxygen Water vapor delivery Boiler Bubblers Flash systems Pyrogenic system : H 2 + O 2 H 2 O with a torch flame Chlorine sources, for minimized mobile ions in gate oxidation Anhydrous hydrogen chloride HCl Trichloroethylene (TCE), Trichloroethane (TCA) 2006/9/

6 Boiler System Heated Gas line Heated Fore line MFC Process Tube Exhaust Vapor Bubbles Water Heater 2006/9/27 11 Bubbler System N 2 Water MFC N 2 + H 2 O Process Tube Heated Gas Line N 2 Bubbles Exhaust Heater 2006/9/

7 Flush System Hot Plate Water N 2 MFC Process Tube Heater 2006/9/27 13 Pyrogenic Steam System Hydrogen Flame, 2 H 2 + O 2 2 H 2 O O 2 H 2 To Exhaust Thermal Couple Process Tube Paddle Wafer Boat 2006/9/

8 Pyrogenic System Advantage All gas system Precisely control of flow rate Disadvantage Introducing of flammable, explosive hydrogen Typical H 2 :O 2 ratio is between 1.8:1 to 1.9: /9/27 15 Pyrogenic Wet Oxidation System MFC Process Tube MFC MFC MFC Wafers Burn Box Control Valves H 2 Process N 2 O 2 Purge N 2 Regulator Scrubbier Exhaust 2006/9/

9 P-type dopant Diffusion Sources B 2 H 6, burnt chocolate, sickly sweet odor Poisonous, flammable, and explosive N-type dopants PH 3, rotten fish smell AsH 3, garlic smell Poisonous, flammable, and explosive Purge gas N /9/27 17 Deposition Sources Silicon source for poly and nitride deposition: Silane, SiH 4, pyrophoric, toxic and explosive DCS, SiH 2 Cl 2, extremely flammable Nitrogen source for nitride deposition: NH 3, pungent, irritating odor, corrosive Dopants for polysilicon deposition B 2 H 6, PH 3 and AsH 3 Purge gas N /9/

10 Anneal Sources High purity N 2, is used for most anneal processes. H 2 O sometimes used as ambient for PSG or BPSG reflow. O 2 is used for USG anneal after USG CMP in STI formation process. Lower grade N 2 is used for idle purge. 2006/9/27 19 Exhaust System Removal of hazardous gases before release Poisonous, flammable, explosive and corrosive gases. Burn box removes most poisonous, flammable and explosive gases Scrubber removes burned oxide and corrosive gases with water. Treated gases exhaust to the atmosphere. 2006/9/

11 Wafer Loading, Horizontal System Wafers Process gases To Exhaust Process Tube Paddle Wafer Boat 2006/9/27 21 Temperature Control Thermal processes are very sensitive to the temperature Precisely temperature control is vital 0.5 C at central zone 0.05% at 1000 C! 2006/9/

12 Temperature Control System Thermocouples touching the reaction tube Proportional band controllers feed the power to the heating coils The heating power is proportional to difference between setting point and measured value 2006/9/27 23 Reaction Chamber High-purity Quartz Stability at high temperature Basic Cleanliness Drawback Fragility Some metallic ions Not a sodium barrier Small flakes at > 1200 C, devitrification 2006/9/

13 Horizontal Furnace Heating Coils Wafers Quartz Tube Gas flow Temperature Center Zone Flat Zones (3~5) Distance 2006/9/27 25 Vertical Furnace, Process Position Process Chamber Wafers Heaters Suscepter Tower 2006/9/

14 Quartz Tube Electric Fused Flame Fused Both of them as trace amount of metals Flame-fused tubes produced devices have better characteristics. 2006/9/27 27 Quartz Tube Clean Very important especially for deposition furnace to prevent particle contamination Ex-situ clean Hydrofluoric acid (HF) tank Remove a thin layer of quartz every time limited tube lifetime In-situ clean Plasma generator inside tube Free fluorine from NF 3 etch away contaminant 2006/9/

15 Silicon Carbide Tube Pros Higher thermal stability (> 1200 C) Better metallic ion barrier Cons Heavier More expensive than quartz 2006/9/27 29 Ramping Temperature Control Anti-Warp Methods Load wafer slowly at a lower temperature (idle temperature, ~ 800 C) Ramp temperature to process point after a short stabilization period Slow loading 1 inch/min thermal capacity of 200 six-inch wafers can drop temperature as much as 50 C 2006/9/

16 Horizontal Furnace Heating Coils Wafers Quartz Tube Gas flow Temperature Center Zone Flat Zone Distance 2006/9/27 31 Vertical Furnaces Place the process tube in vertical direction Smaller footprint Better contamination control Better wafer handling Lower maintenance cost and higher uptime 2006/9/

17 Vertical Furnace, Loading and Unloading Position Process Chamber Heaters Wafers Suscepter Tower 2006/9/27 33 Smaller Footprint Clean room footage becomes very expensive Small footprint reduces cost of ownership (COO) 2006/9/

18 Better Contamination Control Gas flow from top to bottom Better uniformity for Laminar gas flow control Particles has less chance to fall at the center of the wafers 2006/9/27 35 Better Wafer Handling High torque on paddle of horizontal when it handle large amount of large diameter wafers Zero torque for wafer tower in vertical system 2006/9/

19 Summery of Hardware Furnaces are commonly used in thermal processes Furnaces usually consist with control system, gas delivery system, process tube or chamber, wafer loading system, and exhaust system. Vertical furnace is more widely used due to it smaller footprint, better contamination control, and lower maintenance. Precise temperature and its uniformity is vital for the success of the thermal processes. 2006/9/27 37 Oxidation 2006/9/

20 Oxidation Introduction Applications Mechanism Process System RTO 2006/9/27 39 Introduction Silicon reacts with oxygen Stable oxide compound Widely used in IC manufacturing Si + O 2 SiO /9/

21 Oxidation Original Silicon Surface O 2 Silicon Dioxide Silicon O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 O 2 55% 45% 2006/9/27 41 Application of Oxidation Diffusion Masking Layer Surface Passivation Screen oxide, pad oxide, barrier oxide Isolation Field oxide and LOCOS (local oxidation of silicon) Gate oxide 2006/9/

22 Diffusion Barrier Much lower B and P diffusion rates in SiO 2 than that in Si SiO 2 can be used as diffusion mask Dopant SiO 2 SiO 2 Si 2006/9/27 43 Application, Surface Passivation Pad Oxide Sacrificial Oxide Screen Oxide Barrier Oxide SiO 2 Si Normally thin oxide layer (~150Å) to protect silicon defects from contamination and over-stress. 2006/9/

23 Screen Oxide Dopant Ions Photoresist Photoresist Si Substrate Screen Oxide 2006/9/27 45 Pad and Barrier Oxides in STI Process Nitride Pad Oxide Silicon Trench Etch Nitride Pad Oxide USG Silicon Barrier Oxide USG Trench Fill Silicon USG CMP; USG Anneal; Nitride and Pad Oxide Strip 2006/9/

24 Application, Pad Oxide Relieve strong tensile stress of the nitride Prevent stress induced silicon defects Pad Oxide Silicon nitride Silicon Substrate 2006/9/27 47 Application, Device Isolation Electronic isolation of neighboring devices Blanket field oxidation Local oxidation of silicon (LOCOS) Thick oxide, usually 3,000 to 10,000 Å 2006/9/

25 Blanket Field Oxide Isolation Silicon Wafer Clean Silicon Dioxide Silicon Activation Area Field Oxidation Field Oxide Silicon Oxide Etch 2006/9/27 49 LOCOS Process Pad Oxide Silicon nitride P-type substrate Pad oxidation, nitride deposition and patterning Silicon nitride SiO 2 p + P-type substrate p + Isolation Doping p + LOCOS oxidation Bird s Beak SiO 2 p + P-type substrate p + Isolation Doping p + Nitride and pad oxide strip 2006/9/

26 LOCOS Compare with blanket field oxide Better isolation Lower step height Less steep sidewall Disadvantage rough surface topography Bird s beak Recently replaced by shallow trench isolation (STI) 2006/9/27 51 Application, Sacrificial Oxide Defects removal from silicon surface STI STI STI Sacrificial Oxide P-Well P-Well Gate Oxide P-Well USG N-Well Sacrificial Oxidation USG N-Well Strip Sacrificial Oxide USG N-Well Gate Oxidation 2006/9/

27 Application, Device Dielectric Gate oxide: thinnest and most critical layer Capacitor dielectric V G V D > 0 Poly Si Gate Thin oxide n + Source Electrons p-si n + Drain Si Substrate 2006/9/27 53 Oxide and It s Applications Name of the Oxide Thickness Application Time in application Native Å undesirable - Screen ~ 200 Å Implantation Mid-70s to present Masking ~ 5000 Å Diffusion 1960s to mid-1970s Field and LOCOS Å Isolation 1960s to 1990s Pad Å Nitride stress buffer 1960s to present Sacrificial <1000 Å Defect removal 1970s to present Gate Å Gate dielectric 1960s to present Barrier Å STI 1980s to present 2006/9/

28 Silicon Dioxide Grown on Improperly Cleaned Silicon Surface 2006/9/27 55 Pre-oxidation Wafer Clean Particulates Organic residues Inorganic residues Native oxide layers 2006/9/

29 RCA Clean Developed by Kern and Puotinen in 1960 at RCA Most commonly used clean processes in IC fabs SC-1-- NH 4 OH:H 2 O 2 :H 2 O with 1:1:5 to 1:2:7 ratio at 70 to 80 C to remove organic contaminants. SC-2-- HCl:H 2 O 2 :H 2 Owith 1:1:6 to 1:2:8 ratio at 70 to 80 C to remove inorganic contaminates. DI water rinse HF dip or HF vapor etch to remove native oxide. 2006/9/27 57 Pre-oxidation Wafer Clean Particulate Removal High purity deionized (DI) water or H 2 SO 4 :H 2 O 2 followed by DI H 2 O rinse. High pressure scrub or immersion in heated dunk tank followed by rinse, spin dry and/or dry bake (100 to 125 C). 2006/9/

30 Pre-oxidation Wafer Clean Organic Removal Strong oxidants remove organic residues. H 2 SO 4 :H 2 O 2 or NH 3 OH:H 2 O 2 followed by DI H 2 O rinse. High pressure scrub or immersion in heated dunk tank followed by rinse, spin dry and/or dry bake (100 to 125 C). 2006/9/27 59 Pre-oxidation Wafer Clean Inorganic Removal HCl:H 2 O. Immersion in dunk tank followed by rinse, spin dry and/or dry bake (100 to 125 C). 2006/9/

31 Pre-oxidation Wafer Clean Native Oxide Removal HF:H 2 O. Immersion in dunk tank or single wafer vapor etcher followed by rinse, spin dry and/or dry bake (100 to 125 C). 2006/9/27 61 Oxidation Mechanism Si + O 2 SiO 2 Oxygen comes from gas Silicon comes from substrate Oxygen diffuse cross existing silicon dioxide layer and react with silicon The thicker of the film, the lower of the growth rate 2006/9/

32 Oxide Growth Rate Regime Oxide Thickness Linear Growth Regime B X = t A Diffusion-limited Regime X = B t Oxidation Time 2006/9/27 63 Oxide Thickness (micron) <100> Silicon Dry Oxidation 1.2 <100> Silicon Dry Oxidation C 1150 C 1100 C 1050 C 1000 C 950 C 900 C Oxidation Time (hours) 2006/9/

33 Wet (Steam) Oxidation Si + 2H 2 O SiO 2 + 2H 2 At high temperature H 2 O is dissociated to H and H-O H-O diffuses faster in SiO 2 than O 2 Wet oxidation has higher growth rate than dry oxidation. 2006/9/27 65 <100> Silicon Wet Oxidation Rate Oxide Thickness (micron) <100> Silicon Wet Oxidation 1150 C 1100 C 1050 C 1000 C 950 C 900 C Oxidation Time (hours) 2006/9/

34 2006/9/27 67 Factors on Oxidation Rate Temperature Chemistry, wet or dry oxidation Thickness Pressure Wafer orientation (<100> vs. <111>) Silicon dopant 2006/9/

35 Oxidation Rate Temperature Oxidation rate is very sensitive (exponentially related) to temperature Higher temperature will have much higher oxidation rate. The higher of temperature is, the higher of the chemical reaction rate between oxygen and silicon is and the higher diffusion rate of oxygen in silicon dioxide is. 2006/9/27 69 Oxidation Rate Wafer Orientation <111> surface has higher oxidation rate than <100> surface. More silicon atoms on the surface. 2006/9/

36 Wet Oxidation Rate Oxide Thickness (micron) <111> Orientation 95 C Water 1200 C 1100 C 1000 C 920 C Oxidation Time (hours) 2006/9/27 71 Oxidation Rate Dopant Concentration Dopant elements and concentration Highly phosphorus doped silicon has higher growth rate, less dense film and etch faster. Generally highly doped region has higher grow rate than lightly doped region. More pronounced in the linear stage (thin oxides) of oxidation. 2006/9/

37 Oxidation: Dopants Pile-up and Depletion Effects N-type dopants (P, As, Sb) have higher solubility in Si than in SiO 2, when SiO 2 grow they move into silicon, it is call pile-up or snowplow effect. Boron tends to go to SiO 2, it is called depletion effect. 2006/9/27 73 Depletion and Pile-up Effects Original Si Surface Si-SiO 2 interface Original Si Surface Si-SiO 2 interface Dopant Concentration SiO 2 Original Distribution Si Dopant Concentration SiO 2 Si P-type Dopant Depletion N-type dopant Pile-up 2006/9/

38 Oxidation Rate Doped oxidation (HCl) HCl is used to reduce mobile ion contamination. Widely used for gate oxidation process. Growth rate can increase from 1 to 5 percent. 2006/9/27 75 Oxidation Rate Differential Oxidation The thicker of the oxide film is, the slower of the oxidation rate is. Oxygen need more time to diffuse cross the existing oxide layer to react with substrate silicon. 2006/9/

39 Pre-oxidation Clean Thermally grown SiO 2 is amorphous. Tends to cross-link to form a crystal In nature, SiO 2 exists as quartz and sand Defects and particles can be the nucleation sites Crystallized SiO 2 with poor barrier capability. Need clean silicon surface before oxidation. 2006/9/27 77 Oxidation Process Dry Oxidation, thin oxide Gate oxide Pad oxide, screen oxide, sacrificial oxide, etc. Wet Oxidation, thick oxide Field oxide Diffusion masking oxide 2006/9/

40 Dry Oxidation System MFC MFC MFC To Process Tube MFC Control Valves HCl Process N 2 O 2 Purge N 2 Regulator 2006/9/27 79 Dry Oxidation Dry O 2 as the main process gas HCl is used to remove mobile ions for gate oxidation High purity N 2 as process purge gas Lower grade N 2 as idle purge gas 2006/9/

41 Gate Oxidation Steps Idle with purge N 2 flow Idle with process N 2 flow Wafer boats push-in with process N 2 flow Temperature ramp-up with process N 2 flow Temperature stabilization with process N 2 flow Oxidation with O 2, HCl, stop N 2 flow 2006/9/27 81 Dangling Bonds and Interface Charge Interface State Charge (Positive) Dangling Bond SiO Si-SiO 2 Interface Si 2006/9/

42 Gate Oxidation Steps, Continue Oxide annealing, stop O 2, start process flow N 2 Temperature cool-down with process N 2 flow Wafer boats pull-out with process N 2 flow Idle with process N 2 flow Next boats and repeat process Idle with purge N 2 flow 2006/9/27 83 Wet Oxidation Process Faster, higher throughput Thick oxide, such as LOCOS Dry oxide has better quality Process Temperature Film Thickness Oxidation Time Dry oxidation 1000 C 1000 Å ~ 2 hours Wet oxidation 1000 C 1000 Å ~ 12 minutes 2006/9/

43 Wet Oxidation Process Steps Idle with purge N 2 flow Idle with process N 2 flow Ramp O 2 with process N 2 flow Wafer boat push-in with process N 2 and O 2 flows Temperature ramp-up with process N 2 and O 2 flows Temperature stabilization with process N 2 and O 2 flows Ramp O 2, turn-off N 2 flow Stabilize the O 2 flow 2006/9/27 85 Wet Oxidation Process Steps Turn-on H 2 flow, ignition and H 2 flow stabilization Steam oxidation with O 2 and H 2 flow Hydrogen termination, turn-off H 2 while keeping O 2 flow Oxygen termination, turn-off O 2 start process N 2 flow Temperature ramp-down with process N 2 flow Wafer boat pull-out with process N 2 flow Idle with process N 2 flow Next boats and repeat process Idle with purge N 2 flow 2006/9/

44 Rapid Thermal Oxidation For gate oxidation of deep sub-micron device Very thin oxide film, < 30 Å Need very good control of temperature uniformity, WIW and WTW. Due to reduced feature size, RTO will be used to achieve the device requirement. 2006/9/27 87 RTP Process Diagram Load wafer Ramp up 1& 2 RTO RTA Cool down Unload wafer O 2 flow Temperature HCl flow N 2 flow Time 2006/9/

45 High Pressure Oxidation Faster growth rate Reducing oxidation temperature: 1 amt. = 30 C Higher dielectric strength 2006/9/27 89 High Pressure Oxidation Stainless Steel Jacket High Pressure Inert Gas High Pressure Oxidant Gas Quartz Process Chamber 2006/9/

46 High Pressure Oxidation Oxidation time to grow 10,000 Å wet oxide Temperature Pressure Time 1 atmosphere 5 hours 1000 C 5 atmosphere 1 hour 25 atmosphere 12 minutes 2006/9/27 91 High Pressure Oxidation Oxidation temperature to grow 10,000 Å wet oxide in 5 hours Time Pressure Temperature 1 atmosphere 1000 C 5 hours 10 atmosphere 700 C 2006/9/

47 High Pressure Oxidation Requires complex system Concerns safety issues Not widely used in IC production today 2006/9/27 93 Oxide Measurement Thickness Uniformity Color chart Ellipsometry Reflectometry Gate oxide Break down voltage C-V characteristics 2006/9/

48 Ellipsometry Linearly Polarized Incident Light Elliptically Polarized Reflected Light s p n 1, k 1, t1 n 2, k 2 To measure film refractive index and thickness 2006/9/27 95 Reflectometry - film color difference Incident light 1 2 Human eye or photodetector t Dielectric film, n( ) Substrate 2006/9/

49 C-V Test Configuration Large Resistor Capacitor Meter Oxide Aluminum Silicon Metal Platform Heater Heater 2006/9/27 97 Summary of Oxidation Oxidation of silicon High stability and relatively easy to form. Applications Isolation, masking, pad, barrier, gate, and etc. Wet and Dry oxidation More dry processes for advanced IC chips Rapid thermal oxidation and annealing for ultra-thin gate oxide 2006/9/

50 Diffusion Process 2006/9/27 99 Diffusion Most common physics phenomena Materials disperse from higher concentration to lower concentration region Silicon dioxide as diffusion mask Was widely used for semiconductor doping Predeposition step and then drive-in Predeposition step includes solid (B or P disks), liquid (POCl 3 ) or gas (B 2 H 6, AsH 3, PH 3 ) sources Need a dedicated tube to avoid cross-contamination! 2006/9/

51 Illustration of Diffusion Doping Dopant Silicon 2006/9/ Illustration of Diffusion Doping After a certain thermal budget Dopant Junction Depth Silicon 2006/9/

52 Definition of Junction depth Dopant Concentration Junction Depth, x j Background dopant concentration Dopant Concentration Distance from the wafer surface 2006/9/ Diffusion Masking Oxide Masking Oxide N-Silicon p + p + N-Silicon 2006/9/

53 Thermal Budget Dopant atoms diffuse fast at high temperature D = D 0 exp ( E A /kt) Smaller device geometry has less room for dopant thermal diffusion, i.e. less thermal budget Thermal budget determines the appropriate time and temperature of the post-source/drain thermal processes 2006/9/ Illustration of Thermal Budget Gate S/D Implantation Over Thermal Budget 2006/9/

54 Thermal Budget T ( C) 1 m 0.5 m m Thermal Budget (sec) m Source: Chang and Sze, ULSI Technology /T (K) 2006/9/ Diffusion Doping Process Both dopant concentration and junction depth are related to temperature. No way to independently control both factors Isotropic dopant profile Mostly replaced by ion implantation after the mid-1970s. 2006/9/

55 Diffusion Doping Process Silicon dioxide as hard mask Deposit dopant oxide (thermal proc.) Cap oxidation : the oxide layer over the active region prevent dopant back-diffusion into gas phase Drive-in (thermal proc.) 2006/9/ Diffusion Doping Process Oxidation, photolithography and oxide etch Pre-deposition: B 2 H O 2 B 2 O H 2 O Cap oxidation: 2 B 2 O Si 3 SiO B 2 H 2 O + Si SiO H 2 Drive-in Boron diffuses into silicon substrate 2006/9/

56 Diffusion Doping Process Oxidation, photolithography and oxide etch Deposit dopant oxide: 4POCl 3 + 3O 2 2P 2 O 5 + 3Cl 2 Cap oxidation 2P 2 O 5 + 5Si 5SiO 2 + 4P Phosphorus concentrates on silicon surface Drive-in Phosphorus diffuses into silicon substrate 2006/9/ Phosphorus Diffusion System MFC Process Tube MFC MFC MFC Wafers Burn Box Control Valves POCl 3 Process N 2 O 2 Purge N 2 Regulator Scrubbier Exhaust 2006/9/

57 Wafer Clean Si Substrate 2006/9/ Oxidation SiO 2 Si Substrate 2006/9/

58 Doped Area Patterning PR SiO 2 Si Substrate 2006/9/ Etch Silicon Dioxide PR SiO 2 Si Substrate 2006/9/

59 Strip Photoresist SiO 2 Si Substrate 2006/9/ Wafer Clean SiO 2 Si Substrate 2006/9/

60 Dopant Oxide Deposition Deposited Dopant Oxide SiO 2 Si Substrate 2006/9/ Cap Oxidation SiO 2 Si Substrate 2006/9/

61 Phosphoric Oxide Deposition and Cap Oxidation Push Temp Ramp Temp. Stab. Dopant Deposition Cap Oxide N 2 Vent Ramp Down Pull Temperature N 2 Flow POCl 3 Flow O 2 Flow Wafer Position 2006/9/ Drive-in SiO 2 Si Substrate 2006/9/

62 Strip Oxide, Ready for Next Step SiO 2 Si Substrate 2006/9/ Phosphorus Drive-in Push Stab. Temp Ramp Temp. Stab. Drive-in Ramp Down Pull Temperature N 2 Flow O 2 Flow Wafer Position 2006/9/

63 Limitations and Applications Diffusion is isotropic process and always dope underneath masking oxide Can t independently control junction depth and dopant concentration Still used for well implantation & drive-in R&D for ultra shallow junction (USJ) formation 2006/9/ Application of Diffusion: Drive-in Wells have the deepest junction depth Need very high ion implantation energy Cost of MeV ion implanters is very high Diffusion can help to drive dopant to the desired junction depth while annealing wafers 2006/9/

64 Well Implantation and Drive-in Photoresist P + P-Epi N-Well P-Epi N-Well 2006/9/ Diffusion for Boron USJ Formation Small devices needs ultra shallow junction Boron is small and light, implanter energy could be too high for it goes too deep Controlled thermal diffusion is used in R&D for shallow junction formation 2006/9/

65 Surface Clean Silicide Sidewall Spacer Sidewall Spacer STI Si Substrate STI 2006/9/ BSG CVD Silicide Sidewall Spacer Sidewall Spacer Boron-Silicate Glass STI Si Substrate STI 2006/9/

66 RTP Dopant Drive-in Gate Oxide Polysilicon Silicide Boro-Silicate Glass STI Si Substrate STI 2006/9/ Strip BSG Polysilicon Gate Oxide Silicide STI Si Substrate STI 2006/9/

67 Four-Point Probe Measurement I V R s = l/wt P 1 P 2 P 3 P 4 S 1 S 2 S 3 Doped Region Substrate 2006/9/ Summary of Diffusion Physics of diffusion process is well understood Diffusion was widely used in doping processes in early IC manufacturing and rapidly replaced by ion implantation since the mid-1970s Some R&D work may still adopt diffusion process in view of cost 2006/9/

68 Annealing and RTP Processes 2006/9/ Post-implantation Annealing Energetic ions damage crystal structure after implantation Amorphous silicon has high resistivity Need external energy such as heat for atoms to recover single crystal structure Only in single crystal structure dopants can be activated to provide electrons or holes as the majority carriers 2006/9/

69 Post-implantation Annealing Single-crystal structure has lowest potential energy Atoms tend to stop on lattice grid Heat can provide external energy to atoms for fast thermal motion Atoms will find and settle at the lattice grid where has the lowest potential energy Higher temperature, faster annealing Furnace tube or RTA facility, the latter has much better wafer-to-wafer (WTW) temperature uniformity control 2006/9/ Before Ion Implantation Lattice Atoms 2006/9/

70 After Ion Implantation Lattice Atoms Dopant Atom 2006/9/ Thermal Annealing Lattice Atoms Dopant Atom 2006/9/

71 Thermal Annealing Lattice Atoms Dopant Atoms 2006/9/ Alloy Annealing A thermal process in which different atoms chemically bond with each other to form a metal alloy. Widely used in silicide formation Self aligned silicide (salicide) Titanium silicide, TiSi 2 Cobalt silicide, CoSi 2 Furnace process and RTP are often employed 2006/9/

72 Silicide Much lower resistivity than polysilicon Used as gate and local interconnection Used as capacitor electrodes Improving device speed and reduce heat generation TiSi 2, WSi 2 are the most commonly used silicide CoSi 2, MoSi 2, and etc are also used 2006/9/ Titanium Silicide Process Argon sputtering clean Titanium PVD RTP Anneal, ~700 C Strip titanium, H 2 O 2 :H 2 SO /9/

73 Titanium Silicide Process Titanium Polysilicon n + n + STI USG p + p + Ti Deposition Titanium Silicide STI n + n + USG p + p + Annealing Sidewall Spacer Titanium Silicide STI n + n + USG p + p + Ti Strip 2006/9/ Aluminum-silicon Alloy Form on silicon surface Prevent junction spiking due to silicon dissolving in aluminum Al p + SiO 2 Al p + Al n-type Silicon 2006/9/

74 Reflow Flowed surface is smoother and flatter Easier for photolithography and metallization Higher temperature, better reflow result Reflow time and temperature are determined by the thermal budget Higher dopant concentration requires lower reflow temperature 2006/9/ Illustration of BPSG Reflow As Deposit p + PSG n + n + LOCOS SiO 2 p + p + p + P-type substrate N-well After Reflow p + PSG n + n + LOCOS SiO 2 p + p + p + P-type substrate N-well 2006/9/

75 PSG Reflow Results 2006/9/ Reflow Undoped silicate glass (USG) becomes soft at very high temperature T > 1500 C, will flow due to the surface tension PSG and BPSG become soft at significant lower temperature (< 1100 C down to 850 C) Phosphorus also can trap sodium PSG and BPSG is commonly used as pre-metal dielectric (PMD) 2006/9/

76 Summary of Anneal The most commonly used anneal processes are post-implantation annealing, alloy annealing and reflow Thermal anneal is required after ion implantation for recover crystal structure and activation dopant atoms Thermal anneal helps metal to react with silicon to form silicides 2006/9/ Summary of Anneal Metal anneal helps to form larger grain size and reduces the resistivity PSG or BPSG reflow smoothens and flattens the dielectric surface and helps photolithography and metallization processes RTP becomes more commonly used in annealing processes 2006/9/

77 Summary of Anneal Advantages of RTP Much faster ramp rate (75 to 150 C/sec) Higher temperature (up to 1200 C) Faster process Minimize the dopant diffusion Better control of thermal budget Better wafer to wafer uniformity control 2006/9/ High Temperature Chemical Vapor Deposition Processes 2006/9/

78 What is CVD? Chemical Vapor Deposition Gas(es) or vapor(s) chemically react on substrate surface and form solid byproduct on the surface as deposited thin film. Other byproducts are gases and leave the surface. Widely used in IC processing for metal, dielectric and silicon thin film deposition. 2006/9/ High Temperature CVD Epitaxy Polysilicon LPCVD Silicon Nitride 2006/9/

79 Epitaxy Monocrystralline layer Epitaxy silicon Epitaxy silicon-germanium Epitaxy GaAs 2006/9/ Epitaxy Silicon Provide high quality silicon substrate without trace amount of oxygen and carbon. Required for bipolar devices. Needed for high performance CMOS devices. 2006/9/

80 Epitaxy Silicon High temperature (~1000 C) processes. Silane (SiH 4 ), DCS (SiH 2 Cl 2 ) or TCS (SiHCl 3 ) as silicon source gases. Hydrogen as process gas and purge gas Arsine (AsH 3 ), Phosphine (PH 3 ), and Diborane (B 2 H 6 ) are used as dopant gases. 2006/9/ Epitaxy Silicon Deposition Silane process Heat (1000 C) DCS process SiH 4 Si + H 2 Silane Epi-Si Hydrogen Heat (1150 C) SiH 2 Cl 2 Si + 2HCl Silane Epi-Si Hydrochloride 2006/9/

81 Epitaxy Silicon Doping N-type Dopant Heat (1000 C) AsH 3 As + 3/2 H 2 Arsine As Hydrogen Heat (1000 C) PH 3 P + 3/2 H 2 Arsine Phosphorus Hydrogen 2006/9/ Epitaxy Silicon Doping P-type Dopant Heat (1000 C) B 2 H 6 2 B + 3 H 2 Diborane Boron Hydrogen 2006/9/

82 Epitaxy Silicon Usually deposited ( grown ) by wafer manufacturer instead by IC fab. In fab epi process: special needs such as dopant concentration and epi thickness. Selective epi for raised source/drain. Single wafer epitaxy process. 2006/9/ Polysilicon High temperature stability. Reasonable good conductivity. Widely used for the gate and local interconnection in MOS devices. Also widely used as the capacitor electrodes in memory devices, especially DRAM. 2006/9/

83 Polysilicon Applications in DRAM Ta 2 O 5 or BST Poly 5 Poly 4 TiSi 2 Poly 3 Poly 1 Sidewall Spacer n + n + n + p-silicon Poly /9/ Polysilicon High temperature (~700 C) furnace LPCVD processes. Silane (SiH 4 ) or DCS (SiH 2 Cl 2 ) as silicon source gases. Nitrogen as purge gas Arsine (AsH 3 ), Phosphine (PH 3 ), and Diborane (B 2 H 6 ) are used as dopant gases. 2006/9/

84 Polysilicon Deposition Silane process Heat (750 C) DCS process SiH 4 Si + H 2 Silane Poly-Si Hydrogen Heat (750 C) SiH 2 Cl 2 Si + 2HCl Silane Poly-Si Hydrochlride 2006/9/ N-type Dopant Polysilicon Doping Heat (750 C) AsH 3 As + 3/2 H 2 Arsine As Hydrogen Heat (750 C) PH 3 P + 3/2 H 2 Phosphine Phosphorus Hydrogen 2006/9/

85 P-type Dopant Polysilicon Doping Heat (750 C) B 2 H 6 2 B + 3 H 2 Diborane Boron Hydrogen 2006/9/ Temperature Relationship of Silane Process On single crystal silicon substrate Silane as source gases T > 900 C deposit single crystal silicon 900 C > T > 550 C deposit polysilicon T < 550 C deposit amorphous silicon 2006/9/

86 Temperature and Crystal Structure for Silane Processes Grain Boundary Grain T<550 C Amorphous Si 550 C <T< 900 C Polysilicon T > 900 C Single Crystal Si 2006/9/ Polysilicon LPCVD System MFC Process Tube MFC MFC Control Valves Wafers Burn Box SiH 4 Process N 2 Purge N 2 Regulator Scrubbier Exhaust 2006/9/

87 Polysilicon Deposition Process Idle with purge N 2 flow Idle with process N 2 flow Wafer load into tower with process N 2 flow Tower raises into process chamber (bell jar) with process N 2 flow Pump down chamber to base pressure (< 2 mtorr) by turningoff N 2 flow Stabilize wafer temperature with N 2 flow and leak check Set up process pressure (~250 mtorr) and with N 2 flow Turn-on SiH 4 flow and turn-off N 2, start deposition Close gate valve, fill N 2 and ramp-up pressure to atmospheric pressure Tower lowed and wafer temperature cooled down, with process N 2 flow Unload wafer with process N 2 flow Idle with purge N 2 flow 2006/9/ Polysilicon Deposition Process Chamber Temperature Load Wafer Raise Tower Pump Down Temp. Stab. Pump Down Press. Stab. Si 3 N 4 Dep. Pump Down N 2 Vent Lower Tower Unload Wafer Wafer Temperature N 2 Flow Silane Flow Chamber Pressure Wafer Tower Position 2006/9/

88 Silicon Nitride Dense material Widely used as diffusion barrier layer and passivation layer LPCVD (front-end) and PECVD (back-end) LPCVD nitride usually is deposited in a furnace 2006/9/ Application of Silicon Nitride LOCOS formation as oxygen diffusion barrier STI formation as oxide CMP stop PMD barrier layer Etch stop layer Passivation 2006/9/

89 LOCOS Process Pad Oxide Silicon nitride P-type substrate Pad oxidation, nitride deposition and patterning Silicon nitride SiO 2 p + P-type substrate p + Isolation Doping p + LOCOS oxidation Bird s Beak SiO 2 p + P-type substrate p + Isolation Doping p + Nitride and pad oxide strip 2006/9/ STI Process Nitride Pad Oxide Silicon Pad Oxidation and LPCVD Nitride Nitride Pad Oxide Nitride Pad Oxide Photoresist Silicon Silicon Etch Nitride and Pad Oxide Strip Photoresist Photoresist 2006/9/

90 STI Process Nitride Pad Oxide Silicon Trench Trench on Silicon Barrier oxidation, CVD USG Trench Fill Nitride Pad Oxide Silicon USG Barrier Oxide Silicon USG USG CMP; Nitride, Pad Oxide Strip 2006/9/ Self-aligned Contact Etch Stop Photoresist Photoresist Oxide Nitride BPSG BPSG TiSi 2 n + n + p-silicon n + Sidewall Spacer Poly Gate 2006/9/

91 Nitride Breakthrough Photoresist Photoresist Oxide BPSG BPSG Sidewall Spacer Nitride n + TiSi 2 n + p-silicon n + Poly Gate 2006/9/ Strip Photoresist Oxide BPSG BPSG Sidewall Spacer Nitride n + TiSi 2 n + p-silicon n + Poly Gate 2006/9/

92 Deposit Ti/TiN and Tungsten Ti/TiN Oxide BPSG W BPSG Sidewall Spacer Nitride n + TiSi 2 n + p-silicon n + Poly Gate 2006/9/ CMP Tungsten and TiN/Ti Oxide BPSG W BPSG Sidewall Spacer Nitride n + TiSi 2 n + p-silicon n + Poly Gate 2006/9/

93 Silicon Nitride Applications PD Silicon Nitride PD Silicon Oxide IMD Seal Nitride M1 M2 FSG FSG FSG Cu Cu IMD Etch Stop Nitride PMD Barrier Nitride FSG PSG W PSG W n + n + STI USG p + p + P-Well N-Well Sidewall Spacer 2006/9/ Silicon Nitride Deposition Silane or DCS as silicon source NH 3 as nitrogen source N 2 as purge gas 3 SiH 2 Cl NH 3 Si 3 N HCl + 6 H 2 or 3 SiH NH 3 Si 3 N H /9/

94 Silicon Nitride LPCVD System Process Chamber Heaters Wafers Tower MFC MFC MFC MFC SiH 2 Cl 2 Process N 2 NH 3 Purge N 2 Control Valves Regulator Pump Burn Box Scrubbier 2006/9/ Exhaust Nitride Deposition Process Sequence Chamber Temperature Load Wafer Raise Tower Pump Down Temp. Stab. Pump Down Press. Stab. Si 3 N 4 Dep. Pump Down N 2 Vent Lower Tower Unload Wafer Wafer Temperature N 2 Flow NH 3 Flow DCS Flow Chamber Pressure Wafer Tower Position 2006/9/

95 Future Trends of HT-CVD More single wafer rapid thermal CVD Integrated processes in cluster tools 2006/9/ Summary of Furnace Deposition Polysilicon and silicon nitride are the two most commonly film deposited in high temperature furnace Silane and DCS are the two most commonly used silicon sources. Polysilicon can be doped while deposition by flowing phosphine, arsine or diborane 2006/9/

96 Rapid Thermal Process 2006/9/ Rapid Thermal Processing (RTP) Mainly used for post-implantation rapid thermal anneal (RTA) process. Fast temperature ramp-up, 100 to 150 C/sec compare with 15 C/min in horizontal furnace. Reduce thermal budge and easier process control. 2006/9/

97 Rapid Thermal Processing (RTP) Single wafer rapid thermal CVD (RTCVD) chamber can be used to deposit polysilicon and silicon nitride. RTCVD chamber can be integrated with other process chamber in a cluster tool for in-line process. Thin oxide layer (< 40 Å) is likely to be grown with RTO for WTW uniformity control. 2006/9/ Schematic of RTP Chamber Wafer External Chamber Process Gases Quartz Chamber Tungsten-Halogen Lamp IR Pyrometer 2006/9/

98 Lamp Array Bottom Lamps Top Lamps Wafer 2006/9/ RTP Chamber Photo courtesy of Applied Materials, Inc 2006/9/

99 Annealing and Dopant Diffusion At higher temperature >1100 C anneal is faster than diffusion Post implantation prefer high temperature and high temperature ramp rate. Single wafer rapid thermal process tool has been developed initially for this application 2006/9/ Annealing and Dopant Diffusion Dopant atoms diffuse at high temperature Furnace has low temperature ramp rate (~10 C/min) due to large thermal capacity Furnace annealing is a long process which causes more dopant diffusion Wafer at one end gets more anneal than wafer at another end 2006/9/

100 Anneal Rate and Diffusion Rate Anneal Rate Diffusion Rate Temperature 2006/9/ Dopant Diffusion After Anneal Gate RTA Furnace anneal 2006/9/

101 Advantage of RTP over Furnace Much faster ramp rate (75 to 150 C/sec) Higher temperature (up to 1200 C) Faster process Minimize the dopant diffusion Better control of thermal budget Better wafer to wafer uniformity control 2006/9/ RTP Temperature Change Load wafer Ramp up Anneal Cool down Unload wafer Temperature N 2 Flow Time 2006/9/

102 Thermal Nitridization Titanium PVD Thermal nitridization with NH 3 NH 3 + Ti TiN + 3/2 H /9/ Titanium Nitridization Ti SiO 2 Ti TiN SiO /9/

103 RTO Process Ultra thin silicon dioxide layer < 30Å Better WTW uniformity Better thermal budget control 2006/9/ RTP Process Diagram Load wafer Ramp up 1& 2 RTO RTA Cool down Unload wafer O 2 flow Temperature HCl flow N 2 flow Time 2006/9/

104 Future Tends in RTP In-situ process monitoring Cluster tools RTO, RTA and RTCVD applications RTCVD single-wafer chamber owns better control of thermal budget and WTW uniformity over LPCVD 2006/9/ RTCVD Chamber Lamp Housing Reactants Heating Lamps Wafer Reactants & byproducts Water Cooled Chamber Wall Quartz Window IR Pyrometer 2006/9/

105 Temperature of RTP & Furnace Temperature RTP Furnace Room Temp. Time 2006/9/ Cluster Tool RTO/RTP RTCVD -Si HF Vapor Clean Transfer Chamber Cool down Loading Station Unloading Station 2006/9/

106 Summary of RTP Fast thermal process but with low throughput Better process control Thermal budget Wafer to wafer uniformity Minimized dopant diffusion Cluster tool, easy process integration 2006/9/ Summary of Thermal Process Oxidation, diffusion, annealing, and CVD Wet oxidation is faster, dry oxidation has better film quality. For advanced fab mainly dry oxidation. Diffusion doping with oxide mask, used in lab LPCVD polysilicon and front-end silicon nitride Annealing recovers crystal and activates dopants RTP: better control, faster and less diffusion Furnaces: high throughput and low cost, will continue to be utilized in the future 2006/9/