STUDENT NAME and NUMBER: (PLEASE PRINT CLEARLY) Georgia Institute of Technology Department of Electrical and Computer Engineering.

Transcription

1 STUDENT NAME nd NUMBER: (PLEASE PRINT CLEARLY) Georgi Institute of Technology Deprtment of Electricl nd Computer Engineering Mrks: 2 /2 /2 DATE: Octoer 26, 2 Test #2 ECE23: Introduction to Computer Engineering 3 /2 4 /2 5 /2 Totl: / TIME: 4:35 p.m. - 5:55 p.m. REMARKS:. All questions should e nswered (in the spce provided). 2. Books nd notes my NOT e used, with the exception of one 8.5 x sheet of pper.. NUMBER SYSTEMS AND ARITHMETIC (MA MARK: 2) ) Represent the following numers in inry two s complement form using 5-its. = -8 = - = -7 = ) Add the following 5-it unsigned numers. Indicte if rnge overflow hs occured. Overflow yes or no? c) Add the following 5-it signed two s complement numers. Indicte if rnge overflow hs occured. Overflow yes or no? v.. - of 8 -

2 ECE23 Test #2 (continued) d) Find the diminished rdix complement of the following octl numer using 3 digits. (Hint: You cn pproch this using octl mth or y converting to inry, performing the pproprite complement, nd then converting ck to octl.) => 8 2. COMBINATIONAL BUILDING BLOCKS (MA MARK: 2) ) Someone hs mixed up the input columns of the truth tle for 4-to-2 priority encoder. List out the priority order for ech of the inputs In k from highest priority to lowest priority. Inputs In In In c In d Outputs Z Z Highest priority Lowest priority ) Implement the logic circuit for the following truth tle using 3-to-8 decoder nd miniml set of ny other simple gtes tht my e required (AND, OR, NAND, NOR, NOT). Inputs 2 Outputs Z Z v of 8 -

3 ECE23 Test #2 (continued) c) Implement the logic circuit for the following truth tle using n 8-to- multiplexer nd miniml set of other simple gtes tht my e required (AND, OR, NAND, NOR, NOT). Inputs 2 Output Z d) Slightly hrder thn the previous question, now implement the logic circuit for the sme truth tle using 4-to- multiplexer nd miniml set of other simple gtes tht my e required (AND, OR, NAND, NOR, NOT). Inputs 2 Output Z 3. LATCHES AND REGISTERS (MA MARK: 2) ) Descrie the differences etween level-sensitive (or level-triggered), positive edge-triggered, nd negtive edge-triggered devices. v of 8 -

4 ECE23 Test #2 (continued) ) Complete the elow timing digrm where is the output of trnsprent ltch, 2 the output of positive edge-triggered flip-flop, nd 3 the output of negtive edge-triggered flip-flop. These ll hve D s n input nd CLK s the enle signl. Assume the ltch nd flip-flops re initilly clered. CLK D 2 3 Trnsprent ltch output Positive edge-triggered flip-flop Negtive edge-triggered flip-flop c) Although we hve not studied the JK flip-flop s illustrted elow, it functions the sme s the SR flipflop except when the inputs re ll high, which is normlly indeterminte in n SR flip-flop. Fill in the two tles for the mrked points in the circuit digrm for the given vlues of (t). When (t) = J= Clk K= S C R c d S C R c d (t) When (t) = c d (t) d) Wht is the opertion eing performed y the ove JK flip-flop when the inputs re high? Wht type of cell is this similr too when the inputs re high? v of 8 -

5 ECE23 Test #2 (continued) 4. FINITE STATE MACHINES (MA MARK: 2) ) Develop the stte tle for the following stte digrm. / / Present Stte Input Next Stte Output S S / / / / / S 2 / S 3 ) With the following input strem, pply it to the previous stte mchine nd determine the output s well s the ending stte t the end of the input strem. Input = Output = Ending Stte = c) Is the ove stte mchine Mely mchine or Moore mchine. Justify your nswer! v of 8 -

6 ECE23 Test #2 (continued) v of 8 - d) A stte mchine is defined y the following stte tle. Drw the corresponding stte digrm where (S 2 S S ) = () is the initil stte. e) For the ove stte mchine, re there ny initil input comintions tht would mke it impossile to visit ll of the sttes? If so, for wht initil input comintion(s), nd which stte(s) would e missed? Present Stte Input Next Stte Output S 2 S S N 2 N N x w x y z w z x w w

7 ECE23 Test #2 (continued) 5. COUNTERS, SHIFT AND ROTATE REGISTERS (MA MARK: 2) ) Suppose you hve 4-it i-directionl shift register tht cn perform oth logicl nd two s complement rithmetic shifts. The contents of the shift register is initilly. When seril shift-in vlue is required, it is set to. The tle elow indictes wht type of shift opertion is performed t ech clock pulse. Complete the tle with how the contents of the shift register chnge t ech clock pulse. Clock Pulse # Shift Opertion Shift Register Contents ASL LSL LSL ASR ASR LSR ASR ASL ) Given the following 6-it counter, develop modulo-4 counter (divide y 4 counter) with miniml externl logic, ut, tht still includes the CE, CLEAR, φ, nd φ 2 inputs nd the z outputs. CE 6-it counter φ CLEAR z 5 z 4 z 3 z 2 z z φ 2 v of 8 -

8 ECE23 Test #2 (continued) c) Below is 4-it i-directionl shift register where ( x 3, x 2, x, x ) is prllel input, ( z 3, z 2, z, z ) is the contents of the register, x l nd x r re seril shift inputs for the left nd right shifting, respectively, nd ( c, c ) controls the shifting properties of the register. Given this 4-it i-directionl shift register tht cn perform logicl shifts, design new 4-it i-directionl shift register tht cn perform oth logic shifts nd two s complement rithmetic shifts using miniml externl logic. Include one extr input, W, tht indictes whether to perform logicl shift ( W = ) or n rithmetic shift ( W = ). x 3 x 2 x x W x l x r x 3 x 2 x x x l c 4-it idirectionl x r shift register c z 3 z 2 z z c c z 3 z 2 z z d) Given n 8-it ripple counter, how mny flip-flop vlues will e complemented to get the next count vlue if the following re the current counter contents (MSB on the left, LSB on the right). Current counter contents # of complements to next vlue v of 8 -