Instruction Set Architecture (ISA)

Transcription

1 Instruction Set Architecture (ISA) Department of Computer Science Faculty of Computer and Information Sciences Hosei University, Tokyo Japan yamin/ ISA p.1/28

2 Instruction Set Architecture A very important abstraction Interface between hardware and low-level software Standardizes instructions, machine language bit patterns, etc. Advantage: different implementations of the same architecture Disadvantage: sometimes prevents using new innovations ISA p.2/28

3 Modern Instruction Set Architectures Intel IA-32 (80x86/Pentium/Xeon) AIM PowerPC (Apple, IBM, and Motorola AIM) DEC/Compaq DEC Alpha SGI/MIPS MIPS (Microprocessor without Interlocked Pipeline Stages) SUN SPARC (Scalable Performance Architecture) HP HP-PA (Hewlett Packard Precision Architecture) ISA p.3/28

4 Intel 80x86 Registers Names EAX ECX EDX EBX ESP EBP ESI EDI EIP EFLAGS 31 0 CS SS DS ES FS GS Use GPR 0 GPR 1 GPR 2 GPR 3 GPR 4 GPR 5 GPR 6 GPR 7 Code segment pointer Stack segment pointer Data segment pointer 0 Data segment pointer 1 Data segment pointer 2 Data segment pointer 3 Instruction pointer (PC) Condition codes ISA p.4/28

5 Typical 80x86 Instruction Formats (1) JE EIP + displacement JE Condition Displacement (2) CALL 8 32 CALL Offset (3) MOV EBX, [EDI + 45] MOV d w r / m Displacement ISA p.5/28

6 Typical 80x86 Instruction Formats (4) PUSH ESI 5 3 PUSH Reg (5) ADD EAX, # ADD Reg w Immediate (6) TEST EDX, # TEST w r / m Immediate ISA p.6/28

7 Some Typical Operations on the 80x86 Arithmetic, Logical ADD, SUB Add/subtract (register-memory format) CMP Compare (register-memory format) SHL, SHR, RCR Shift left, shift right, rotate with carry condition code CBW Convert 8-bit data into 16-bit data (in EAX) TEST Logical AND and set condition codes INC, DEC Increments/decrements destination OR, XOR Logical OR, exclusive OR ISA p.7/28

8 Some Typical Operations on the 80x86 Control JNZ, JZ Conditional jump to EIP + 8-bit offset JMP Unconditional jump, 8-bit or 16-bit offset CALL Subroutine call, 18-bit offset, return address pushed onto stack RET Returns from subroutine: pops return address from stack and jumps to it LOOP Loop branch (decrement ECX), jump to EIP + 8-bit offset displacement if ECX 0 ISA p.8/28

9 Some Typical Operations on the 80x86 Data transfer MOV Move between two registers or between register and memory PUSH, POP Push data on stack or pop data from stack top to a register LES Load ES and one of the GPRs from memory String MOVS Copies from string source to destination LODS Loads a byte, word, or double word of a string into EAX ISA p.9/28

10 MIPS Instruction Format I-type instruction Opcode rs rt Immediate 6 bits 5 bits 5 bits 16 bits R-type instruction Opcode rs rt rd shamt func 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits J-type instruction Opcode Offset address to PC 6 bits 26 bits ISA p.10/28

11 Register File of the MIPS Processor Register name Number Usage $zero 0 constant 0 $at 1 reserved for assembler $v0 $v1 2 3 expression evaluation and results of a function $a0 $a3 4 7 arguments 1 3 $t0 $t temporary (not preserved across call) $s0 $s saved temporary (preserved across call) $t8 $t temporary (not preserved across call) $k0 $k reserved for OS kernel $gp 28 point to global area $sp 29 stack pointer $fp 30 frame point $ra 31 return address (used by function call) ISA p.11/28

12 Category of MIPS Instructions Arithmetic add, sub, addi, addu, mul, mulu, div, divu Logical and, or, andi, ori, sll, srl Data transfer lw, sw, lb, lbu, sb Conditional branch beq, bne, bnez, slt, slti, sltu, sltiu Unconditional jump j, jr, jal ISA p.12/28

13 MIPS Operations Data Transfers Instruction LB,LBU,SB LH,LHU,SH LW,LWU,SW LD,SD L.S,L.D,S.S,S.D MFC0,MTC0 MOV.S,MOV.D MFC1,MTC1 Instruction meaning Load byte, load byte unsigned, store byte Load half word, load half word unsigned, store half word Load word, Load word unsigned, store word Load double word, store double word Load SP, load DP, store SP, store DP Move from/to GPR to/from a special register Copy one SP or DP FP register to another FP register Copy 32 bits from/to FP registers to/from integer registers ISA p.13/28

14 MIPS Operations Arithmetic/Logical Operations Instruction DADD,DADDI,DADDU,DADDUI DSUB,DSUBU DMULT,DMULTU,DDIV,DDIVU MADD AND,ANDI OR,ORI,XOR,XORI LUI DSLL,DSRL,DSRA,DSLLV, DSRLV,DSRAV SLT,SLTI,SLTU,SLTIU Instruction meaning Add, add immediate; signed and unsigned Subtract signed and unsigned Multiply and divide; signed and unsigned Multiply-add And, and immediate Or, or imm., exclusive or, exclusive or imm. Load upper imm. bits 32 to 47 of reg. Sign ext. Shift: both imm. and variable form; shifts are left logical, right logical, right arithmetic Set less than; imm. signed and unsigned ISA p.14/28

15 MIPS Operations Control Transfers Instruction BEQZ,BNEZ BEQ,BNE BC1T,BC1F MOVN,MOVZ J,JR JAL,JALR TRAP ERET Instruction meaning Branch GPR equal/not equal to zero; 16-bit offset from PC+4 Branch GPR equal/not equal; 16-bit offset from PC+4 Test comparison bit in the FP status register and branch; 16-bit offset from PC+4 Copy GPR to another GPR if third GPR is negative, zero Jumps: 26-bit offset from PC+4 (J) or target in register (JR) Jump and link: save PC+4 in R31, target is PC-relative (JAL) or a register (JALR) Transfer to operating system at a vectored address Return to user code from an exception ISA p.15/28

16 MIPS Operations Floating Point Operations Instruction ADD.D,ADD.S,ADD.PS SUB.D,SUB.S,SUB.PS MUL.D,MUL.S,MUL.PS DIV.D,DIV.S,DIV.PS CVT._._ C..D,C..S Instruction meaning Add DP, SP numbers, and pairs of SP numbers Subtract DP, SP numbers, and pairs of SP numbers Multiply DP, SP numbers, and pairs of SP numbers Divide DP, SP numbers, and pairs of SP numbers CVT.x.y converts from type x to type y, where x and y are L (64-bit integer), W (64-bit integer), D (DP), or S (SP). Both operands are FPRs. DP and SP compares: =LT,GT,LE,GE,EQ,NE; sets bit in FP status register ISA p.16/28

17 MIPS Instruction Format (1) R-format add $1, $2, $3 # $1=$2+$3 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct ISA p.17/28

18 MIPS Instruction Format (2) I-format lw $1, 100($2) # $1=Memory[$2+100] 6-bit 5-bit 5-bit 16-bit op rs rt Address/Immediate ISA p.18/28

19 MIPS Instruction Format (3) J-format j # jump to bit op 26-bit Target address ISA p.19/28

20 MIPS Instruction Examples add $s1, $s2, $s3 # $s1=$s2+$s3 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct sub $s1, $s2, $s3 # $s1=$s2 $s3 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct ISA p.20/28

21 MIPS Instruction Examples and $s1, $s2, $s3 # $s1=$s2 AND $s3 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct or $s1, $s2, $s3 # $s1=$s2 OR $s3 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct ISA p.21/28

22 MIPS Instruction Examples addi $s1, $s2, 100 # $s1=$s bit 5-bit 5-bit 16-bit op rs rt Immediate andi $s1, $s2, 100 # $s1=$s2 AND bit 5-bit 5-bit 16-bit op rs rt Immediate ISA p.22/28

23 MIPS Instruction Examples ori $s1, $s2, 100 # $s1=$s2 OR bit 5-bit 5-bit 16-bit op rs rt Immediate sll $s1, $s2, 10 # $s1=shift($s2) left logical 10 bits 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct ISA p.23/28

24 MIPS Instruction Examples srl $s1, $s2, 10 #$s1=shift($s2) right logical 10 bits 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct lui $s1, 100 # $s1=100<<16 6-bit 5-bit 5-bit 16-bit op rs rt Immediate ISA p.24/28

25 MIPS Instruction Examples lw $s1, 100($s2) # $s1=memory[$s2+100] 6-bit 5-bit 5-bit 16-bit op rs rt Address sw $s1, 100($s2) # $Memory[$s2+100]=$s1 6-bit 5-bit 5-bit 16-bit op rs rt Address ISA p.25/28

26 MIPS Instruction Examples beq $s1, $s2, 25 # if $s1=$s2, goto PC+4+25*4 6-bit 5-bit 5-bit 16-bit op rs rt Address bne $s1, $s2, 25 # if $s1 $s2, goto PC+4+25*4 6-bit 5-bit 5-bit 16-bit op rs rt Address ISA p.26/28

27 MIPS Instruction Examples slt $s1, $s2, $s3 # if $s2<$s3, $s1=1; else $s1=0 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct j # jump to bit op 26-bit Target address ISA p.27/28

28 MIPS Instruction Examples jal # $31=PC+4; jump to bit op 26-bit Target address jr $ra # jump register $ra 6-bit 5-bit 5-bit 5-bit 5-bit 6-bit op rs rt rd shamt funct ISA p.28/28