Chapter 12 CPU Structure and Function

Transcription

1 Chapter 12 CPU Structure and Function

2 Contents Processor organization Register organization Instruction cycle Instruction pipelining Pentium processor PowerPC processor

3 12.1 Processor Organization Requirements on CPU Fetch instructions Interpret instructions Fetch data Process data Write data CPU consists of ALU Control unit Registers Internal bus

4 CPU With Systems Bus

5 CPU Internal Structure

6 12.2 Register Organization Design issues Completely GPRs vs specialized registers Specialized registers for particular operands + only BX, SI, and DI used for storing offset address in 80x86 + saving bits to represent them Specialization limits programmer s flexibility Number of registers For CISC, between 8 and 32 regarded as optimum + Fewer registers result in more memory references + More registers do not noticeably reduce memory references RISC uses hundreds of registers Register length Address register must be long enough to hold the target address Data register must be long enough to hold values of most data types + Some machine allow consecutive registers to hold double-length values

7 User Visible Registers GPR Data register Address register Segment pointers Index registers Stack pointer Condition codes(flags) Set according to the result of operations Used for checking certain condition Can be read (implicitly) by programs e.g. Jump if zero Can not (usually) be set by programs

8 Control & Status Registers Program Counter Updated after each instruction fetch Updated when branch instruction is met Instruction Register Memory Address Register Connected directly to address bus Memory Buffer Register Connected directly to data bus Program Status Word Sign, zero, carry, equal, overflow, interrupt enable/disable, supervisor mode Others Pointer to PCB (Process Control Block), Interrupt vector register Stack-related registers, Page table pointer

9 Supervisor Mode Intel microprocessor has 4 modes Ring zero Kernel functions Ring one Operating system functions Ring three User programs Ring two May be used for DBMS

10 Example Register Organizations Motorola 8 data registers MC68000 (Not including purly internal regs) Used primarily for data manipulation + 8-, 16-, and 32-bit operations are possible Also used as index registers 9 address registers 32-bit wide Includes two stack pointers + One for user and one for system PC and status register

11 Example Register Organizations Intel 8086 (Every register is special purpose) 4 16-bit data registers (can be used as general in some instructions) AX, BX, CX, DX 4 pointer and index registers SP, BP, SI, DI 4 segment registers CS, DS, SS, ES Instruction Pointer and flags

12 Example Register Organizations

13 12.3 Instruction Cycle Subcycles of instruction cycle Fetch Execute Interrupt Indirect(Newly added) Indirect cycle Indirect addressing requires additional memory access Can be thought of as additional instruction subcycle

14 Instruction Cycle State Diagram

15 Data Flow Fetch cycle PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1

16 Data Flow, Fetch Cycle

17 Data Flow Indirect cycle IR is examined If indirect addressing, indirect cycle is performed Right most N bits of MBR transferred to MAR Control unit requests memory read Result (address of operand) moved to MBR

18 Data Flow, Indirect Cycle

19 Data Flow Execute cycle May take many forms depending on instructions May include Memory read/write Input/Output Register transfers ALU operations

20 Data Flow Interrupt cycle Current PC saved to allow resumption after interrupt Contents of PC copied to MBR Special memory location (e.g. stack pointer) loaded to MAR MBR written to memory PC loaded with address of interrupt handling routine Next instruction (first of interrupt handler) can be fetched

21 Data Flow, Interrupt Cycle

22 12.4 Instruction Pipelining Pipelining strategy Similar to an assembly line in automobile factory Instruction has a number of stages Stages can be executed simultaneously Simple two-stage pipelining Fetch and execute stages If two stages were of equal duration, instruction cycle time would be halved But things are not that easy Execution time is longer than fetch time + Fetch stage may have to wait Conditional branch makes the next instruction unknown + Fetch stage wait or guess the branch

23 Two Stage Instruction Pipeline

24 Instruction Pipelining More stages mean further speedup Fetch Instruction(FI) Decode Instruction(DI) Calculate Operands (CO) Fetch Operands(FO) Execute Instructions(EI) Write Operand(WO) Characteristics(Equal duration assumed) Reduced execution time for 9 inst. from 54 to 14 Some instructions may not go through all 6 stages LOAD does not need WO stage Some stages may not be performed in parallel FI, FO, and WO stages involve a memory access

25 Timing Diagram for Instruction Pipeline Operation

26 Instruction Pipelining Factors that limit performance enhancement Stages may not be of equal duration Conditional branch instruction Invalidate several instruction fetches Interrupt Data dependency CO stage may depend on the contents of a register that could be altered by a previous instruction that is still in pipeline System need to contain logic to solve this conflict

27 Effect of a Conditional Branch

28 FI Fetch Instruction DI Decode Instruction CO Calculate Operands Yes Unconditional Branch? No FO Fetch Operands EI Execute Instruction Update PC WO Write Operands Empty Pipe Yes Branch or Inter -rupt? No Figure Six-Stage Instruction Pipeline

29 FI DI CO FO EI WO FI DI CO FO EI WO 1 I1 1 I1 2 I2 I1 2 I2 I1 3 I3 I2 I1 3 I3 I2 I1 4 I4 I3 I2 I1 4 I4 I3 I2 I1 5 I5 I4 I3 I2 I1 5 I5 I4 I3 I2 I1 6 I6 I5 I4 I3 I2 I1 6 I6 I5 I4 I3 I2 I1 Time 7 I7 I6 I5 I4 I3 I2 7 I7 I6 I5 I4 I3 I2 8 I8 I7 I6 I5 I4 I3 8 I15 I3 9 I9 I8 I7 I6 I5 I4 9 I16 I15 10 I9 I8 I7 I6 I5 10 I16 I15 11 I9 I8 I7 I6 11 I16 I15 12 I9 I8 I7 12 I16 I15 13 I9 I8 13 I16 I15 14 I9 14 I16 (a) No branches (b) With conditional branch Figure An Alternative Pipeline Depiction

30 Pipeline Performance Measures of performance Cycle time can be determined as τ = max[τ i ] + d = τ m + d 1 <= i <= k where τ m = maximum stage delay k = number of stages in the instruction pipeline d = time delay of a latch, needed to advance signals and data from one stage to the next We can ignore d since τ m >> d Total time T k to execute n instructions is T k = [k + (n - 1)]τ Thus speedup factor is defined as S k = T 1 /T k = nkτ /[k +(n - 1)]τ = nk/ [k +(n - 1)]

31 Speedup Factors with Pipelining

32 Speedup Factors with Pipelining

33 Dealing with Branches Approaches for dealing with branches Multiple streams Prefetch branch target Loop buffer Branch prediction Delayed branch Multiple streams Have two pipelines Prefetch each branch into a separate pipeline Use appropriate pipeline Problems There may be contention delays for accessing data Additional branch instruction needs an additional stream

34 Dealing with Branches Prefetch branch target Target of branch is prefetched in addition to the instruction following branch Keep target until branch is executed Used in IBM 360/91 Loop buffer Contains n most recently fetched instructions, in sequence Whenever a branch is to be taken, buffer is checked Well suited to dealing with loops If loop buffer is large enough to contain all the instructions in a loop, we need to fetch them only once Used in CDC and CRAY-1

35 Loop Buffer Diagram

36 Dealing with Branches Branch prediction Predict never taken Predict always taken Predict by opcode Taken/not taken switch Branch history table Predict never taken Assume that jump will not happen Always fetch next instruction Used in MC68020 & VAX 11/780 VAX will not prefetch the instruction after branch if a page fault would result

37 Dealing with Branches Predict always taken Assume that jump will happen Always fetch target instruction Studies show that conditional branches are taken more than 50% But prefetching the branch target is more likely to cause a page fault Predict by opcode Some instructions are more likely to result in a jump than others JNZ of 80x86 Success rates of >75% are reported

38 Dealing with Branches Taken/Not taken switch Based on previous history History bits are associated with each conditional branch instruction Single bit switch Record whether the last execution resulted in a branch or not Not good for the nested loop case Two bit switch Two consecutive wrong predictions change the prediction Drawback If the decision is to take the branch, target instruction cannot be fetched until the target address is decoded

39 Read next conditional branch instr Read next conditional branch instr Predict taken Predict not taken Yes Branch taken? No Branch taken? No Yes Read next conditional branch instr Read next conditional branch instr Predict taken Predict not taken Yes Branch taken? No No Branch taken? Yes Figure Branch Prediction Flow Chart

40 Branch Prediction State Diagram

41 Dealing with Branches Branch history table Each entry consists of the address of a branch instruction, history bits, and information about the target instruction Used in AMD29000 microprocessor

42 Dealing with Branches

43 Dealing with Branches

44 Dealing with Branches Delayed Branch Do not take jump until you have to Rearrange instructions To improve pipeline performance, rearrange instructions so that branch instructions occur later than actually desired

45 Intel Pipelining Fetch From cache or external memory Put in one of two 16-byte prefetch buffers Fill buffer with new data as soon as old data consumed Average 5 instructions fetched per 16-byte load Independent of other stages to keep buffers full Decode stage 1 Opcode & address-mode info is decoded Required information is in at most first 3 bytes of instruction Can direct D2 stage to get rest of instruction Decode stage 2 Expand opcode into control signals Computation of complex address modes Execute ALU operations, cache access, register update Write back Update registers & flags Results sent to cache & bus interface write buffers

46 Pentium Instruction Formats

47 12.5 Pentium Processor Register organization General : EAX ~ EDX, ESP, EBP, ESI, and EDI Segment : CS, SS, DS, ES, FS, and GS Flags(EFLAGS) : condition codes and mode bits Instruction pointer Registers for floating-point unit Numeric + Register for holding 80-bit floating-point number Control Status + 16-bit register reflecting the state of floating-point unit Tag word + 2 bits associated with each numeric register + Represents valid, zero, special(nan, infinity..), and empty

48 Pentium 4 Registers

49 Pentium 4 Registers

50 EFLAGS Register Condition codes and control bits Carry, parity, auxiliary, zero, sign, and overflow Trap flag(tf) Causes an interrupt after each instruction execution Interrupt enable flag(if) Direction flag(df) I/O privilege flag(iopl) Causes CPU to generate an exception on all accesses to I/O devices Resume flag(rf) Used for debugging Alignment check(ac) Identification flag(id) Provides information about vendor, family, and model

51 EFLAGS Register

52 Control Registers 4 32-bit control registers(cr0 ~ CR4) CR0 Protection enable(pe) Monitor coprocessor(mp) Emulation(EM) + Set when CPU does not have floating-point unit Task switched(ts) Extension type(et) Numeric error(ne) Write protect(wp) Alignment mask(am) Not write through(nw) + Selects mode of operation of data cache Cache disable(cd) Paging(PG)

53 Control Registers 4 32-bit control registers(cr0 ~ CR4) CR2 CR3 CR4 Holds 32-bit linear address of the last page accessed before a page fault Leftmost 20 bits for the 20 most significant bits of the base address of the page directory Additional control bits

54 Control Registers

55 MMX Register Mapping MMX uses 64 bit data types Each instruction use 3 bit register address fields 8 MMX registers No MMX specific registers Aliasing to lower 64 bits of existing 8 floating point registers

56 Mapping of MMX Registers to FP Registers

57 Pentium Interrupt Processing Interrupts Maskable : Received on INTR pin Nonmaskable : Received on NMI pin Exceptions Processor detected Programmed : Instructions that generate exception Interrupt vector table Each interrupt type assigned a number Index into the interrupt vector table 256 * 32 bit interrupt vectors

58 Pentium Interrupts and Exceptions

59 Pentium Interrupt Processing 5 priority classes Class 1 (1) Traps on the previous instruction Class 2 (2, ) External interrupts Class 3 (3, 14) Faults from fetching next instruction Class 4 (6, 7) Faults from decoding next instruction Class 5 (0, 4, 5, 8, 10-14, 16, 17) Faults on executing an instruction

60 Pentium Interrupt Processing Interrupt handling If the transfer involves a change of privilege level, SS and ESP are pushed onto the stack EFLAGS is pushed IF and TF flags are cleared CS and EIP are pushed If error code is accompanied, it is pushed CS and EIP of interrupt service routine are fetched to be executed To return from interrupt, IRET instruction is executed

61 12.6 PowerPC Processor Register organization Fixed-point unit General : bit GPRs Exception register(xer) : Used to report exceptions Floating-point unit General : bit GPRs Floating-point status and control register(fpscr) + Used to control the operation and to record status Branch processing unit Condition register : 8 4-bit condition code fields Link register + Used for indirect addressing of the target address Count register + Used to control an iteration loop

62 PowerPC User Visible Registers

63 PowerPC Interrupt Processing Types of interrupts Machine state registers Interrupt handling Place the address of next instruction in SRR0 MSR is copied into SRR1 MSR is set according to interrupt type Control is transferred to interrupt handler To return from interrupt, rfi instruction is executed

64 PowerPC Interrupt Table

65 PowerPC Interrupt Table(Cont d)

66 PowerPC MSR