William Stallings Computer Organization and Architecture

Transcription

1 William Stallings Computer Organization and Architecture Chapter 14 Unit Operations Rev ( ) by Enrico Nardelli

2 Execution of the Instruction Cycle It has many elementary phases, each executed in a single clock cycle (remember pipelining) In each phase only very simple operations (called micro-operations) are executed: Move contents between registers (internals, interface with ALU, interface with memory) Activate devices (ALU, memory) Micro-operations are the CPU atomic operations, hence define its low-level behaviour A micro-operation is the set of actions (data flows and controls) that can be completed in a single clock cycle Rev ( ) by Enrico Nardelli 14-2

3 Constituent Elements of Program Execution Rev ( ) by Enrico Nardelli 14-3

4 Sequence of micro-operations for instruction fetch t 1 : MAR <- (PC) <DF 1 > t 2 : MBR <- (memory) <DF 2 DF 3 DF 4 DF 5 > PC <- (PC) +1 <DF 7 > t 3 : IR <- (MBR) <DF 6 > CPU (each t i is a clock cycle, 1 2 PC MAR i.e. an atomic time unit) An alternative organization 7 3 Unit t 1 : MAR <- (PC) 6 5 t 2 : MBR <- (memory) IR MBR t 3 : PC <- (PC) +1 MAR = Memory Address Register Address MBR = Memory Buffer Register IR = Instruction Register IR <- (MBR) PC = Program Counter Data Memory Rev ( ) by Enrico Nardelli 14-4

5 Rules for micro-operation sequencing Proper precedence must be observed MAR <- (PC) must precede MBR <- (memory) Conflicts must be avoided Must not read & write same register at same time MBR <- (memory) & IR <- (MBR) must not be in same cycle Also: PC <- (PC) +1 involves addition Depending on the kind of ALU may need additional micro-operations, hence it may be better to have it in t 2 Minimization of the number of micro-operations is an algorithmic problem on graphs Rev ( ) by Enrico Nardelli 14-5

6 Sequence of micro-operations for direct addressing t 1 : MAR <- (IR) <DF 1 > t 2 : MBR <- (memory) <DF 2 DF 3 DF 4 DF 5 > CPU 3 MAR Memory 1 Unit 3 IR MBR 5 MAR = Memory Address Register MBR = Memory Buffer Register IR = Instruction Register PC = Program Counter Address Data Rev ( ) by Enrico Nardelli 14-6

7 Sequence of micro-operations for register indirect addressing t 1 : MAR <- ((IR register-address )) <DF 1 DF 2 > t 2 : MBR <- (memory) <DF 3 DF 4 DF 5 DF 6 > CPU 4 2 MAR Memory Registers 1 Unit 4 1 IR MBR 6 MAR = Memory Address Register MBR = Memory Buffer Register IR = Instruction Register PC = Program Counter Address Data Rev ( ) by Enrico Nardelli 14-7

8 Sequence of micro-operations for indirect addressing t 1 : MAR <- (IR address ) <DF 1 > t 2 : MBR <- (memory) <DF 2 DF 3 DF 4 DF 5 > t 3 : MAR <- (MBR) <DF 6 > t 4 : MBR <- (memory) <DF 7 DF 8 DF 9 DF 10 > CPU 3-8 MAR Memory 1 6 Unit 3-8 IR MBR 5-10 MAR = Memory Address Register MBR = Memory Buffer Register IR = Instruction Register PC = Program Counter Address Data Rev ( ) by Enrico Nardelli 14-8

9 Sequence of micro-operations for relative addressing t 1 : MAR <- (IR) + (PC) <DF 1 DF 2 DF 3 DF 4 > t 2 : MBR <- (memory) <DF 5 DF 6 DF 7 DF 8 > CPU 6 PC 2 ALU 4 MAR Memory 3 Unit 6 1 IR MBR 8 MAR = Memory Address Register MBR = Memory Buffer Register IR = Instruction Register PC = Program Counter ALU = Arithmetic Logic Unit Address Data Rev ( ) by Enrico Nardelli 14-9

10 Sequence of micro-operations for base and indexed addressing t 1 : MAR <- ((IR register-address )) + (IR address ) <DF 1 DF 2 DF 3 DF 4 DF 5 > t 2 : MBR <- (memory) <DF 6 DF 7 DF 8 DF 9 > 3 ALU Registers IR 2 1 CPU MAR Unit MBR Memory MAR = Memory Address Register MBR = Memory Buffer Register IR = Instruction Register PC = Program Counter ALU = Arithmetic Logic Unit Address Data Rev ( ) by Enrico Nardelli 14-10

11 Sequence of micro-operations for combination of displacement and indirect addressing Try them yourself! Rev ( ) by Enrico Nardelli 14-11

12 Sequence of micro-operations for interrupt handling t 1 : MBR <- (PC) <DF 1a > MAR <- (Stack-Pointer) <DF 1b > t 2 : Memory <- (MBR) <DF 1c DF 1d DF 1e > t 3 : MAR <- Interrupt_Code <DF 2a > t 4 : MBR <- (Memory) <DF 2b DF 2c DF 2d DF 2e > t 5 : PC <- (MBR) <DF 2f > CPU 1d - 2c 1b Registers 1b MAR 2a Unit 1c - 2b 1d - 2c 2d 1e 1e - 2d Memory 2f 2e PC MBR 1a 1c MAR = Memory Address Register Rev ( ) by Enrico Nardelli Address Data MBR = Memory Buffer Register IR = Instruction Register PC = Program Counter

13 Micro-operation sequencing for the execution phase (1) Different for each instruction MUL R1 X - multiply the contents of location X to Register 1 and store result in Register 1 and 2 Assuming that content of cell at address X is in MBR after the operand fetch phase: t 1 : t 2 : ALU <- (R1) * (MBR) R1 <- (ALU) low R2 <- (ALU) high Rev ( ) by Enrico Nardelli 14-13

14 Micro-operation sequencing for the execution phase (2) ISZ X - increment memory cell X and skip if it s zero Assuming that content of cell at address X is in MBR after the operand fetch phase: t 1 : MBR <- (MBR) + 1 t 2 : Note: memory <- (MBR) IF (MBR) == 0 THEN PC <- (PC) + 1 IF-THEN is a single micro-operation Rev ( ) by Enrico Nardelli 14-14

15 Micro-operation sequencing for the execution phase (3) PPJ X - Save in stack the return address and jump to address X t 1 : t 2 : MBR <- (PC) MAR <- (SP) memory <- (MBR) SP <- (SP) + 1 PC <- (IR address ) Rev ( ) by Enrico Nardelli 14-15

16 A simplified flow diagram for the execution of instruction cycle ICC = Instruction Cycle Code 11 (Interrupt) 00 (Fetch) ICC? Execute interrupt handling micro-ops ICC = (Execution) Opcode? Execute micro-ops for the given opcode 01 (Indirect Addressing) Execute indirect addressing micro-ops ICC = 10 No Fetch instruction Indirect addressing? Yes Interrupt enabled? Fetch data ICC = 01 ICC = 11 ICC = 00 ICC = 10 Rev ( ) by Enrico Nardelli 14-16

17 Functions of Unit Sequencing Causing the CPU to step through a series of microoperations Execution Causing the execution of each micro-op ALL THESE ACTIONS are performed by means of Signals Rev ( ) by Enrico Nardelli 14-17

18 A simplified data flow diagram of a Unit Instruction Register Flags Unit Signals internal to CPU Signals Clock Signals Rev ( ) by Enrico Nardelli 14-18

19 Input Signals Clock One micro-op (or set of parallel ops) per clock cycle Different signals are needed for different steps Instruction register Op-code for current instruction Determines which micro-instructions are performed Flags State of CPU Results of previous operations Interrupts Acknowledgments Rev ( ) by Enrico Nardelli 14-19

20 Output Signals To other CPU components For data movement To activate specific functions To the To control memory To control I/O modules Output signals from the control unit make all micro-operations happen Rev ( ) by Enrico Nardelli 14-20

21 Example of Signal use in a simplified schema of a CPU C5 C12 M B R C8 C1 C3 C4 C10 C15 C11 AC PC C13 IR C6 C7 C9 C2 C14 C16 Decod. Cx C0 M A R The flow of data is enabled when the Signal x is enabled Flags Unit signals Cx Clock ALU signals Cx Rev ( ) by Enrico Nardelli 14-21

22 Example of Signal Sequence Instruction Fetch (1) t 1 : MAR <- (PC) unit (CU) activates signal C2 to open gate between PC and MAR t 2 : MBR <- (memory) CU activates C0 to open gate between MAR and address bus CU activates the memory read control signal (CR - not shown) to the memory CU activates C5 to open gate between data bus and MBR Rev ( ) by Enrico Nardelli 14-22

23 Example of Signal Sequence Instruction Fetch (2) t 3 : PC <- (PC) +1 In the simple schema shown there is no direct data path from ALU to PC hence the micro-op has to be split in two (ALU has internally an output buffer to store result): t 3-1 : ALU <- (PC) increment ALU t 3-2 : AC <- (ALU) CU activates C14 CU act. control signal CA (not shown) for ALU CU activates C9 PC <- (AC) CU activates C15 t 4 : IR <- (MBR) CU activates C4 Rev ( ) by Enrico Nardelli 14-23

24 Example of Signal Sequence Instruction Fetch (3) Optimization t 2 and t 3-1 can be executed together t 3-2 and t 4 can be executer together New organization t 1 : MAR <- (PC) C2 t 2 : MBR <- (memory) C0 CR C5 (PC)+1 in ALU C14 CA t 3 : AC <- (ALU) C9 PC <- (AC) C15 IR <- (MBR) C4 Rev ( ) by Enrico Nardelli 14-24

25 Example of Signal Sequence - Indirect Addressing t 1 : MAR <- (IR address ) CU activates C16 to open gate between IR and MAR t 2 : MBR <- (memory) CU act. C0 to open gate between MAR and address bus CU act. the memory read control signal (CR) CU act. C5 to open gate between data bus and MBR t 3 : MAR <- (MBR) CU activates C8 to open gate between MBR and MAR t 4 : MBR <- (memory) CU activates C0, CR and C5 as above Rev ( ) by Enrico Nardelli 14-25

26 Other Examples of Signal Sequence Direct Addressing Relative Addressing Try them yourself! Rev ( ) by Enrico Nardelli 14-26

27 Limitations The simplified schema of a CPU s does not show registers, hence we cannot show Register addressing Register indirect addressing Base addressing Indexed addressing Combination of displacement and indirect addressing Try adding to the simplified schema one or more of the above addressing modalities and derive the required micro-operations! Rev ( ) by Enrico Nardelli 14-27

28 Internal Organization of CPU Usually a single internal bus less complex then having direct data paths between registers and ALU Gates control movement of data onto and off the internal bus signals control also data transfer to and from external systems bus Temporary registers in input to ALU are now needed for proper operation of ALU Rev ( ) by Enrico Nardelli 14-28

29 Hardwired Implementation (1) Consider the control unit as a combinational circuit Outputs of the circuit are the control signals Inputs of the circuit are status signal for ICC and opcode bits For each configuration of inputs produce a proper output That is, the activation of a given control signal Cn has to happen when this condition is true OR this condition is true OR Rev ( ) by Enrico Nardelli 14-29

30 Hardwired Implementation (2) Example: signals P and Q code ICC: then fetch is coded by P Q, indirect by P Q, execute by PQ, and interrupt by PQ Opcode bits are further control signals Boolean expression activating C5 in the simplified schema of a CPU: C5 = P Q t 2 + P Q(t 2 + t 4 ) + PQ B where B is the boolean expression representing, for all opcodes activating C5, all micro-operations actually activating it E.g.: if C5 is activated by opcode 3 during t 2 and t 4 and by opcode 7 during t 3 and t 4 then B is: OC3(t 2 +t 4 )+OC7(t 3 +t 4 ) Rev ( ) by Enrico Nardelli 14-30

31 A simplified data flow diagram of a Unit for the hardwired implementation Instruction Register OC 1 Decoder OC m Clock Flags clocks for mops t 1 t n Unit Signals internal to CPU Signals Signals Rev ( ) by Enrico Nardelli 14-31

32 Problems with the Hardwired Implementation Complex sequencing & micro-operation logic Difficult to design and test Inflexible design Difficult to add new instruction Rev ( ) by Enrico Nardelli 14-32