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8 CD4047BM CD4047BC Low Power Monostable Astable Multivibrator General Description CD4047B is capable of operating in either the monostable or astable mode It requires an external capacitor (between pins 1 and 3) and an external resistor (between pins 2 and 3) to determine the output pulse width in the monostable mode and the output frequency in the astable mode Astable operation is enabled by a high level on the astable input or low level on the astable input The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components A frequency twice that of Q is available at the Oscillator Output a 50% duty cycle is not guaranteed Monostable operation is obtained when the device is triggered by low-to-high transition at a trigger input or high-tolow transition at b trigger input The device can be retriggered by applying a simultaneous low-to-high transition to both the a trigger and retrigger inputs A high level on Reset input resets the outputs Q to low Q to high Features Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS SPECIAL FEATURES Low power consumption special CMOS oscillator configuration Monostable (one-shot) or astable (free-running) operation True and complemented buffered outputs Only one external R and C required Block and Connection Diagrams October 1993 MONOSTABLE MULTIVIBRATOR FEATURES Positive- or negative-edge trigger Output pulse width independent of trigger pulse duration Retriggerable option for pulse width expansion Long pulse widths possible using small RC components by means of external counter provision Fast recovery time essentially independent of pulse width Pulse-width accuracy maintained at duty cycles approaching 100% ASTABLE MULTIVIBRATOR FEATURES Free-running or gatable operating modes 50% duty cycle Oscillator output available Good astable frequency stability typical e g2% a 0 03% C 100 khz frequency e g0 5% a 0 015% C 10 khz deviation (circuits trimmed to frequency V DD e 10V g10%) Applications Frequency discriminators Timing circuits Time-delay applications Envelope detection Frequency multiplication Frequency division Dual-In-Line Package CD4047BM CD4047BC Low Power Monostable Astable Multivibrator TL F TL F Top View Order Number CD4047B C1995 National Semiconductor Corporation TL F 5969 RRD-B30M105 Printed in U S A

9 Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications DC Supply Voltage (V DD ) b0 5V to a18v DC Input Voltage (V IN ) b0 5V to V DD a0 5V DC Storage Temperature Range (T S ) b65 Ctoa150 C Power Dissipation (P D ) Dual-In-Line 700 mw Small Outline 500 mw Lead Temperature (T L ) (Soldering 10 seconds) 260 C Recommended Operating Conditions (Note 2) DC Supply Voltage (V DD ) Input Voltage (V IN ) Operating Temperature Range (T A ) CD4047BM CD4047BC 3Vto15V DC 0 to V DD V DC b55 Ctoa125 C b40 Ctoa85 C DC Electrical Characteristics CD4047BM (Note 2) Symbol Parameter Conditions b55 C 25 C 125 C Min Max Min Typ Max Min Max I DD Quiescent Device Current V DD e 5V ma V DD e 10V ma V DD e 15V ma V OL Low Level Output Voltage li Ol k 1 ma V DD e 5V V V DD e 10V V V DD e 15V V V OH High Level Output Voltage li Ol k 1 ma V DD e 5V V V DD e 10V V V DD e 15V V V IL Low Level Input Voltage V DD e 5V V O e 0 5V or 4 5V V V DD e 10V V O e 1V or 9V V V DD e 15V V O e 1 5V or 13 5V V V IH High Level Input Voltage V DD e 5V V O e 0 5V or 4 5V V V DD e 10V V O e 1V or 9V V V DD e 15V V O e 1 5V or 13 5V V I OL Low Level Output Current V DD e 5V V O e 0 4V ma (Note 3) V DD e 10V V O e 0 5V ma V DD e 15V V O e 1 5V ma I OH High Level Output Current V DD e 5V V O e 4 6V b0 64 b0 51 b0 88 b0 36 ma (Note 3) V DD e 10V V O e 9 5V b1 6 b1 3 b2 25 b0 9 ma V DD e 15V V O e 13 5V b4 2 b3 4 b8 8 b2 4 ma I IN Input Current V DD e 15V V IN e 0V b0 1 b10b5 b0 1 b1 0 ma V DD e 15V V IN e 15V b ma DC Electrical Characteristics CD4047BC (Note 2) Symbol Parameter Conditions b40 C 25 C 85 C Min Max Min Typ Max Min Max I DD Quiescent Device Current V DD e 5V ma V DD e 10V ma V DD e 15V ma V OL Low Level Output Voltage li Ol k 1 ma V DD e 5V V V DD e 10V V V DD e 15V V V OH High Level Output Voltage li Ol k 1 ma V DD e 5V V V DD e 10V V V DD e 15V V Units Units 2

10 DC Electrical Characteristics CD4047BC (Note 2) (Continued) Symbol Parameter Conditions b40 C 25 C 85 C Min Max Min Typ Max Min Max V IL Low Level Input Voltage V DD e 5V V O e 0 5V or 4 5V V V DD e 10V V O e 1V or 9V V V DD e 15V V O e 1 5V or 13 5V V V IH High Level Input Voltage V DD e 5V V O e 0 5V or 4 5V V V DD e 10V V O e 1V or 9V V V DD e 15V V O e 1 5V or 13 5V V I OL Low Level Output Current V DD e 5V V O e 0 4V ma (Note 3) V DD e 10V V O e 0 5V ma V DD e 15V V O e 1 5V ma I OH High Level Output Current V DD e 5V V O e 4 6V b0 52 b0 44 b0 88 b0 36 ma (Note 3) V DD e 10V V O e 9 5V b1 3 b1 1 b2 25 b0 9 ma V DD e 15V V O e 13 5V b3 6 b3 0 b8 8 b2 4 ma I IN Input Current V DD e 15V V IN e 0V b0 3 b10b5 b0 3 b1 0 ma V DD e 15V V IN e 15V b ma Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices should be operated at these limits The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device oepration Note 2 V SS e 0V unless otherwise specified Note 3 I OH and I OL are tested one output at a time AC Electrical Characteristics CD4047B T A e 25 C C L e 50 pf R L e 200k input t r e t f e 20 ns unless otherwise specified Symbol Parameter Conditions Min Typ Max Units t PHL t PLH Propagation Delay Time Astable V DD e 5V ns Astable to Osc Out V DD e 10V ns V DD e 15V ns t PHL t PLH Astable Astable to Q Q V DD e 5V ns V DD e 10V ns V DD e 15V ns t PHL t PLH a Trigger b Trigger to Q V DD e 5V ns V DD e 10V ns V DD e 15V ns t PHL t PLH a Trigger Retrigger to Q V DD e 5V ns V DD e 10V ns V DD e 15V ns t PHL t PLH Reset to Q Q V DD e 5V ns V DD e 10V ns V DD e 15V ns t THL t TLH Transition Time Q Q Osc Out V DD e 5V ns V DD e 10V ns V DD e 15V ns t WL t WH Minimum Input Pulse Duration Any Input V DD e 5V ns V DD e 10V ns V DD e 15V ns t RCL t FCL a Trigger Retrigger Rise and V DD e 5V 15 ms Fall Time V DD e 10V 5 ms V DD e 15V 5 ms C IN Average Input Capacitance Any Input pf AC Parameters are guaranteed by DC correlated testing Units 3

11 Logic Diagram Special input protection circuit to permit larger input-voltage swings Truth Table Function Terminal Connections Output Pulse Input Pulse From To V DD To V SS To TL F Typical Output Period or Pulse Width Astable Multivibrator Free-Running t A (10 11) e 4 40 RC True Gating Complement Gating t A (13) e 2 20 RC Monostable Multivibrator Positive-Edge Trigger Negative-Edge Trigger t M (10 11) e 2 48 RC Retriggerable External Countdown (See Figure) (See Figure) (See Figure) Note External resistor between terminals 2 and 3 External capacitor between terminals 1 and 3 Typical Implementation of External Countdown Option t EXT e (N b 1) t A a (t M a t A 2) TL F

12 Typical Performance Characteristics Typical Q Q Osc Out Period Accuracy vs Supply Voltage (Astable Mode Operation) Typical Q Q Pulse Width Accuracy vs Supply Voltage Monostable Mode Operation TL F f Q Q R C A 1000 khz 22k 10 pf B 100 khz 22k 100 pf C 10 khz 220k 100 pf D 1 khz 220k 1000 pf E 100 Hz 2 2M 1000 pf TL F t M R C A 2 ms 22k 10 pf B 7 ms 22k 100 pf C 60 ms 220k 100 pf D 550 ms 220k 1000 pf E 5 5 ms 2 2M 1000 pf Typical Q Q and Osc Out Period Accuracy vs Temperature Astable Mode Operation Typical Q and Q Pulse Width Accuracy vs Temperature Monostable Mode Operation TL F f Q Q R C A 1000 khz 22k 10 pf B 100 khz 22k 100 pf C 10 khz 220k 100 pf D 1 khz 220k 1000 pf Timing Diagram Astable Mode TL F t M R C A 2 ms 22k 10 pf B 7 ms 22k 100 pf C 60 ms 220k 100 pf D 550 ms 220k 1000 pf Monostable Mode TL F TL F Retrigger Mode TL F

13 CD4047BM CD4047BC Low Power Monostable Astable Multivibrator Physical Dimensions inches (millimeters) LIFE SUPPORT POLIC Order Number CD4047BMJ or CD4047BCJ NS Package Number J14A Order Number CD4047BMN or CD4047BCN NS Package Number N14A NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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15 MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator General Description The MM54 74HC123A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits Connection Diagram Dual-In-Line Package TL F Top View Order Number MM54HC123A or MM74HC123A Truth Table Inputs Outputs Clear A B Q Q L X X L H X H X L H X X L L H H L u H v H u L H January 1988 Each multivibrator features both a negative A and a positive B transition triggered input either of which can be used as an inhibit input Also included is a clear input that when taken low resets the one shot The HC123 can be triggered on the positive transition of the clear while A is held low and B is held high The HC123A is retriggerable That is it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extended Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques The output pulse equation is simply PWe(R EXT )(C EXT ) where PW is in seconds R is in ohms and C is in farads All inputs are protected from damage due to static discharge by diodes to V CC and ground Features Typical propagation delay 25 ns Wide power supply range 2V 6V Low quiescent current 80 ma maximum (74HC Series) Low input current 1 ma maximum Fanout of 10 LS-TTL loads Simple pulse width formula T e RC Wide pulse range 400 ns to % (typ) Part to part variation g5% (typ) Schmitt Trigger A Binputs enable infinite signal input rise and fall times Timing Component H e High Level L e Low Level TL F u e Transition from Low to High v e Transition from High to Low e One High Level Pulse e One Low Level Pulse X e Irrelevant Note Pin 6 and Pin 14 must be hard-wired to GND MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator C1995 National Semiconductor Corporation TL F 5206 RRD-B30M105 Printed in U S A

16 Absolute Maximum Ratings (Notes1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (V CC ) b0 5V to a7 0V DC Input Voltage (V IN ) b1 5V to V CC a1 5V DC Output Voltage (V OUT ) b0 5V to V CC a0 5V Clamp Diode Current (I IK I OK ) g20 ma DC Output Current per pin (I OUT ) g25 ma DC V CC or GND Current per pin (I CC ) g50 ma Storage Temperature Range (T STG ) b65 Ctoa150 C Power Dissipation (P D ) (Note 3) 600 mw S O Package only 500 mw Lead Temperature (T L ) (Soldering 10 seconds) 260 C Operating Conditions Min Max Units Supply Voltage V CC V DC Input or Output Voltage V CC V V IN V OUT Operating Temp Range (T A ) MM HC b a C MM HC b a C Input Rise or Fall Times (Clear Input) t r t f V CC e V ns V CC e V ns V CC e V ns DC Electrical Characteristics (Note 4) 74HC 54HC T A e25 C Symbol Parameter Conditions V CC T A eb40 to 85 C T A eb55 to 125 C Units Typ Guaranteed Limits V IH Minimum High Level Input V V Voltage V V V V V IL Maximum Low Level Input V V Voltage V V V V V OH Minimum High Level V IN ev IH or V IL Output Voltage li OUTl s ma V V V V V V V IN ev IH or V IL V li OUTl s ma V V li OUTl s ma V V V OL Maximum Low Level V IN ev IH or V IL Output Voltage li OUTl s ma V V V V V V V IN ev IH or V IL V li OUTl s ma V V li OUTl s ma V V I IN Maximum Input Current V IN ev CC or GND V g g g ma Pins I IN Maximum Input Current V IN ev CC or GND V g g g ma all other pins I CC Maximum Quiescent Supply V IN ev CC or GND V ma Current standby I OUT e ma I CC Maximum Active Supply V IN ev CC or GND V ma Current per R C EXT e V CC V ma monostable V ma Note 1 Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation Temperature Derating Plastic N Package b12mw C from 65 C to85 C Ceramic J Package b12mw C from 100 C to125 C Note 4 For a power supply of 5V g10% the worst-case output voltages (V OH V OL ) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst-case V IH and V IL occur at V CC e5 5V and 4 5V respectively (The V IH value at 5 5V is 3 85V ) The worst-case leakage current (I IN I CC and I OZ ) occur for CMOS at the higher voltage and so the 6 0V values should be used 2

17 AC Electrical Characteristics V CC e5v T A e25 C C L e15 pf t r et f e6ns Symbol Parameter Conditions Typ Limit Units t PLH Maximum Trigger Propagation Delay ns A B or Clear to Q t PHL Maximum Trigger Propagation Delay ns A B or Clear to Q t PHL Maximum Propagation Delay Clear to Q ns t PLH Maximum Propagation Delay Clear to Q ns t W Minimum Pulse Width A B or Clear ns t REM Minimum Clear Removal Time ns t WQ MIN Minimum Output Pulse Width C EXT e pf ns R EXT e kx t WQ Output Pulse Width C EXT e pf ms R EXT e kx AC Electrical Characteristics C L e50 pf t r et f e6 ns (unless otherwise specified) 74HC 54HC T A e25 C Symbol Parameter Conditions V CC T A eb40 to 85 C T A eb55 to 125 C Units Typ Guaranteed Limits t PLH Maximum Trigger Propagation V ns Delay A B or Clear to Q V ns V ns t PHL Maximum Trigger Propagation V ns Delay A B or Clear to Q V ns V ns t PHL Maximum Propagation Delay V ns Clear to Q V ns V ns t PLH Maximum Propagation Delay V ns Clear to Q V ns V ns t W Minimum Pulse Width V ns A B Clear V ns V ns t REM Minimum Clear V ns Removal Time V ns V ns t TLH t THL Maximum Output V ns Rise and Fall Time V ns V ns t WQ MIN Minimum Output C EXT e pf V ms Pulse Width R EXT e kx V ns R EXT e kx V CC e V V ns t WQ Output Pulse Width C EXT e mf Min V ms R EXT e kx Max V ms C IN Maximum Input pf Capacitance Pins C IN Maximum Input pf Capacitance other inputs C PD Power Dissipation Note pf Capacitance Note 5 C PD determines the no load dynamic power consumption P D e C PD V 2 CC f a I CC V CC and the no load dynamic current consumption I S e C PD V CC f a I CC 3

18 Logic Diagram TL F Theory of Operation j POSITIVE EDGE TRIGGER k NEGATIVE EDGE TRIGGER l POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING) n RESET PULSE SHORTENING o CLEAR TRIGGER FIGURE 1 TL F TRIGGER OPERATION As shown in Figure 1 and the logic diagram before an input trigger occurs the one shot is in the quiescent state with the Q output low and the timing capacitor C EXT completely charged to V CC When the trigger input A goes from V CC to GND (while inputs B and clear are held to V CC ) a valid trigger is recognized which turns on comparator C1 and N- channel transistor N1j At the same time the output latch is set With transistor N1 on the capacitor C EXT rapidly discharges toward GND until V REF1 is reached At this point the output of comparator C1 changes state and transistor N1 turns off Comparator C1 then turns off while at the same time comparator C2 turns on With transistor N1 off the capacitor C EXT begins to charge through the timing re- 4

19 sistor R EXT toward V CC When the voltage across C EXT equals V REF2 comparator C2 changes state causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 This ends the timing cycle with the monostable in the quiescent state waiting for the next trigger A valid trigger is also recognized when trigger input B goes from GND to V CC (while input A is at GND and input clear is at V CC k) The HC123A can also be triggered when clear goes from GND to V CC (while A is at GND and B is at V CC o) It should be noted that in the quiescent state C EXT is fully charged to V CC causing the current through resistor R EXT to be zero Both comparators are off with the total device current due only to reverse junction leakages An added feature of the HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage Thus propagation delay from trigger to Q is independent of the value of C EXT R EXT or the duty cycle of the input waveform RETRIGGER OPERATION The HC123A is retriggered if a valid trigger occurs l followed by another trigger m before the Q output has returned to the quiescent (zero) state Any retrigger after the timing node voltage at the R C EXT pin has begun to rise from V REF1 but has not yet reached V REF2 will cause an increase in output pulse width T When a valid retrigger is initiated m the voltage at the R C EXT pin will again drop to V REF1 before progressing along the RC charging curve toward V CC The Q output will remain high until time T after the last valid retrigger Because the trigger-control circuit flip-flop resets shortly after C X has discharged to the reference voltage of the lower reference circuit the minimum retrigger time t rr is a function of internal propagation delays and the discharge time of C X t rr 20 a 187 V CC b 0 7 a 565 a (0 256 V CC)C X V CC b Another removal retrigger time occurs when a short clear pulse is used Upon receipt of a clear the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger This time is dependent on the capacitor used and is approximately t rr e 196 a 640 V CC b 0 7 a 522 a (0 3 V CC)C X ns (V CC b 0 7)2 RESET OPERATION These one shots may be reset during the generation of the output pulse In the reset mode of operation an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to V CC by turning on transistor Q1 n When the voltage on the capacitor reaches V REF2 the reset latch will clear and then be ready to accept another pulse If the clear input is held low any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change Since the Q output is reset when an input low level is detected on the Clear input the output pulse T can be made significantly shorter than the minimum pulse width specification Typical Output Pulse Width vs Timing Components Typical Distribution of Output Pulse Width Part to Part Typical 1ms Pulse Width Variation vs Supply TL F Minimum R EXT vs Supply Voltage TL F Typical 1ms Pulse Width Variation vs Temperature TL F TL F TL F Note R and C are not subjected to temperature The C is polypropylene 5

20 MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator Physical Dimensions inches (millimeters) LIFE SUPPORT POLIC Dual-In-Line Package (J) Order Number MM54HC123AJ or MM74HC123AJ NS Package Number J16A Dual-In-Line Package (N) Order Number MM74HC123AN NS Package Number N16E NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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