Chapter 2. Introduction to Logic Circuits

Transcription

1 Chapter 2 Introduction to Logic Circuits

2 x = 0 x = 1 (a) Two states of a switch S (b) Symbol for a switch x Figure 2.1. A binary switch.

3 Battery S x Light (a) Simple connection to a battery Power supply S x Light (b) Using a ground connection as the return path Figure 2.2. A light controlled by a switch.

4 Power supply S S Light (a) The logical AND function (series connection) S Power supply S Light (b) The logical OR function (parallel connection) Figure 2.3. Two basic functions.

5 S X 1 S Power supply S X 3 Light X 2 Figure 2.4. A series-parallel connection.

6 R Power supply x S Light Figure 2.5. An inverting circuit.

7 Figure 2.6. A truth table for the AND and OR operations.

8 Figure 2.7. Three-input AND and OR operations.

9 x x 2 2 x x 2 n x n (a) AND gates x + x 2 2 x + x n x n (b) OR gates x x Figure 2.8. The basic gates. (c) NOT gate

10 f = ( x + x ) x Figure 2.9. The function from Figure 2.4.

11 Please see portrait orientation PowerPoint file for Chapter 2 Figure An example of logic networks.

12 Figure An example of a logic circuit.

13 Figure Addition of binary numbers.

14 Figure Proof of DeMorgan s theorem in 15a.

15 Please see portrait orientation PowerPoint file for Chapter 2 Figure The Venn diagram representation.

16 Please see portrait orientation PowerPoint file for Chapter 2 Figure Verification of the distributive property.

17 Please see portrait orientation PowerPoint file for Chapter 2 Figure Verification of x y + x z + y z = x y + x z.

18 Figure Proof of the distributive property 12b.

19 Figure Proof of DeMorgan s theorem 15a.

20 Figure A function to be synthesized.

21 f (a) Canonical sum-of-products f (b) Minimal-cost realization Figure Two implementations of the function in Figure 2.19.

22 Figure A bubble gumball factory.

23 Figure 2.22 Three-variable minterms and maxterms.

24 Figure A three-variable function.

25 f x 3 (a) A minimal sum-of-products realization x 3 f (b) A minimal product-of-sums realization Figure Two realizations of a function in Figure 2.23.

26 x 2 x n x n (a) NAND gates x x n x n (b) NOR gates Figure NAND and NOR gates.

27 (a) = + (b) + = Figure DeMorgan s theorem in terms of logic gates.

28 x 3 x 4 x 5 x 3 x 4 x 5 x 3 x 4 x 5 Figure Using NAND gates to implement a sum-of-products.

29 x 3 x 4 x 5 x 3 x 4 x 5 x 3 x 4 x 5 Figure Using NOR gates to implement a product-of sums.

30 f x 3 (a) POS implementation f x 3 (b) NOR implementation Figure 2.29 NOR-gate realization of the function in Example 2.11.

31 f x 3 (a) SOP implementation f x 3 (b) NAND implementation Figure NAND-gate realization of the function in Example 2.10.

32 Figure Truth table for a three-way light control.

33 Please see portrait orientation PowerPoint file for Chapter 2 Figure Implementation of the function in Figure 2.31.

34 Please see portrait orientation PowerPoint file for Chapter 2 Figure Implementation of a multiplexer.

35 Figure Display of numbers.

36 Please see portrait orientation PowerPoint file for Chapter 2 Figure A typical CAD system.

37 Figure The logic circuit for a multiplexer.

38 Figure Verilog code for the circuit in Figure 2.36.

39 module example2 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; endmodule and (z1, x1, x3); and (z2, x2, x4); or (g, z1, z2); or (z3, x1, ~x3); or (z4, ~x2, x4); and (h, z3, z4); or (f, g, h); Figure Verilog code for a four-input circuit.

40 Figure Logic circuit for the code in Figure 2.38.

41 Figure Using the continuous assignment to specify the circuit in Figure 2.36.

42 module example4 (x1, x2, x3, x4, f, g, h); input x1, x2, x3, x4; output f, g, h; endmodule assign g = (x1 & x3) (x2 & x4); assign h = (x1 ~x3) & (~x2 x4); assign f = g h; Figure Using the continuous assignment to specify the circuit in Figure 2.39.

43 Figure Behavioral specification of the circuit in Figure 2.36.

44 Figure A more compact version of the code in Figure 2.42.

45 Figure A logic circuit with two modules.

46 Figure Verilog specification of the circuit in Figure 2.12.

47 Figure Verilog specification of the circuit in Figure 2.34.

48 Figure Hierarchical Verilog code for the circuit in Figure 2.44.

49 Figure 2.48 The function f (,, x 3 ) = Σ m(0, 2, 4, 5, 6).

50 0 0 m m 1 m 2 m m 0 m 2 m 1 m 3 (a) Truth table (b) Karnaugh map Figure Location of two-variable minterms.

51 f = + Figure The function of Figure 2.19.

52 0 x m 0 x m 1 m 2 0 m 0 m 2 m 6 m m 3 m 4 m 5 1 m 1 m 3 m 7 (b) Karnaugh map m m m 7 (a) Truth table Figure Location of three-variable minterms.

53 Figure Examples of three-variable Karnaugh maps.

54 x 3 x m 0 m 4 m 12 m 8 01 m 1 m 5 m 13 m 9 x m 3 m 2 m 6 m 7 m 15 m 14 m 11 m 10 x 4 Figure A four-variable Karnaugh map.

55 Figure Examples of four-variable Karnaugh maps.

56 x 3 x x 3 x x 5 = 0 x 5 = 1 f 1 = x 3 + x 3 x 4 + x 3 x 5 Figure A five-variable Karnaugh map.

57 x x 3 Figure Three-variable function f (,, x 3 ) = Σ m(0, 1, 2, 3, 7).

58 x 3 x x x 3 x x 3 x 4 x 3 x 3 Figure Four-variable function f (,, x 4 ) = Σ m(2, 3, 5, 6, 7, 10, 11, 13, 14).

59 x 3 x x 3 x x 3 x x 3 x x 3 x 4 Figure The function f (,, x 4 ) = Σ m(0, 4, 8, 10, 11, 12, 13, 15).

60 x 3 x x 3 x x 3 x x 3 x x 3 x 4 x 4 x 4 x 1 x 3 x 1 x 3 Figure The function f (,, x 4 ) = Σ m(0, 2, 4, 5, 10, 11, 13, 15).

61 x ( + x 3 ) ( + ) Figure POS minimization of f (,, x 3 ) = Π M(4, 5, 6).

62 x 3 x ( x 3 + x ) ( + x ) ( + + x 3 + x ) 4 Figure POS minimization of f (,, x 4 ) = Π M(0, 1, 4, 8, 9, 12, 15).

63 Please see portrait orientation PowerPoint file for Chapter 2 Figure Two implementations of the function f (,, x 4 ) = Σ m(2, 4, 5, 6, 10) + D(12, 13, 14, 15).

64 Please see portrait orientation PowerPoint file for Chapter 2 Figure Using don t-care minterms when displaying BCD numbers.

65 Please see portrait orientation PowerPoint file for Chapter 2 Figure An example of multiple-output synthesis.

66 Please see portrait orientation PowerPoint file for Chapter 2 Figure Another example of multiple-output synthesis.

67 x 3 x 3 (a) Function A (b) Function B x 3 x 3 (c) Function C (d) Function f Figure The Venn diagrams for Example 2.23.

68 Please see portrait orientation PowerPoint file for Chapter 2 Figure Karnaugh maps for Example 2.26.

69 Please see portrait orientation PowerPoint file for Chapter 2 Figure Karnaugh maps for Example 2.27.

70 Figure A K-map that represents the function in Example 2.28.

71 Figure The logic circuit for Example 2.29.

72 Figure Verilog code for Example 2.29.

73 Figure The circuit for Example 2.30.

74 Figure Verilog code for Example 2.30.

75 x 3 x 3 x 4 x 4 (a) (b) Figure P2.1. Two attempts to draw a four-variable Venn diagram.

76 x 3 m 0 x 4 x 3 m 2 m 1 Figure P2.2. A four-variable Venn diagram.

77 x 3 f Time Figure P2.3. A timing diagram representing a logic function.

78 x 3 f Time Figure P2.4. A timing diagram representing a logic function.

79 Please see portrait orientation PowerPoint file for Chapter 2 Figure P2.5. Circuit for problem 2.78.

80 Please see portrait orientation PowerPoint file for Chapter 2 Figure P2.6. Circuit for problem 2.79.