Cyclone vs. Spartan-3 Performance Analysis

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1 White Paper Introduction The Altera Cyclone FPGA family is the low-cost FPGA performance leader, outperforming the Xilinx Spartan-3 family by an average of 70.2% when comparing the fastest speed-grade devices for both families. Even the slowest speed-grade Cyclone devices have an average of 29.6% performance advantage over the fastest speed-grade Spartan-3 devices, according to our benchmark results, clearly making the Cyclone FPGA family the performance leader. This white paper demonstrates the Cyclone family performance leadership by presenting complete benchmark data and a detailed analysis. Benchmark Methodology The benchmark was conducted using 49 designs collected from various customers in different market segments. Designs that include heavy use of multipliers represent a significant part of the benchmarked designs. The total number of designs in the low-cost FPGA benchmark suite (Cyclone vs. Spartan-3) is smaller than the number of designs in high-performance FPGA benchmark suite (Stratix vs. Virtex-II Pro) because the density range for low-cost devices is narrower than the density range for high-performance devices. For design synthesis, two independent experiments were exercised to obtain the results from commercially available synthesis software (i.e., Synplify from Synplicity) and the synthesis tools integrated in Altera and Xilinx software. The place-and-route and timing analysis for each design are completed in Altera Quartus II software and Xilinx ISE software. Both the fastest and slowest speed-grade Cyclone devices were used to compare with the fastest speedgrade Spartan-3 devices. Table 1 provides the basic information about the software and devices used in the benchmark. Refer to the FPGA Performance Benchmark Methodology white paper [3] for detailed benchmark methodology discussions. Table 1. Benchmark Setup Vendor Altera Xilinx FPGA Family Cyclone Family Spartan-3 Family Speed-Grade Synthesis Tool 3 rd party Integrated Tool Fastest (-6) and Slowest (-8) Synplify Quartus Integrated Synthesis (QIS) Fastest (-5) Synplify Xilinx Synthesis Technology (XST) Place-and Route Tool Quartus II version 4.0 Service Pack 1 ISE 6.2i Service Pack 1 April 2004, ver WP-CYCSPTN3PA-1.0

2 Altera Corporation Benchmarking Results The benchmark data include the results from using the commercial synthesis tool, Synplify, and the synthesis tools integrated in Quartus II and ISE software. For performance ratios in figures shown in this section, the followings apply: performance ratio > 1 : Cyclone device outperforms Spartan-3 device performance ratio = 1 : Cyclone and Spartan-3 devices show the same performance performance ratio < 1 : Spartan-3 device outperforms Cyclone device Benchmark Results Using Synpilfy Based on the benchmark data, comparing the fastest speed-grade devices for both Cyclone and Spartan-3 families, 130-nm Cyclone devices show a stunning 70.2% performance advantage over 90-nm Spartan-3 devices. The Cyclone family outperforms Spartan-3 in 48 of the 49 design an outstanding 98% winning rate. Figure 1 shows the benchmark data comparing the performance of the fastest devices for both Cyclone and Spartan-3 families. Figure 1. Fastest Speed-Grade Cyclone Devices vs. Fastest Speed-Grade Spartan-3 Devices Performance Comparison Note: (1) Data are collected using best effort software settings. Refer to FPGA Performance Benchmarking Methodology white paper. The Cyclone performance advantage is so pronounced that even the slowest speed-grade Cyclone device outperforms the fastest speed-grade devices by an average of 29.6%. The slowest speed-grade Cyclone product outperforms the fastest speed-grade Spartan-3 family in 43 of the 49 designs. Figure 2 shows the results for slowest speed-grade Cyclone devices vs. fastest speed-grade Spartan-3 devices. 2

3 Altera Corporation Figure 2. Slowest Speed-Grade Cyclone Devices vs. Fastest Speed-Grade Spartan-3 Devices Performance Comparison Note: (1) Data are collected using best effort software settings. Refer to FPGA Performance Benchmarking Methodology white paper. Benchmark Results Using QIS and XST To simulate the user experience for using low-cost FPGAs and lowest-cost FPGA tools, Altera compared Cyclone and Spartan-3 performance using synthesis tools integrated with the FPGA vendors software. This experiment uses Quartus Integrated Synthesis (QIS) in the Quartus II software for Cyclone devices and Xilinx Synthesis Technology (XST) in ISE software for Spartan-3 devices. This experiment uses the fastest speed-grade Cyclone and Spartan-3 devices and there are 33 designs; the design count reduction is mainly attributed to issues with the XST tool where the designs cannot pass through the XST. The benchmark results show that Cyclone devices outperform Spartan-3 by an average of 103.1%. The Cyclone family wins all 33 designs. Figure 3 shows the results for this benchmark. 3

4 Altera Corporation Figure 3. Cyclone-QIS vs. Spartan-3-XST Performance Comparison Notes: (1) Data are collected using least effort software settings. Refer to FPGA Performance Benchmarking Methodology white paper. (2) The lower number of designs in the QIS and XST flow is mainly attributed to the designs that cannot pass through XST. Cyclone FPGA Advantages The combination of the industry leading Quartus II place-and-route engine and the outstanding performance of the Cyclone architecture enable the Cyclone FPGA family to be the performance leader in the low-cost FPGA space. Advanced EDA Tool - The Quartus II Software The Quartus II software technology leadership produces optimal performance results for the Cyclone device family. Xilinx collateral [6] refers to the UCLA study, Optimality and Stability Study of Timing-Driven Placement Algorithms, [1] which finds that the Xilinx ISE placer was 4.1% from optimal. The same research shows that Quartus II software is only 3.0% away from the optimal, setting the Quartus II software as the most optimal FPGA place-and-route software in the industry. Xilinx collateral omits this point and incorrectly suggests that Xilinx tools outperform other tools in the industry [6]. In addition to the leadership in the place-and-route engine, the Quartus II software timing analyzer performs thorough timing analysis and handles many timing analysis pitfalls [4] to reduce the risk of design failure due to improper analysis. The Design Space Explorer (DSE) and integrated physical synthesis technology further strengthen the Quartus II leadership in the timing closure technology, allowing designers an automated mechanism for obtaining the best performance for their systems in an FPGA. 4

5 Altera Corporation Look-up Table and Routing Resource Performance The performance of an FPGA is determined by a combination of the silicon fabrication process, logic and routing structure, dedicated features, I/O support, and the maturity of the EDA tool. By examining the equivalent micro timing parameters such as the look-up table (LUT), routing segments, and dedicated features, they serve as indicators of how one FPGA architecture compares against another. The Cyclone LUT distinct attribute allows different propagation delay depending on which input is taken (See Figure 4). The Quartus II software automatically takes full advantage of this ability and rotates inputs to the LUT such that the critical path of a design enjoys the fast path through the LUT. However, the delay of the Spartan-3 LUT is modeled to be the same for each of its input in the Xilinx ISE 6.2i software. When the fastest LUT path is taken, Cyclone LUT provides over 6x performance gain over a Spartan-3 LUT. Even when the LUT path with the most delay is used, Cyclone LUT still provides a 43% performance improvement over the Spartan-3 LUT. Figure 4. Cyclone LUT vs. Spartan-3 LUT and Dedicated Multiplexer Delay Comparison Similar to the Virtex-II Pro family, the Spartan-3 family includes dedicated multiplexers (MUXF) as function expanders. These dedicated multiplexers in both the Virtex-II Pro and Spartan-3 families are often assumed capable of increasing large logic function performance [7]. Figure 5 shows the delay of the Spartan-3 LUT and MUXF. The delay of the Spartan-3 MUXF is about the same as a LUT, consequently, MUXFs provide no real improvement in logic performance. Furthermore, with the excessive delay from the MUXFs, each MUXF should be considered a distinct logic level, contrary to the Xilinx white paper WP206 [6] which only considers LUTs as logic levels. 5

6 Altera Corporation Figure 5. Cyclone vs. Spartan-3 Logic Delay Comparison Routing delay is also a reference point for determining the overall FPGA performance. The Cyclone family consistently provides better performance than Spartan-3 as shown in Figure 6. On average, for each increment in LUT distance, the Cyclone path delay increases by 5.8ps versus 9.5ps in Spartan-3. Cyclone routing resources offer an average of 39% faster performance per incremental LUT distance. Figure 6. Path Delay vs. Distance Profile for Cyclone and Spartan-3 Devices Notes: (1) Cyclone EP1C20-6 speed-grade and Spartan-3 XC3S speed-grade are used. (2) Cyclone and Spartan-3 data are extracted from Quartus II version 4.0 service pack 1 and ISE 6.2i service pack 1, respectively. (3) Delay is measured for the path between two registers without logic components (such as LUT, dedicated multiplexers, etc.). 6

7 Altera Corporation To further analyze the performance differences between the Cyclone and Spartan-3 families, a set of 46 design building blocks in 18 categories has been benchmarked. These building blocks, ranging from counters to wide logic functions to multiplexers and parity checkers, are commonly found in any design. The Cyclone family outperforms Spartan-3 in all 18 design categories and is on average 61% faster. Figure 7 shows the Cyclone and Spartan-3 performance comparison in each category. Figure 7. Design Building Block Performance Comparison between Cyclone and Spartan-3 Notes: (1) Cyclone -6 speed-grade and Spartan-3-5 speed-grade devices are used. (2) Designs are synthesized by Quartus Integrated Synthesis and Xilinx Synthesis Technology (XST) for Cyclone and Spartan-3, respectively. (3) Quartus II version 4.0 service pack 1 and ISE 6.2i service pack 1 are used for place-and-route and timing analysis for Cyclone and Spartan-3, respectively. Conclusion Low-cost FPGA performance is critical in allowing designers to comfortably meet system performance goals and accelerate time-to-market for their systems. The Cyclone FPGA family outperforms the Spartan-3 family by an average of 70.2% based on the benchmark results using real customer designs. Even the slowest speed-grade Cyclone devices are 29.6% faster than the fastest speed-grade Spartan-3 devices, clearly making the Cyclone device family the low-cost FPGA performance leader. 7

8 Altera Corporation References [1] Cong J., Romesis M., and Xie M. Optimality and Stability Study of Timing-Driven Placement Algorithms, UCLA Technical Report ( [2] Altera Cyclone Handbook [3] Altera white paper, FPGA Performance Benchmarking Methodology [4] Altera white paper, Performing Equivalent Timing Analysis Between the Altera Quartus II Software and Xilinx ISE [5] Xilinx Data Sheet, DS099, Spartan-3 FPGAs Complete Data Sheet, March 4, 2004 [6] Xilinx white paper, WP206, The 40% Performance Advantage of Virtex-II Pro FPGAs over Competitive PLDs, version 1.2, March 1, 2004 [7] Xilinx white paper, WP209, Virtex Variable-Input LUT Architecture, version 1.0, January 12,

9 Altera Corporation 101 Innovation Drive San Jose, CA (408) Copyright 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.* All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 9

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