ISSN Vol.02, Issue.07, October-2014, Pages:

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1 ISSN Vol.02, Issue.07, October-2014, Pages: Design and Implementation of Digital Adaptive Filter on Spartan-6 FPGA for ECG Signal Processing V. ARCHANA PRIYA 1, M. MURALIDHAR 2 Abstract: Recent advances in synthesis tools for VLSI designs suggest a feasible high-level design approach for the implementation of DSP Filters on FPGAs at ease. An efficient FPGA based hardware design for the implementation of adaptive filter is proposed using XILINX System Generator tools. Digital filters play a vital role in today s complex digital processing. Designing of the digital adaptive filter can be done with less effort by using the Xilinx System Generator. This paper brings out adaptive digital filter design implementation by performing the hardware-in-the-loop verification. The hardware model is automatically generated by the system generator in the design. Here the board support packages are readily generated for the Spartan-6 FPGA. ECG data from MIT-BIH archives were tried out for the testing of Adaptive filters and a significant improvement in the ECG signal parameters were observed. Keywords: Xilinx System Generator; Matlab Simulink; Hardware Co-Simulation; Spartan6 FPGA. I. INTRODUCTION Designing of digital filters is a very complex task using the normal conventional methods and also time consuming to design and implement. All this process can be done easily by design using advanced MATLAB Simulink features. The project work carried out as partial fulfillment of graduate degree by designing of a digital adaptive filter using XILINX System Generator Tools and MATLAB/Simulink, Simulink as a graphical design tool offers high level integration with the MATLAB environment. Implementation of digital adaptive filters is done on Spartan-6 using Xilinx System generator. Filters are used to remove the unwanted noise components from the information bearing signal. If the unwanted components like noise and other artifacts statistical properties are varying with time then the conventional optimum filter based on Gaussian Noise model will not give fruitful results, hence the deployment of an Adaptive filter is inevitable. Adaptive filters are the solution which is most widely applied for non stationary signals/noise. Fig.1. Design Process Steps. Design Process Steps: Designing and Implementing the Digital adaptive filter using this method are done using the steps given below and its shown in Fig.1, First the design of the model with the required specifications for the digital adaptive filter is done. Software simulation was performed and parameters of the filter were adjusted for the required performance. Next the hardware co simulation block was generated for the specific FPGA and it s the results were verified by connecting the hardware co-simulation block in loop to the actual filter design. II. DIGITAL ADAPTIVE FILTER A. Digital Filter Digital filters are found everywhere in present day signal processing applications. Filters are used to extract desired characteristics of a signal, and to remove unwanted signals, like noise from the signal. The digital filters are used to restrict the signal into a particular frequency band as done in low pass filtering, high pass filtering etc., Digital filters perform their operation on sampled and discrete time signals. B. Adaptive Filter Adaptive filtering involves change of filter coefficients with time, to vary with changing signal/noise characteristics. Adaptive filters play a key role in processing non stationary signals. Adaptive filters are linear and time variant systems. Adaptive filters are required for applications where the desired processing operation is not known in advance and/or changing. In many practical areas it might require to filter a signal whose exact frequency response is unknown. Solution to such a problem is an adaptive filter. Fig.2. Block Diagram of Adaptive Filter IJVDCS. All rights reserved.

2 i. Adaptive Filtering Algorithms There are two most widely used algorithms for adaptive filtering process. That are, Recursive Least Squares(RLS) Algorithm Least Mean Squares(LMS) Algorithm In this project work we used RLS algorithm. The Recursive least squares is a more widely used algorithm for adaptive filters that can recursively find the filter coefficients as shown in Fig.2.. The Recursive Least squares algorithm is well known for its excellent performance for working in time varying environments. But the computational complexity is high for recursive least squares algorithm and also has its own stability problems. ii. Adaptive Noise Cancellation Adaptive filters have found their applications in numerous fields like compression of predictive video and speech, cancellation of noise and echo signals, equalization, in medical applications like removal of unwanted signal from an original Electrocardiogram signal. In this project we have implemented the adaptive noise cancellation which is one of the applications of adaptive filters. Adaptive noise Cancellation is a technique of estimating the signals corrupted by noise signals or interference as shown in Fig.3. Its advantage is with no initial estimates of signal or noise, levels of noise rejection can be attained which would be difficult to achieve by other signal processing methods that are usually used to remove the noise from the signals. It requires two input signals, a primary input signal containing the corrupted signal and a reference input containing noise correlated with the primary noise in some unknown way. In order to obtain the signal estimate the reference input is adaptively filtered and is deducted from the primary input. The adaptive filter for example taking ECG input from the patient and from the power supply as signal would be able to track the actual frequency of the power signal as it fluctuates. An adaptive technique allows for a filter with a smaller rejection range that ensures quality of the output signal is more accurate which is very essential for medical diagnoses. V. ARCHANA PRIYA, M. MURALIDHAR III. DESIGNING OF DIGITAL ADAPTIVE FILTER USING SIMULINK A. MATLAB The Matlab environment provides command/gui interfaces and has a well defined set of software modules known as Tool Boxes, which can perform more number of specialized computations. Matlab has more number of tool boxes among that Digital signal processing tool box has more importance, which is helpful in designing filters, performing filtering, performing discrete fourier transforms etc. B. SIMULINK Simulink, developed by Math Works, is a data flow graphical programming language tool for modeling, simulating and analyzing multidomain dynamic systems. Simulink is a graphical, drag and drop environment for building both the simple and complex system dynamic simulations. It allows users to focus on the structure of the problem, rather than having to worry much about the programming language. It is used to analyze, model, and simulate the dynamic systems by using block diagrams as shown in Fig.4. Simulink is fully integrated with MATLAB, fast and easy to learn and is highly flexible. Fig.4. Design of ECG processing using adaptive filter. Fig.3. Adaptive Noise Cancellation System. Design of Digital Adaptive Filter using Simulink: The digital adaptive filter is designed using the blocks readily available in Simulink and the Xilinx blockset of Simulink and is shown in the figure below. In my project design there are two parts, one part with Simulink native blocks, and the rest of the part with Xilinx blocks. The Xilinx blocks are grouped in a Xilinx System Generator Subsystem. These blocks are optimized for Xilinx FPGAs by the System Generator.

3 Design and Implementation of Digital Adaptive Filter on Spartan-6 FPGA for ECG Signal Processing IV. IMPLEMENTATION OF ADAPTIVE FILTER Xilinx system generator provides a good stability between USING XILINX SYSTEM GENERATOR the advanced design entry, the quantity of control capable in The Xilinx System Generator block allows control of the design processes and data testing properties is provided system and execution and is used to call up the code by the XSG which is usually expected in a high-level tool. generator. Each Simulink model holding any component from the Xilinx Blockset must hold not less than one System V. SPARTAN-6 FPGA Generator block. When a System Generator piece is added to Spartan 6 is built on a 45 nm technology which delivers an a model, it is conceivable to detail how code creation and optimal balance of power, cost, and performance. The execution ought to be taken care of. For a point by point Spartan-6 family of FPGA has a dual register 6 input LUT examination on the most proficient method to utilize the XSG logic and also possesses an affluent choice of in built system block, check Compilation and Simulation utilizing the level blocks which includes 18Kb block RAMs, SDRAM System Generator Block. Using Xilinx system generator memory controllers, second generation DSP48A1 slices, parallel systems with industry s highly advanced FPGAs can enhanced mixed-mode clock management blocks, power be developed. Xilinx system generator provides automatic optimized elevated speed serial transceiver blocks, autodetect code generation and system modeling from Simulink and configuration options, advanced system level power MATLAB. Xilinx system generator integrates embedded, management modes, and superior IP security. Spartan6 RTL, MATLAB, IP and hardware components of a DSP FPGAs offers the flexibility to react fast for the varying user system. The system generator tool can automatically create requirements. It improves the performance with flexible synthesizable Hardware Description Language code that can serial and parallel interface abilities. be mapped to Xilinx pre-optimized algorithms. This HDL design that is generated can then be synthesized for execution Spartan-6 Families: The family of Spartan-6 FPGA consists in any Xilinx FPGAs like Spartan 6E and Spartan 3E FPGAs of two sub families which are optimized with features etc. Normally it is very difficult to develop a VHDL code harmonized to strict market necessities for low price, and that synthesizes simply in less time. As VHDL code is high-volume applications. In this project Spartan-6 LX generated automatically by the System Generator and we FPGA is used. actually don t write the code, and it can be synthesized XASpartan-6 LX FPGA: Which is Logic optimized. without difficulty. It is very easy to generate error free XASpartan-6 LXT FPGA: Offers High-speed serial designs in high level languages like Matlab but the designers connectivity need to have more experience. Advantages of Xilinx System Generator: Capability of the cycle accurate and bit true simulation for DSP is one of the important features of XSG because of which the user can authenticate the design before its implementation on hardware The models that are developed by using XSG can effortlessly be run in Matlab, which is one of the most important arguments to use Xilinx Blockset and the Xilinx system generator. The process of Synthesizing the code which is generated from the Xilinx model with System Generator is uncomplicated to create, and the creation and verification of test bench, test vectors is also excellent. With a graphical atmosphere of Simulink and a predefined set of Xilinx DSP cores blocks, the System Generator meets the need of hardware designers who optimizes the implementations and also the system architects who would combine the components of a complete design. Most proficient graphical user interface for the design entry and ability to reuse the code along with automatic configuration of design would reduce the design time and overhead of the engineer by a huge order. A unique feature of XSG i.e., hardware in the loop cosimulation allows the designers to speed up the simulation and verifying the design in hardware. Features of Spartan 6 FPGA: Spartan 6 is a 45nm Low Power Process Technology that is optimized for power, cost, and performance, and is an efficient low power copper process technology. Possess six-input LUTs which are efficient and are helpful to get better performance and reduce the power. Offers an optimized choice of I/O standards. Spartan 6 has low static and dynamic power. Offers LUTs which are flexible and are configurable as logic, shift registers or distributed RAM. Possess 3,800 to 147,000 logical cells to be used for system level integration. Spartan-6 FPGAs provides flexibility to act in response for rapidly varying user requirements.spartan-6 FPGAs offers cost efficient substitute to ASICs and enable the designers to develop the designs with minimum creation lifecycles. VI. HARDWARE CO-SIMULATION Hardware software co-simulation is a phenomenon which refers to verify that the hardware and software part of a model works properly together. This process is usually performed when the model hardware is accessible. With hardware software co-design it is essential to confirm exact functionality prior to the creation of hardware. Through the hardware and software co-design it is possible to build up extremely efficient and reliable systems. Low level

4 techniques of simulation are consumes more time for evaluation and configuration. System Generator would provide hardware co-simulation interface which makes it possible to incorporate an FPGA directly into a Simulink simulation. The system generator has an option Hardware Co-simulation compilation targets which is similar to the HDL Netlist that creates a bitstream automatically. After creation of the bitstream, System Generator can incorporate an FPGA hardware platform automatically which is configured with the bitstream generated. When the model designed is run in Simulink, outcome for the part which is compiled is measured in hardware, that allows the compiled part to be tested in actual hardware, and can speed up simulation. Hardware software co-simulation interface which is narrated in using FPGA Hardware in the Loop allows executing the model in hardware in command of Simulink. V. ARCHANA PRIYA, M. MURALIDHAR the PQRS wave information which is of no interest and enhanced the T wave which is of more importance and the harmonics are also get enhanced. A. Hardware Co-Simulation Block System Generator would automatically create a new hardware co-simulation block soon after it completes compilation process of our model into an FPGA bitstream. A Simulink library is also produced to store up the hardware co-simulation block. The port names on the hardware cosimulation block will be equivalent to the ports names, port types and data rates on the original design. Hardware cosimulation blocks are used in a Simulink model in the similar way how the other blocks are used. During the process of simulation, a hardware co-simulation block would interact with the basic FPGA board. B. Hardware in the Loop Hardware in the loop is a type of real time simulation which varies from the real time simulation by the adding up of an actual module in the loop. The major reason of the HIL Simulation is to check the hardware target on a simulator prior to we put into practice it on the real environment. It is more advantageous in terms of duration, cost, and safety. Hardware in the loop simulation is a trusted, cost effective substitute in which testing is done in a virtual test circumstances, as a replacement of real devices. By appropriately specifying the target hardware specifications and by selecting the generate option in system generator block in the design the hardware co- simulation block is generated. By placing the hardware co-simulation block in the loop with the actual design we will get the design that is suitable to be executed in the target FPGA. The final design with the hardware co-simulation block placed in the loop for testing of the function of digital adaptive filter for noise cancellation is as shown in the figure below. VII. RESULTS ECG signal from MIT-BIH database for Twaves were tried for the testing of the Digital Adaptive Filter using Xilinx Block Set in Matlab Simulink and is verified for the performance. A 12 lead ECG is taken and the 11 th lead is considered as an input signal and the 1 st lead is considered as a correlation to the input signal. The results obtained are as shown in the below fig.5. The final output signal suppressed a) Output waveforms b) FFT spectrum of input signal c) FFT spectrum of output signal

5 Design and Implementation of Digital Adaptive Filter on Spartan-6 FPGA for ECG Signal Processing [3] S.C. Douglas, ``Introduction to Adaptive Filters,'' in The DSP Handbook, V.J. Madisetti and D. Williams, eds. (Boca Raton, FL: CRC/IEEE Press, 1998), Chapter 18. [4] Widrow, B., Adaptive Noise Cancelling: Principles and Applications, Proc. IEEE, vol. 63, pp , Dec [5] Xilinx System Generator for DSP. ise/ optional prod/system generator.htm, Xilinx. [6] en/. d) AdaptiveFilter coefficients Author s Profile: V.ARCHANA PRIYA was born in Nellore, Andhra Pradesh, India. She received B.Tech degree in electronics and communication engineering from Priyadarshini College of engineering and technology, Nellore. She is pursuing M.Tech from Narayana Engineering College, Nellore, AP, India. M.MURALIDHAR was born in Chennai, India. He received his Bachelors degree in Electronics and Communication from University of Madras followed by a Masters degree in Electrical Engineering from Indian Institute of Technology, Madras. He has over 8 years of teaching and 14 years of Industrial experience in designing and developing Embedded Systems for some of OEM Majors in and outside India. e) Adaptive Filter Frequency Response Fig.5. Results. VIII. CONCLUSION By designing the digital filters with the help of MATLAB Simulink the designing of the system is done WITH ease and the same digital adaptive filter design for ECG processing is implemented on Spartan 6 FPGA using Xilinx system generator and by following the hardware co-simulation method it provides full system integration and also enable parallel development of Hardware and Software components and thus reduces the duration of development cycle, hence reduces the time to Market. By executing the Hardware in the loop we can verify the hardware target on a simulator prior to its verification on the real environment and acts as a replacement for real-devices and is more advantageous in terms of testing effort, cycle time, cost, and safety. IX. REFERENCES [1] S. Haykin, Adaptive Filter Theory, Prentice Hall, Englewood Cliffs, NJ, 4th edition, [2] R. Chand, et al., "FPGA Implementation of Fast FIR Low Pass Filter for EMG Removal from ECG Signal," IEEE, vol , 2010.