Application Note AN-1043

Transcription

1 Application Note AN-043 Stabilize the Buck Converter with Transconductance Amplifier By Michael (Choning) Qiao, Parviz Parto and Reza Amirani. Introduction Loop Gain of System Typical Procedure of Design Type II (PI) Design Introduction to PI ) Design Example of PI Type III (PID) ) Introduction to Type III s ) Type III (PID) Design Method A ) Design Example of PID Method A ) Type III (PID) Compensation Design Method B ) Design Example of IRU3037 with Ceramic Capacitor and PID Method B Conclusion... 0 Synchronous DC-DC buck converters have high efficiency, and International Rectifier has developed a series of PWM voltage mode controllers for synch buck converters, including single and multi-phase controllers such as IRU3037, IRU3038, IRU3046 and IRU3055. One feature of these controllers is that transconductance amplifiers are employed as voltage feedback error amplifiers.

2 APPLICATION NOTE AN-043 Stabilize the Buck Converter with Transconductance Amplifier Michael (Choning) Qiao, Parviz Parto and Reza Amirani, International Rectifier Synchronous buck converters have received great attention in low power, low voltage DC-DC converter applications in recent years due to their high efficiency. International Rectifier Inc. has developed a series of PWM voltage mode controllers for synchronous buck converters, including single phase and multi-phase controllers such as IRU3037, IRU3038, IRU3046, IRU3055, etc. One feature of these controllers is that transconductance amplifiers are employed as voltage feedback Error Amplifiers. Theoretically, a transconductance amplifier is an equivalent voltage controlled current source. It multiplies the difference of input voltage with a certain gain and generates a current into the output node. It features high output impedance and it is stable by most of the output compensation components. The output short circuit protection and internal compensation is not required. This results in a smaller die size and simple design. In this application note, how to stabilize the buck converter with transconductance Error amplifier is discussed. The goal of the design is to provide a loop gain function with a high bandwidth (high zero-crossover frequency) and adequate phase margin. As a result, fast load response and good steady state output can be achieved.. Introduction to Synchronous Buck Converter with Transconductance Amplifier + V IN Q Q2 PWM generator with Transconductance Amplifier L Figure - Simplified diagram for synchronous buck converter with transconductance amplifier. The simplified diagram for synchronous buck converter with transconductance amplifier is shown in Figure, where RL is the inherent resistance of output inductor RL Output Inductor Buck Converter Output Capacitor Cc2 Rc Cc ESR COUT R LOAD Rf VOUT and ESR is the Equivalent Series Resistance of output capacitor. There are three sections. One is synchronous buck converter including output inductor and capacitor. The controller such as IRU3037 provides the basic function block such as PWM generator and transconductance amplifier. The resistor and capacitor with the transconductance amplifier, function as a compensator to stabilize the system. From control system point of view, the three blocks are shown in Figure 2. G(s) PWM Generator D(s) VOSC GP(s) VOUT +ESR COUT s GP(s) L +s ( +s 2 L COUT RLOAD ) +ESR COUT G(s) GP(s) ---(2) VOSC Buck Converter Figure 2 - The control diagram for the synchronous buck converter with transconductance amplifier. The transfer function of the PWM generator is basically /VOSC, where VOSC is the peak to peak voltage of oscillator listed in the datasheet. The transfer function of the buck converter can be simplified as follows: FPO ---(3) 2 π L COUT VIN ---() The (s) indicates that the transfer function varies as a function of frequency. For simplification, we can combine the transfer function of PWM generator and buck converter. This results in power stage of buck converter and is expressed as: Basically, the transfer function of the power stage is a second order system and the Bode plot is shown in Figure 3. The resonance of the output LC filter introduces a double pole and Gain Slope (see Figure 3). The resonance frequency of the LC filter is expressed as follows: Rev.. 0/07/02

3 APPLICATION NOTES AN-043 The ESR of the output capacitor and capacitance introduces one zero for the system. The zero is given as: FZO ---(4) 2 π ESR COUT Where FZO is a character parameter and dependent on the characteristic of what capacitor is chosen. Typically, for an electrolytic capacitor, the FZO is in a few KHz range. Power Stage f VIN VOSC Magnitude Desired Loop Gain FPO FZO Fo f 0 Phase Phase Margin f Fpo Fzo Figure 4 - Bode plot of desired loop gain function. 0 Phase f 3. Typical Procedure of Design In order to realize the desired loop gain with high enough zero-cross over frequency and proper phase margin, a compensator has to be designed. A typical procedure is as follows: Figure 3 - The Bode plot of buck converter power stage. 2. Loop Gain of System The loop gain of system is defined as the product of transfer function along the closed control loop. From Figure 2, the loop gain is defined as: H(s) D(s) GP(s) D(s) G(s) ---(5) VOSC The Bode plots of desired loop gain and power stage is shown in Figure 4, where FO is the zero crossover frequency defined as the frequency when loop gain equals unity. Typically, FO can be chosen to be /0~/5 of the switching frequency. FO determines how fast the dynamic load response is. The higher FO is, the faster dynamic response will be. The slope rate of loop gain around FO should be 20dB in order to get a stable system. The phase margin is shown in Figure 4. Typically, 45 or more phase margin is desired for a stable system. Step - Collect system parameters such as input voltage, output voltage, etc. and determine switching frequency. Step 2 - Determine the power stage poles and zeros. Step 3 - Determine the zero crossover frequency and compensation type. The compensation type is determined by the location of zero crossover frequency and characteristics of output capacitor as shown in Table. Type Type II (PI) Type III (PID) Method A Type III (PID) Method B Location of Zero Crossover Frequency (FO) FPO < FZO < FO < fs/2 FPO < FO < FZO < fs/2 FPO < FO < fs/2 < FZO Typical Output Capacitor Electrolytic, Tantalum Tantalum, Ceramic Ceramic Table - The compensation type and location of zero crossover frequency. Rev.. 2 0/07/02

4 APPLICATION NOTE AN-043 Step 4 - Determine the desired location of zeros and poles for the selected compensator. Step 5 - Calculate the real parameters-resistor and capacitors for the selected compensator. Choose the resistors and capacitors from standard catalog such that they are as close to the calculated value as possible. 4. Type II (PI) Design 4.) Introduction to PI Rf VOUT Ve Rc Figure 5 - PI configuration. Power Stage Desired Loop Gain PI Fpo Fzo Fo Cc fs/2 A PI compensator can be used as shown in Figure 5. Overall, the Bode plots of power stage, desired loop gain and PI compensator are displayed in Figure 6. A PI compensator has one zero at: FZ ---(6) 2π RC CC Resistors Rf and are used to determine the output voltage. The output voltage is determined as: VOUT Rf + ---(7) The output voltage can be directly connected to the feedback pin of the Error amplifier. This is shown as: VOUT The resistor RC determines the zero crossover frequency. It can be calculated as: 2π FO L VOSC Rf + RC ESR VIN When the above equation is combined with equation (7), it results to: 2π FO L VOSC VOUT RC ---(8) ESR VIN Set the zero of PI compensator to 75% of FPO: FZ 0.75 FPO ---(9) 2π RC CC The compensator capacitor Cc can be calculated as: L COUT CC ---(0) π FPO RC 0.75 RC In practice, one more capacitor is sometimes added in parallel with the RC network as shown in Figure 7. VOUT Figure 6 - Bode plot of the buck converter power stage, desired loop gain and PI compensator. In many applications, an electrolytic capacitor is chosen as the output capacitor due to its low cost. For electrolytic capacitor, the zero caused by ESR (FZO) is a few KHz. If the switching frequency is a few hundred KHz, the zero crossover frequency FO is chosen to be /0 of switching frequency and FO is located at: FPO < FZO < FO < fs/2 Fz Rf Ve Rc Cc2 Cc Figure 7 - PI compensator with one additional pole. Rev.. 0/07/02 3

5 APPLICATION NOTES AN-043 This additional capacitor gives a second pole as: FP2 ---() CC CC2 2π RC Set this pole to one half of switching frequency, which results in the capacitor Cc2. FP2 fs 2 CC + CC2 CC2 ---(2) π RC fs π RC fs - CC 4.2) Design Example of PI Take IRU3037 controlled buck converter as an example. The schematic is shown in Figure 8. Step - Collect system parameters such as input voltage, output voltage, etc. and determine switching frequency. Input Voltage Output Voltage Output Current Switching Frequency Output Inductor Output Capacitor Peak to Peak Oscillator Ramp Voltage Reference Voltage Transconductance Gain 5V 3.3V 0A 200KHz 3.3µH 2200µF with 8mΩ ESR VOSC.25V.25V 0.6mA/V or 600µmho Table 2 - The parameters of IRU3037 controlled buck converter in Figure 8. D N448 L 5V C3 uf C4 uf D2 N448 C5 0.uF uh C2 2x 0TPB00ML, 00uF, 55mΩ C 47uF C8 0.uF SS Vcc Vc U IRU3037 HDrv LDrv Q IRF7457 Q2 IRF7460 L2 3.3uH 0A C7 2200uF ESR 8mΩ Cc2 68pF Cc 4.7nF Rc 27K Comp Gnd Fb K, % Rf.65K, % Figure 8 - Application of IRU3037 with PI compensator. Rev.. 4 0/07/02

6 APPLICATION NOTE AN-043 Step 2 - Determine the power stage poles and zeros. The pole caused by the output inductor and output capacitor is calculated as: FPO 2π L COUT FPO FZO FZO 2π 3.3µH 2200µF 2π ESR COUT 2π 8mΩ 2200µF.87KHz The zero caused by ESR of the output capacitor is calculated as: 4KHz Step 3 - Determine the zero crossover frequency and compensation type. Select desired zero-crossover frequency: fs FO ~ 5 fs 0 Select FO20KHz Because we have FPO<FZO<FO< is chosen., a PI Step 4 - Determine the desired location of zeros and poles for the selected compensator. Select: FZ 0.75 FPO KHz.4KHz If additional capacitor is chosen: FP2 fs 2 00KHz Step 5 - Calculate the real parameters-resistor and capacitors for the selected compensator. Calculate RC from equation (8): RC 2π FO L VOSC ESR VIN VO RC 2π 20KHz 3.3µH mΩ 5V RC 25.3K Select RC 27K Calculate CC By: L COUT CC π FPO RC 0.75 RC CC 3.3µH 2200µF K fs 2 4.2nF (Optional) Second capacitor CC2 can be calculated using equation (2): CC2 Zf π RC fs π 27K 200K 59pF Select CC2 68pF Calculate resistors Rf and. Select resistor to be a reasonable value. For example, from low noise point of view, select K, %. VO Rf K.64K.25 Select Rf.64K, % 5. Type III (PID) 5.) Introduction The PI compensation is based on the output capacitor having enough ESR to ensure stability. If the output capacitor is a ceramic capacitor, the zero caused by ESR will be much larger than the desired zero cross over frequency, the type III (PID) compensation is considered as shown in Figure 9. The Bode plot of the PID compensation network is shown in Figure 0. Rf3 Rf Cf3 VOUT Rc Cc2 Cc Figure 9 - PID compensation network. PID Fz Fz2 Fp2 Ve Figure 0 - Bode plot of PID compensator. Zc Fp3 fs/2 Rev.. 0/07/02 Select CC 4.7nF 5

7 APPLICATION NOTES AN-043 The transfer function of the PID compensator is given as: Ve - ZC ---(3) VOUT + Zf+Zf/ The error amplifier gain is independent of the transconductance under the following condition: Zf Zf >> + and ZC >> So we have: Ve VOUT ZC Zf By replacing the ZC and Zf according to Figure 9, the transfer function can be expressed as: s s + ( 2π FZ) ( + 2π FZ2) D(s) s Rf (CC+CC2) s s + + 2π FP2 2π FP3 ( )( ) The compensator has two zeros and three poles. FZ ---(5) 2π RC CC FZ2 ---(6) 2π Cf3 (Rf+Rf3) FP 0 FP2 ---(7) 2π Rf3 Cf3 FP3 ---(8) 2π RC CC CC2 CC+CC2 ---(4) The type III compensator is usually designed by selection of location of FZ, FZ2, FP2 and FP3 in order to get the desired zero crossover frequency and enough phase margin. If ZC>, equation (3) will change its polarity and a 80 degree phase shift will be introduced. The system will become unstable. Therefore, a careful selection of ZC has to be made. It is verified that the following restriction has to be followed: RC >> 2 (mandatory); Rf Rf3 > (desirable) ---(9) Where Rf Rf3 are the parallel resistance of Rf, and Rf3. 5.2) Type III (PID) Design Method A If the zero caused by ESR is less than half of the switching frequency, that is FPO<FO<FZO<fS/2, then the following design method can be used. Set first zero of PID at 75% of the resonant pole caused by output inductor and capacitor: FZ 75% FPO ---(20) Set second zero of PID at exact resonant pole caused by output inductor and capacitor: FZ2 FPO ---(2) Set second pole of PID at the zero caused by output capacitor ESR: FP2 FZO ---(22) Set the third pole of PID at one half of switching frequency: FP3 fs/2 ---(23) The Bode plot of power stage and proposed PID compensator is shown in Figure. Power Stage Loop Gain PID Fz Fpo Fz2 Fo Fp2 Fzo Fp3 fs/2 Figure - The Bode plot of the buck converter power stage, the desired loop gain and PID compensator (method A). The zero crossover frequency FO is determined by the following equation: VOSC 2π FO L COUT Cf3 ---(24) VIN RC Rev.. 6 0/07/02

8 APPLICATION NOTE AN-043 5V D N448 L C3 uf C4 uf D2 N448 C5 0.uF uh C2 2x 0TPB00ML, 00uF, 55mΩ C 47uF Tantalum C8 0.uF SS Vcc Comp Cc 4.7nF U IRU3037 Gnd Cc2 50pF Vc Rc 0K HDrv LDrv Fb Q IRF7457 Q2 IRF7460 Cf3 2.2nF 7.5K, % Rf.7K, % L2 3.3uH Rf3 2.74K 0A C7 Poscap, 2x 6TPC50M 50uF, ESR 40mΩ Each Figure 2 - An example of IRU3037 controlled buck converter with PID compensation method A. 5.3) Design Example of PID Method A Step - Collect system parameters in Figure 2 such as input voltage, output voltage, etc. and determine the switching frequency. Comparing with section 4.2, only the output capacitor is changed. The output capacitor is 2 50µF with 40mΩ each. The total ESR is: ESR 40mΩ/2 20mΩ Total capacitor is: COUT 2 50µF 300µF Step 2 - Determine the power stage poles and zeros. FPO 2π L COUT FPO FZO 2π 3.3µH 300µF 5KHz Zero caused by ESR: FZO 26.5KHz 2π ESR COUT 2π 20mΩ 2 50µF Step 3 - Determine the zero crossover frequency and compensation type. Select desired zero-crossover frequency. fs FO ~ 5 fs 0 If we select FO30KHz and we have FPO<FZO<FO<fS/2, the PI compensator in section 4.2 can be chosen. Suppose FO5KHz and FPO<FO<FZO<fS/2, then a PID compensator with method A is chosen. Step 4 - Determine the desired location of zeros and poles for the selected compensator. Select: FZ 0.75 FPO 3.75KHz FZ2 FPO 5KHz FP2 FZO 26.5KHz fs 200KHz FP3 00KHz 2 2 Rev.. 0/07/02 7

9 APPLICATION NOTES AN-043 Step 5 - Calculate the real parameters-resistor and capacitors for the selected compensator. 2 Select RC so that RC >> Calculate CC and CC2 by setting FZ0.75 FPO and FP3fS/2: CC 2π FZ RC 2π 3.75KHz 0K 4.2nF Calculate capacitor Cf3 by using equation (24): Calculate Rf3 and Rf by setting FP2FZO and FZ2FPO: Calculate : Check: K 0.6mA / V Select RC 0K Select CC 4.7nF CC2 2π FP3 RC 2π 00KHz 0K 59pF Select CC2 50pF > 30pF(reasonable capacitor) Cf3 VOSC 2π FO L COUT Select Cf32.2nF VIN RC Cf3.25 2π 5KHz 3.3µH 300µF 5V 0K Rf3 2π Cf3 FP2 Select Rf3 2.74K Rf Rf 2π Cf3 FZ2 2π 2.2nF 5KHz Select Rf.7K 2.3nF 2.73K 2π 2.2nF 26.5KHz - Rf3 Rf VOUT Select 7.5K, %.7K 7.3K K.7K Rf Rf3.7K 7.5K 2.74K Rf Rf3.7K > /.6K 5.4) Type III (PID) Compensation Design Method B If a ceramic capacitor is chosen, the zero caused by ESR of capacitor is in the order of the switching frequency such as FZO>fS/2. The compensator method A will not be very suitable. The compensation calculation can be based on the lead lag compensation (method B). The Bode plot of power stage, loop gain, PID compensator method B and phase are shown in Figure 3. Power Stage Loop Gain PID Phase of PID Fz Fpo Fo Fz2 Fp2 Figure 3 - Bode plot of buck converter with PID compensator method B. In the bold outline area of Figure 3, the PID compensator can be seen as lead-lag compensation. It is known that the lead-lag compensation can give a maximum phase boost at frequency. F FP2 FZ2 ---(25) Phase Boost Fzo Fp3 fs/2 If Rf Rf3</, then iteration may be required by going back and selecting a larger RC. Rev.. 8 0/07/02

10 APPLICATION NOTE AN-043 The maximum phase gain will be generated, that is: ( ) θmax Sin - FP2 - FZ2 ---(26) FP2 + FZ2 One of the design strategies is that we can set the maximum phase boost occurring at zero-cross over frequency, that is: FO FP2 FZ2 ---(27) Suppose θmargin is the desired phase margin and 60 is typical value. Parameter φ is the phase of power stage at zero crossover frequency. The required phase boost from PID compensator is set by: θmax θmargin - φ ---(28) Because φ 0 and θmax θmargin. The second zero of PID compensator can be calculated by: - SinθMAX FZ2 FO ---(29) + SinθMAX The second pole of compensator is given by: + SinθMAX FP2 FO ---(30) - SinθMAX The other zeroes and poles of compensator can be set by: Select FZ by FZ<FZ2 and FZ<FPO ---(3) FP3 FS/2 ---(32) The zero crossover frequency is determined by the following: 2π FO L COUT VOSC Cf3 ---(33) RC VIN D N448 L 5V C3 uf C4 uf D2 N448 C5 0.uF uh C2 2x 0TPB00ML, 00uF, 55mΩ C 47uF Tantalum C8 0.uF SS Vcc U Vc IRU3037 HDrv LDrv Q IRF7457 Q2 IRF7460 L2 3.3uH 0A C7 0x 22uF ESR, 0mΩ Each Comp Cc 3.3nF Gnd Cc2 82pF Rc 20K Fb 6.7K, % Cf3 nf Rf 27.4K Rf3 2.5K Figure 4 - Example of IRU3037 controlled buck converter with ceramic capacitors and PID compensator method B. Rev.. 0/07/02 9

11 APPLICATION NOTES AN ) Design Example of IRU3037 with Ceramic Capacitor and PID Method B Step - Collect system parameters in Figure 4 and determine switching frequency. Comparing with section 4.2 output capacitor is 0 ceramic cap with 22µF, 0mΩ ESR. Total capacitance is: Step 2 - Determine the power stage poles and zeros. Step 3 - Determine the zero crossover frequency and compensation type. Select zero crossover frequency as: fs 200KHz FO 20KHz 0 0 Because FPO< FO< fs/2 << FZO, we select the PID compensation based on lead lag (method B). Step 4 - Determine the desired location of zeros and poles for PID compensator. The desired phase margin is: Then: COUT 0 22µF 220µF ESR 0mΩ/0 mω FPO 2π L COUT FPO FZO FZO θmax θmargin 60 FZ2 FO FP2 FO 2π 3.3µH 220µF 5.9Hz 2π ESR COUT 2π mω 220µF 723KHz - SinθMAX + SinθMAX + SinθMAX - SinθMAX Select FZ<FZ2 and FZ<FPO 5.36KHz 74KHz Select FZ 0.5 FZ KHz 2.68KHz Select FP3 fs/2 00KHz Step 5 - Calculate the real parameters-resistor and capacitors of compensator. Select RC: RC >> 2/ 2/0.6µmho 3.3K Select RC 20K Calculate: CC Calculate: Calculate Cf3 based on location of zero crossover frequency: Calculate: Calculate: 2π FZ RC 2π 2.68KHz 20K Select CC 3.3nF CC2 2π FP3 RC Select CC2 82pF Cf3 2π FO L COUT RC Cf3 For DC regulation, calculate: 2π 00KHz 20K VOSC VIN 2π 20K 3.3µH 220µF.25V 20K 5V Select Cf3 nf Rf3 2π Cf3 FP2 Select Rf3 2.5K Rf Rf 2π Cf3 FZ2 - Rf3 3nF 80pF.4nF 2π nf 74KHz 2.5K 2π nf 5.36KHz - 2.5K 27.5K Select Rf 27.4K, %.25 Rf 27.4K 6.7K VO Select 6.7K, % Check: Rf Rf3 27.5K K.8K Rf Rf3 > /.6K Rev.. 0 0/07/02

12 APPLICATION NOTE AN-043 Conclusion The control loop design based on transconductance amplifier is proposed for buck converter. For most of buck converter with electrolytic capacitor and low performance tantalum capacitors, a simple type II (PI) compensator can be employed. For ceramic output capacitors, a type III or PID compensator is usually required. Although IRU3037 controlled circuits are taken as an example in this application note, the proposed design method also applies to other IC applications such as IRU3046 or IRU3055 controlled multi-phase buck converters. References [] D. Maksimovic, R. Erickson, Advances in Averaged Switch Modeling and Simulation 2.4MB slides from 3 hour tutorial seminar presented at the IEEE Power Electronics Specialists Conference, June 999, Charleston, South Carolina. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) Visit us at for sales contact information Data and specifications subject to change without notice. 02/0 Rev.. 0/07/02