Set Less Than (slt) Function. 32-bit ALU With 5 Functions

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1 Set Less Than (slt) Function slt function is defined as: if A < B, i.e. if A B < 0 A slt B = if A B, i.e. if A B 0 Thus, each 1-bit ALU should have an additional input (called Less ), that will provide results for slt function. This input has value 0 for all but 1-bit ALU for the least significant bit. For the least significant bit Less value should be sign of A B g. babic Presentation F bit ALU With 5 Functions B i n v e r t B i n v e r t O p e r a t i o n O p e r a t i o n 1-bit ALU1-ALU30 a 0 1 a 0 b 0 A L U 0 R e s u l t 0 C a r r y O u t R e s u l t b a 1 b 1 0 A L U 1 C a r r y O u t R e s u l t 1 C a r r y O u t 1-bit ALU31 the most significant bit a =0 B i n v e r t O p e r a t i o n b R e s u l t S e t Carry Out a 2 b 2 0 a 31 b 31 0 A L U 2 C a r r y O u t A L U 31 R e s u l t 2 R e s u l t 31 S e t O v e r f l o w O v e r f l o w d e t e c t i o n O v e r f l o w Carry Out slt function: Operation = 3 Binvert =1 1

2 32-bit ALU with 5 Functions and Zero Binvert Function Control lines Binvert (1 line) Operation (2 lines) and 0 00 or 0 01 add 0 10 subtract 1 10 slt 1 11 Carry Out g. babic Presentation F A nor B = A and B 32-bit ALU with 6 Functions Binvert Figure B.5.10 (Top) Function Ainvert Binvert Operation and or add subtract Carry Out slt nor Figure B.5.12 g. babic + Carry Out + Binvert 17 2

3 32-bit ALU Elaboration We have (so far) designed an ALU for most (integer) arithmetic and logic functions required by the core MIPS ISA 32-bit ALU with 6 functions omits support for: shift instructions XOR logic instruction integer multiply and divide instructions. Shift instructions: It would be possible to widen 1-bit ALU multiplexer to include 1-bit shift left and/or 1-bit shift right. Hardware designers created the circuit called a barrel shifter, which can shift from 1 to 31 bits in less time than it takes to add two 32-bit numbers. Thus, shifting is normally done outside the ALU. Integer multiply/divide is also usually done outside the ALU. We will next consider integer multiplication g. babic Presentation F 18 Multiplication is more complicated than addition: accomplished via shifting and addition More time and more area required We shall look at 3 hardware design versions based on an elementary school algorithm Example of unsigned multiplication: 5-bit multiplicand = bit multiplier = = But, this algorithm is very impractical to implement in hardware g. babic Presentation F 19 Reading Assignment: 3.4 Multiplication 3

4 Multiplication : Improved Algorithm The multiplication can be done with intermediate additions. The same example: multiplicand multiplier intermediate product add since multiplier bit= intermediate product shift multiplicand and add since multiplier bit= intermediate product shift multiplicand and no addition since multiplier bit=0 shift multiplicand and no addition since multiplier bit=0 shift multiplicand and add multiplier since bit= _ final result g. babic Presentation F 20 Multiplication Hardware: 1 st Version S t a r t M u l t i p l i e r 0 = 1 1. T e s t M u l t i p l i e r 0 M u l t i p l i e r 0 = 0 M u l t i p l i c a n d S h i f t l e f t 6 4 b i t s 1 a. A d d m u l t i p l i c a n d t o p r o d u c t a n d p l a c e t h e r e s u l t i n P r o d u c t r e g i s t e r b i t A L U M u l t i p l i e r S h i f t r i g h t 2. S h i f t t h e M u l t i p l i c a n d r e g i s t e r l e f t 1 b i t 3 2 b i t s 3. S h i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i t P r o d u c t 6 4 b i t s W r i t e C o n t r o l t e s t 3 2 n d r e p e t i t i o n? N o : < 3 2 r e p e t i t i o n s Y e s : 3 2 r e p e t i t i o n s Figure 3.5 D o n e Figure 3.6 g. babic Presentation F 21 4

5 Multiplication Hardware: 2 nd Version S t a r t M u l t i p l i c a n d M u l t i p l i e r 0 = 1 1. T e s t M u l t i p l i e r 0 M u l t i p l i e r 0 = b i t s 1 a. A d d m u l t i p l i c a n d t o t h e l e f t h a l f o f t h e p r o d u c t a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e P r o d u c t r e g i s t e r b i t A L U M u l t i p l i e r S h i f t r i g h t 3 2 b i t s 2. S h i f t t h e P r o d u c t r e g i s t e r r i g h t 1 b i t P r o d u c t S h i f t r i g h t W r i t e C o n t r o l t e s t 3. S h i f t t h e M u l t i p l i e r r e g i s t e r r i g h t 1 b i t 6 4 b i t s 3 2 n d r e p e t i t i o n? N o : < 3 2 r e p e t i t i o n s Y e s : 3 2 r e p e t i t i o n s D o n e g. babic Presentation F 22 Multiplication Hardware: 3 rd Version M u l t i p l i c a n d S t a r t 3 2 b i t s P r o d u c t 0 = 1 1. T e s t P r o d u c t 0 P r o d u c t 0 = b i t A L U 1 a. A d d m u l t i p l i c a n d t o t h e l e f t h a l f o f t h e p r o d u c t a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e P r o d u c t r e g i s t e r 2. S h i f t t h e P r o d u c t r e g i s t e r r i g h t 1 b i t P r o d u c t S h i f t r i g h t W r i t e C o n t r o l t e s t 6 4 b i t s 3 2 n d r e p e t i t i o n? N o : < 3 2 r e p e t i t i o n s Y e s : 3 2 r e p e t i t i o n s Figure 3.7 D o n e g. babic Presentation F 23 5

6 Real Numbers Representing real numbers ,155, x 10 4 Scientific notation: Single digit to the left of digital point: x 10 6 Normalized scientific notation: No leading zeros: x 10-9, but not x 10-8 Similar for binary: = 1.0 x 2 5 or 1.0 x normalized notation Reading Assignment: 3.6 g. babic Presentation F 24 Real Numbers Conversion from real binary to real decimal = since: = = and = = = Conversion from real decimal to real binary: = /2 = LSB = MSB 463/2 = = /2 = = /2 = = /2 = = /2 = = /2 = = /2 = = /2 = = /2 = = g. babic Presentation F 25 6

7 Floating Point Number Formats The term floating point number refers to representation of real binary numbers in computers. IEEE 754 standard defines standards for floating point representations Single precision: s E Fraction Double precision: s E Fraction 31 0 Fraction g. babic Presentation F 26 Converting to Floating Point 1. Normalize binary real number i.e. put it into the normalized form: (-1) s 1.Fraction * 2 Exp = (-1) * = (-1) * Load fields of single or double precision format with values from normalized form, but with the adjustment for E field. E = Exp = Exp for single precision E = Exp = Exp for double precision E is called a biased exponent - (-1) s 1.Fraction * 2 (Exp-Bias) g. babic Presentation F 27 7

8 Floating Point: Example 1 Find single and double precision of Normalized form: (-1) single precision: E = = double precision E = = g. babic Presentation F 28 Floating Point: Example 2 Find single and double precision of Normalized form: (-1) * 2 9 single precision E = = truncation rounding double precision E = = truncation rounding g. babic Presentation F 29 8

9 Converting to Floating Point: Conclusion Rules for biased exponents in single precision apply only for real exponents in the range [-126,127], thus we can have biased exponents only in the range [1,254]. The number 0.0 is represented as S=0, E=0 and Fraction=0. The infinite number is represented with E=255. There are some additional rules that are outside our scope. Find the largest (non-infinite) real binary number (by magnitude) which can be represented in a single precision. Floating point overflow Find the smallest (non-zero) real binary number (by magnitude) which can be represented in a single precision. Floating point underflow g. babic Presentation F 30 Floating Point Addition Figure 3.16 g. babic Presentation F 31 9

10 Arithmetic Unit for Floating Point Addition Figure 3.17 g. babic Presentation F 32 Booth s Algorithm S t a r t 1 b. Subtract multiplicand from the left half of t h e p r o d u c t a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e P r o d u c t r e g i s t e r Product[0-1] = 11 P r o d u c t [0-1] = T e s t P r o d u c t [0-1] P r o d u c t [0-1] = 00 or 11 M u l t i p l i c a n d 3 2 b i t s 1 a. A d d m u l t i p l i c a n d t o t h e l e f t h a l f o f t h e p r o d u c t a n d p l a c e t h e r e s u l t i n t h e l e f t h a l f o f t h e P r o d u c t r e g i s t e r b i t A L U 2. S h i f t t h e P r o d u c t r e g i s t e r r i g h t 1 b i t P r o d u c t S h i f t r i g h t W r i t e C o n t r o l t e s t Arithmetic 3 2 n d r e p e t i t i o n? N o : < 3 2 r e p e t i t i o n s 6 4 b i t s Y e s : 3 2 r e p e t i t i o n s D o n e g. babic Presentation F 33 10

11 Booth s Algorithm: Example 6-bit (signed) multiplicand = ; Note = bit (signed) multiplier = Product register assumed for step subtract (i.e. add ) shift step 1. ends add shift step 2. ends subtract shift step 3. ends 11 - no arithmetic shift step 4. ends 11 - no arithmetic shift step 5. ends g. babic Presentation F 34 Booth s Algorithm: Example (continued) shift step 5. ended add shift step 6. ends Result = = - (256+63) = g. babic Presentation F 35 11