Arithmetic Functions and Circuits

Transcription

1 Introduction to Digital Logic Prof. Nizamettin ADIN Course Outline. Digital Computers, Number ystems, Arithmetic Operations, Decimal, Alphanumeric, and Gray Codes 2. Binary Logic, Gates, Boolean Algebra, tandard Forms 3. Circuit Optimization, Two-Level Optimization, Map Manipulation, Multi-Level Circuit Optimization 4. Additional Gates and Circuits, Other Gate Types, Exclusive-OR Operator and Gates, High-Impedance Outputs 5. Implementation Technology and Logic Design, Design Concepts and Automation, The Design pace, Design Procedure, The major design steps 6. Programmable Implementation Technologies: Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic,Technology mapping to programmable logic devices 7. Combinational Functions and Circuits 8. Arithmetic Functions and Circuits 9. equential Circuits torage Elements and equential Circuit Analysis 0. equential Circuits, equential Circuit Design tate Diagrams, tate Tables. Counters, register cells, buses, & serial operations 2. equencing and Control, Datapath and Control, Algorithmic tate Machines (AM) 3. Memory Basics 2 Introduction to Digital Logic Lecture 8 Arithmetic Functions and Circuits Overview Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors igned binary numbers igned binary addition and subtraction Overflow Binary multiplication Other arithmetic functions Design by contraction 3 4 Iterative Combinational Circuits Block Diagram of a D Iterative Array A n-b n- A B A 0 B 0 Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block for subfunction and repeat to obtain functional block for overall function Cell - subfunction block Iterative array - an array of interconnected cells An iterative array can be in a single dimension (D) or multiple dimensions n- 2 n Cell n- n- 2 Cell n C n- C Cell 0 Example: n = 32 Number of inputs =? Truth table rows =? Equations with up to? input variables Equations with huge number of terms Design impractical! Iterative array takes advantage of the regularity to make design feasible C reserved.

2 Functional Blocks: Addition Functional Block: Half-Adder Binary addition used frequently Addition Development: Half-Adder (HA), a 2-input bit-wise addition functional block, Full-Adder (FA), a 3-input bit-wise addition functional block, Ripple Carry Adder, an iterative array to perform binary addition, and Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance. A 2-input, -bit width binary adder that performs the following computations: C A half adder adds two bits to produce a two-bit sum The sum is expressed as a sum bit, and a carry bit, C The half adder can be specified as a truth table for and C C Logic implification: Half-Adder Five Implementations: Half-Adder The K-Map for, C is: This is a pretty trivial map! By inspection: = + = = ( + ) ( + ) and C = C = (( ) ) These equations lead to several implementations C We can derive following sets of equations for a half-adder: (a) = + (d) = ( + ) C C = C = ( + (b) = ( + ) ( + ) (e) C = C = ) = ( c) = ( C+ ) C = (a), (b), and (e) are OP, PO, and OR implementations for. In (c), the C function is used as a term in the AND-NOR implementation of, and in (d), the C function is used in a PO term for. 9 0 Implementations: Half-Adder Functional Block: Full-Adder The most common half adder implementation is (e) = C = A NAND only implementation is: = ( + ) C C = (( ) ) C C A full adder is similar to a half adder, but includes a carryin bit from lower stages. Like the half-adder, it computes a sum bit, and a carry bit, C. For a carry-in (Z) of 0, it is the same as the half-adder: For a carry- in (Z) of : Z C Z C reserved. 2

3 Logic Optimization: Full-Adder Equations: Full-Adder Full-Adder Truth Table: Full-Adder K-Map: Z C Z Z C From the K-Map, we get: = Z + Z + Z + Z C = + Z + Z The function is the three-bit OR function (Odd Function): = Z The Carry bit C is if both and are (the sum is 2), or if the sum is and a carry-in (Z) occurs. Thus C can be re-written as: C = + ( ) Z The term is carry generate. The term is carry propagate. 3 4 Implementation: Full Adder Binary Adders Full Adder chematic Here,, and Z, and C (from the previous pages) are A, B, C i and C o, respectively. Also, G = generate and P = propagate. Note: This is really a combination of a 3-bit odd function (for )) and Carry logic (for C o ): (G = Generate) OR (P =Propagate AND C i = Carry In) Co = G + P Ci C i+ G i A i B i i P i C i To add multiple operands, we bundle logical signals together into vectors and use functional blocks that operate on the vectors Example: 4-bit ripple carry adder: Adds input vectors A(3:0) and B(3:0) to get a sum vector (3:0) Note: carry out of cell i becomes carry in of cell i + Description ubscript Name Carry In 0 0 C i Augend 0 A i Addend 0 0 B i um 0 i Carry out 0 0 C i bit Ripple-Carry Binary Adder A four-bit Ripple Carry Adder made from four - bit Full Adders: B 3 A 3 B 2 A 2 B A B 0 A 0 Carry Propagation & Delay One problem with the addition of binary numbers is the length of time to propagate the ripple carry from the least significant bit to the most significant bit. The gate-level propagation path for a 4-bit ripple carry adder of the last example: A 3 B3 A 2 A A 0 B 2 B B 0 FA C 3 C 2 C FA FA FA C 0 C 3 C 2 C C0 C 4 C Note: The "long path" is from A 0 or B 0 though the circuit to reserved. 3

4 Carry Lookahead Given tage i from a Full Adder, we know that there will be a carry generated when A i = B i = "", whether or not there is a carry-in. Alternately, there will be A i B i a carry propagated if the G i half-sum is "" and a carry-in, C i occurs. These two signal conditions P i are called generate, denoted as G i, and propagate, denoted as P i respectively and are identified in the circuit: C i+ i C i Carry Lookahead (continued) In the ripple carry adder: Gi, Pi, and i are local to each cell of the adder Ci is also local each cell In the carry lookahead adder, in order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells Defining the equations for the Full Adder in term of the P i and G i : P i = Ai Bi Gi = Ai Bi i = Pi Ci Ci+ = Gi + Pi Ci 9 20 Carry Lookahead Development C i+ can be removed from the cells and used to derive a set of carry equations spanning multiple cells. Beginning at the cell 0 with carry in C 0 : C = G 0 + P 0 C 0 C 2 = G + P C = G + P (G 0 + P 0 C 0 ) = G + P G 0 + P P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 (G + P G 0 + P P 0 C 0 ) = G 2 + P 2 G + P 2 P G 0 + P 2 P P 0 C 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G 0 + P 3 P 2 P P 0 C 0 Group Carry Lookahead Logic Figure 5-6 in the text shows the implementation of these equations for four bits. This could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible. Instead, the concept is extended another level by considering group generate (G 0-3 ) and group propagate (P 0-3 ) functions: G0 3 = G3 + P3 G2 + P3 P2 G + P3 P2 P P0 G0 P0 3 = P3 P2 P P0 Using these two equations: C4 = G0 3 + P0 3 C0 Thus, it is possible to have four 4-bit adders use one of the same carry lookahead circuit to speed up 6-bit addition 2 22 Unsigned ubtraction Algorithm: ubtract the subtrahend N from the minuend M If no end borrow occurs, then M N, and the result is a non-negative number and correct. If an end borrow occurs, the N > M and the difference M N + 2 n is subtracted from 2 n, and a minus sign is appended to the result. Examples: ( ) reserved. 4

5 Unsigned ubtraction (continued) The subtraction, 2 n N, is taking the 2 s complement of N To do both unsigned addition and unsigned A subtraction requires: Quite complex! Borrow Binary adder Goal: hared simpler logic for both addition and subtraction Complement Introduce complements as an approach 0 ubtract/add Quadruple 2-to- multiplexer Result B Binary subtractor elective 2's complementer Complements Two complements: Diminished Radix Complement of N (r ) s complement for radix r s complement for radix 2 Defined as (r n ) Ν Radix Complement r s complement for radix r 2 s complement in binary Defined as r n N ubtraction is done by adding the complement of the subtrahend If the result is negative, takes its 2 s complement Binary 's Complement For r = 2, N = 000 2, n = 8 (8 digits): (r n ) = = or 2 The 's complement of is then: ince the 2 n factor consists of all 's and since 0 = and = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT). Binary 2's Complement For r = 2, N = 000 2, n = 8 (8 digits), we have: (r n ) = or The 2's complement of 000 is then: Note the result is the 's complement plus, a fact that can be used in designing hardware Alternate 2 s Complement Method ubtraction with 2 s Complement Given: an n-bit binary number, beginning at the least significant bit and proceeding upward: Copy all least significant 0 s Copy the first Complement all bits thereafter. 2 s Complement Example: Copy underlined bits: 00 and complement bits to the left: 0000 For n-digit, unsigned numbers M and N, find M N in base 2: Add the 2's complement of the subtrahend N to the minuend M: M + (2 n N) = M N + 2 n If M > N, the sum produces end carry r n which is discarded; from above, M N remains. If M < N, the sum does not produce an end carry and, from above, is equal to 2 n ( N M ), the 2's complement of ( N M ). To obtain the result (N M), take the 2's complement of the sum and place a to its left reserved. 5

6 Unsigned 2 s Complement ubtraction Example Unsigned 2 s Complement ubtraction Example 2 Find s comp The carry of indicates that no correction of the result is required. Find s comp The carry of 0 indicates that a correction of the result is required. Result = (000000) 2 s comp 3 32 ubtraction with Diminished Radix Complement Unsigned s Complement ubtraction - Example For n-digit, unsigned numbers M and N, find M N in base 2: Add the 's complement of the subtrahend N to the minuend M: M + (2 n N) = M N + 2 n If M > N, the result is excess by 2 n. The end carry 2 n when discarded removes 2 n, leaving a result short by. To fix this shortage, whenever and end carry occurs, add in the LB position. This is called the end-around carry. If M < N, the sum does not produce an end carry and, from above, is equal to 2 n ( N M ), the 's complement of ( N M ). To obtain the result (N M), take the 's complement of the sum and place a to its left. Find s comp The end-around carry occurs Unsigned s Complement ubtraction Example 2 Find s comp The carry of 0 indicates that a correction of the result is required. Result = (000000) s comp igned Integers Positive numbers and zero can be represented by unsigned n-digit, radix r numbers. We need a representation for negative numbers. To represent a sign (+ or ) we need exactly one more bit of information ( binary digit gives 2 = 2 elements which is exactly what is needed). ince computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit: s a n 2 a 2 a a 0 where: s = 0 for Positive numbers s = for Negative numbers and a i = 0 or represent the magnitude in some form reserved. 6

7 igned Integer Representations igned Integer Representation Example igned-magnitude here the n digits are interpreted as a positive magnitude. igned-complement here the digits are interpreted as the rest of the complement of the number. There are two possibilities here: igned 's Complement Uses 's Complement Arithmetic igned 2's Complement Uses 2's Complement Arithmetic r =2, n=3 Number ign -Mag. 's Comp. 2's Comp igned-magnitude Arithmetic If the parity of the three signs is 0:. Add the magnitudes. 2. Check for overflow (a carry out of the MB) 3. The sign of the result is the same as the sign of the first operand. If the parity of the three signs is :. ubtract the second magnitude from the first. 2. If a borrow occurs: take the two s complement of result and make the result sign the complement of the sign of the first operand. 3. Overflow will never occur. ign-magnitude Arithmetic Examples Example : (+2) +0 0 (+5) 0 (7) (borrow) Example 2: (+2) + 0 +(-5) 0 => 2s comp => 0 (-3) Example 3: 0 0 (-2) 0 0 -(5) (-7) igned-complement Arithmetic igned 2 s Complement Examples Addition:. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end-around carry ('s Complement). 2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred. 3. The sign of the result is computed in step. ubtraction: Form the complement of the number you are subtracting and follow the rules for addition. Example : 0 (-3) +0 0 (+3) (0) Example 2: 0 (-3) 0 (-3) 0 0 -(+3) 0 (-3) 0 0 (-6) 0 0 (-6) 4 42 reserved. 7

8 igned s Complement Examples Example : 0 (-2) +0 0 (+3) Example 2: 0 (-2) => => (+3) 0 0 (-5) 2 s Complement Adder/ubtractor ubtraction can be done by addition of the 2's Complement.. Complement each bit ('s Complement.) 2. Add to the result. The circuit shown computes A + B and A B: For =, subtract, the 2 s complement B 3 A 3 B 2 A 2 B A B 0 A 0 of B is formed by using ORs to form the s comp and adding the applied to C 0. For = 0, add, B is C 3 FA FA FA FA passed through unchanged C 4 3 C 2 C C Overflow Detection Overflow occurs if n + bits are required to contain the result from an n-bit addition or subtraction Overflow can occur for: Addition of two operands with the same sign ubtraction of operands with different signs igned number overflow cases with correct result sign Detection can be performed by examining the result signs which should match the signs of the top operand Overflow Detection igned number cases with carries C n and C n shown for correct result signs: igned number cases with carries shown for erroneous result signs (indicating overflow): implest way to implement overflow V = C n + C n This works correctly only if s complement and the addition of the carry in of is used to implement the complementation! Otherwise fails for Binary Multiplication Review - Decimal Example: (237 49) 0 The binary digit multiplication table is trivial: (a b) b = 0 b = a = a = 0 This is simply the Boolean AND function. Form larger products the same way we form larger products in base 0. Partial products are: 237 9, 237 4, and 237 Note that the partial product summation for n digit, base numbers requires adding up to n digits (with carries) Note also n m digit multiply generates up to an m + n digit result reserved. 8

9 Binary Multiplication Algorithm We execute radix 2 multiplication by: Computing partial products, and Justifying and summing the partial products. (same as decimal) To compute partial products: Multiply the row of multiplicand digits by each multiplier digit, one at a time. With binary numbers, partial products are very simple! They are either: all zero (if the multiplier digit is zero), or the same as the multiplicand (if the multiplier digit is one). Note: No carries are added in partial product formation! Example: (0 x 0) Base 2 Partial products are: 0, 0, and 0 0 Note that the partial product summation for n digit, base 2 numbers requires adding up to n digits (with carries) in a column Note also n m digit multiply generates up to an m + n digit result (same as decimal) Multiplier Boolean Equations We can also make an n m block multiplier and use that to form partial products. Example: 2 2 The logic equations for each partial-product binary digit are shown below: We need to "add" the columns to get the product bits P0, P, P2, and P3. Note that some columns may generate carries. b b 0 a a 0 (a 0. b ) (a 0. b 0 ) + (a. b ) (a. b 0 ) P 3 P 2 P P 0 Multiplier Arrays Using Adders An implementation of the 2 2 A multiplier array is 0 shown: A B B 0 HA HA B B 0 C 3 C 2 C C Multiplier Using Wide Adders A more structured way to develop an n m multiplier is to sum partial products using adder trees The partial products are formed using an n m array of AND gates Partial products are summed using m adders of width n bits Example: 4-bit by 3-bit adder Following figure shows a 4 3 = 2 element array of AND gates and two 4-bit adders reserved. 9

10 Cellular Multiplier Array Another way to implement multipliers is to use an n m cellular array structure of uniform elements as shown: Each element computes a single bit product equal to a i b j, and implements a single bit full adder Column um from above Cell [ j, k ] pp [ j, k ] b[ k ] a[ j ] A B Co Ci FA Carry [ j, k ] Carry [ j, (k - )] Column um to below Other Arithmetic Functions Convenient to design the functional blocks by contraction - removal of redundancy from circuit to which input fixing has been applied Functions Incrementing Decrementing Multiplication by Constant Division by Constant Zero Fill and Extension Design by Contraction Contraction is a technique for simplifying the logic in a functional block to implement a different function The new function must be realizable from the original function by applying rudimentary functions to its inputs Contraction is treated here only for application of 0s and s (not for and ) After application of 0s and s, equations or the logic diagram are simplified by using rules given on pages of the text. Design by Contraction Example Contraction of a ripple carry adder to incrementer for n = 3 et B = 00 The middle cell can be repeated to make an incrementer with n > Incrementing & Decrementing Multiplication/Division by 2 n Incrementing Adding a fixed value to an arithmetic variable Fixed value is often, called counting (up) Examples: A +, B + 4 Functional block is called incrementer Decrementing ubtracting a fixed value from an arithmetic variable Fixed value is often, called counting (down) Examples: A, B 4 Functional block is called decrementer (a) Multiplication by 00 hift left by 2 C5 (b) Division by 00 hift right by 2 Remainder preserved B3 0 C3 C4 B2 0 C2 B3 B2 B B0 0 0 C3 C2 C C0 (a) B B0 C C0 C 2 C 2 2 (b) reserved. 0

11 Multiplication by a Constant Multiplication of B(3:0) by 0 ee text Figure 5-3 (a) for contraction B 3 Carry output C 6 B 2 B C 5 B 0 4-bit Adder C B 3 B 2 B B 0 um C 3 C 2 C C 0 Zero Fill Zero fill - filling an m-bit operand with 0s to become an n-bit operand with n > m Filling usually is applied to the MB end of the operand, but can also be done on the LB end Example: 00 filled to 6 bits MB end: LB end: Extension Extension - increase in the number of bits at the MB end of an operand by using a complement representation Copies the MB of the operand into the new positions Positive operand example extended to 6 bits: Negative operand example - 00 extended to 6 bits: reserved.