Class Notes (Part 2) CS201. Dr. C. N. Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2

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1 Class Notes (Part 2) CS201 Dr. C. N. Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2

2 C. N. Zhang, CS II. COMPUTER ARITHMETIC 1 The Arithemetic and Logic Unit (ALU) ALU is a part of the computer that actually performs arithmetic and logic operations. 1. Logic operations: include AND, OR, NOT, XOR. 2. Arithmetic operations: include ADD, SUB, MULT, DIV. Control Unit Registers ALU Flags Registers Figure 1: Arithmetic and logic unit. 2 Number Representations Unsigned n-bit binary number representation: B = (B n;1 B n;2 ::: B 1 B 0 ) = B n;1 2 n;1 + B n;2 2 n;2 + :::+ B 1 2+B 0 Example: For n =4,B 3 B 2 B 1 B 0 = 1001 = 9 Signed n-bit binary number representations. In general, there are three signed integer representations: 1. sign and magnitude representation, 2. 1's complement representation, and 3. 2's complement representation. 2.1 Sign and Magnitude Representation Use the leftmost bit (B n;1 ) as the sign bit, the rest of the bits, i.e., the other (n ; 1) bits, represent the magnitude. B =(;1) B n;1 B n;2 B n;3 :::B 1 B 0 The range is [;(2 n;1 ; 1) 2 n;1 ; 1]. Example: For n = 4, ;1 = 1001 and +5 = 0101

3 C. N. Zhang, CS Drawbacks: 1. ADD and SUB operations are complex and slow. For example, the addition S = A + B can be described by the following procedure: (a) S = A n;1 B n;1 (checks for signs of A and B). (b) If S = 0 then S n;1 = A n;1 and S n;2 :::S 0 = A n;2 :::A 0 + B n;2 :::B 0, Else if jaj;jbj 0 then S n;1 = A n;1 and S n;2 :::S 0 = A n;2 :::A 0 ; B n;2 :::B 0, Else S n;1 = B n;1 and S n;2 :::S 0 = B n;2 :::B 0 ; A n;2 :::A 0. Example: A = 0001(+1) and B =1110(;6) (a) S =1 (b) Since jbj jaj, S 3 =1 S 2 S 1 S 0 =110; 001 = There are two zero representations (more hardware is required to detect a zero): +0 = 00 :::0 and ;0 =10::: 's Complement Representation Let B = B n;1 :::B 1 B 0 be an unsigned binary number. The 1's complement ofb is Example: For n = 4, = 2 n ; 1 ; B = B n;1 B n;2 :::B 1 B 0 1's complement of 1001(9) = 's complement of 0101(5) = 1010 Let B be a signed integer. The 1's complement representation of B is Example: For n = 4, = ( B, if B 0 1's complement ofjbj, if B<0 1's complement representation of 5 = 's complement representation of -5 = 1011 The range of 1's complement representation (n-bit): [;(2 n;1 ; 1) 2 n;1 ; 1]

4 C. N. Zhang, CS Let A and B be two numbers in 1's complement representation. The addition procedure for integers in 1's complement representation is as follows: Procedure: 1. S = A + B 2. If there is an end-carry in step 1, then S = S +1 Example-1: For n = 5, A = 00111(7) and B = 00101(5) 1. S = = Result: 01100(12) Example-2: For n = 5, A = 00111(7) and B = 11010(;5) 1. S = = 1 {z} end;carry 2. S = = Result: 00010(2) Example-3: For n =5,A = 11000(;7) and B = 00101(5) 1. S = = Result: 11101(;2) Let A and B be two numbers in 1's complement representation. The subtraction procedure for integers in 1's complement representation is as follows: Procedure: 1. S = A+ 1's complement ofb 2. If there is an end-carry in step 1, then S = S +1 Example-1: For n = 5, A = 00111(7) and B = 00101(5) 1. S = = 1 {z} end;carry 2. S = = Result: 00010(2) Example-2: For n =5,A = 11000(;7) and B = 00101(;5) 1. S = = 1 {z} end;carry 2. S = = Result: 10011(;12) 10010

5 C. N. Zhang, CS Hardware implementation of addition and subtraction in 1's complement representation. For (n = 4), let A = A 3 A 2 A 1 A 0, B = B 3 B 2 B 1 B 0,ands be a control bit. s = ( 1 do subtraction 0 do addition Consider both step 1 of addition and subtraction procedures. We have X i = A i and Y i = B i s + B i s for i = , where X i and Y i are the i th inputs of a 4-bit adder. Y i = B i s + B i s can be implemented by anxor gate. Step 2 of both procedures can be implemented by connecting the end-carry (C 4 ) to the initial carry (C 0 ). The addersubtracter circuit is shown below. B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 s Y 3 X 3 Y 2 X 2 Y 1 X 1 Y 0 X 0 C 4 C 3 C 2 C 1 FA FA FA FA C 0 S 3 S 2 S 1 S 0 Figure 2: Logic diagram of adder-subtracter for 1's complement. Overow detection. An overow occurs if the result of an addition or a subtraction is greater than the largest number (i.e., 2 n;1 ; 1) or is less than the smallest number (i.e., ;2 n;1 ; 1) in the n-bit 1's complement representation. Overow rule: if two positive ortwo negative numbers are added, an overow occurs if and only if the result has the opposite sign. Example-1: For n =4,A = 0111(7), and B = 0101(5), A + B = = 1100 overflow Example-2: For n =4,A = 1000(;7), and B = 0101(5), A ; B = = 1 {z} end;carry ) A ; B =0011 overflow 0010

6 C. N. Zhang, CS Let X = X n;1 :::x 0, Y = Y n;1 :::y 0,andS = S n;1 :::S 0 be the two inputs and the result, respectively. Logic expression of overow in 1's complement representation is overflow = X n;1 Y n;1 S n;1 + X n;1 Y n;1 S n;1 Overow ag: A D ip-op, called V, is used to represent the overow event. Y n-1 X n-1 S n-1 Clock D V C Figure 3: Logic circuit for overow expression 's Complement Representation Let B = B n;1 :::B 1 B 0 be an unsigned binary number. The 2's complement ofb Example: For n = 4, = 2 n ; B = B n;1 B n;2 :::B 1 B 's complement of 1001(9) = 's complement of 0101(5) = 1011 Let B be a signed integer. The 2's complement representation of B is Example: For n = 4, = ( B, if B 0 2's complement ofjbj, if B<0 2's complement of5 = 's complement of-5 = 1011 The range of 2's complement representation (n-bit): [;2 n;1 2 n;1 ; 1]

7 C. N. Zhang, CS Table 1: Ranges of number representations. B 3 b 2 b 1 b 0 Sign-magnitude 1's complement 2's complement Let A and B be two numbers in 2's complement representation. The addition procedure for integers in 2's complement representation is as follows: Procedure: 1. S = A + B (ignore the end-carry) Example: For n =5,A = 00111(7), and B = 11011(;5) 1. S = = 1 {z} Result: 00010(2) end;carry Let A and B be two numbers in 2's complement representation. The subtraction procedure for integers in 2's complement representation is as follows: Procedure: 1. S = A+ 2's complement ofb (ignore the end-carry) Example: For n = 5, A = 11000(;7) and B = 00101(5) 1. S = = 1 {z} Result: 10100(;12) end;carry 10100

8 C. N. Zhang, CS Hardware implementation of addition and subtraction is 2's complement representation. Let A = A 3 A 2 A 1 A 0, B = B 3 B 2 B 1 B 0,ands be a control bit. s = ( 1 do subtraction 0 do addition B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 s FA C 3 FA C 2 FA C 1 FA C 0 C 4 S 3 S 2 S 1 S 0 Figure 4: Logic diagram of adder-subtracter for 2's complement. Overow detection: the overow rule is the same as that of 1's complement representation. Comparison between 1's and 2's complement representations: 1. 1's complement is easier and faster than 2's complement. 2. Addition and subtraction procedures in 1's complement representation require an extra step if there is an end-carry. 3. There are two zeros (i.e., 00 :::0 and 11:::1) in 1's complement representation, but only one zero (i.e., 00 :::0) in 2's complement representation. 2.4 Other Flags and Their Denitions Each ag is implemented by a D ip-op which is set or cleared by arithmetic operation. The number of ags vary from computer to computer which are used for conditional branch instructions. Other ags in PDP-11: N : is set to 1 if the result is negative, otherwise it is set to 0. Z : is set to 1 if the result is 0, otherwise it is set to 0. C : is set to 1 if an end-carry occurs, otherwise it is set to 0.

9 C. N. Zhang, CS Logic Design For Fast Adder In the following, we consider the adder for addition and subtraction in 2's complement representation. 3.1 Time Delay of Ripple-Carry Adder Time delay of a combinational circuit: is counted by adding up the logic gate delays along the longest path through the network. Time delay of Ripple-Carry Adder: the longest path is considered as the path on which the carry propagates from the inputs X 0, Y 0,andC 0 of the least signicant bit (LSB) to the outputs S n;1 of the most signicant bit (MSB). X n-1 Y n-1 X 1 Y 1 X 0 Y 0 C n Adder C n-1 C 2 Adder C 1 Adder C 0 S n-1 S 1 S 0 Most significant bit (MSB) position Least significant bit (LSB) position Figure 5: Ripple-carry adder. Example: Find time delay of a 17-bit adder. Assume that each logic gate delay is 10 ns. Referring to Fig. 6, the time delay from X i, Y i,andc i to S i is 30 ns. The time delay from X i, Y i and C i to C i+1 is 20 ns. ) Total time delay is = 350 ns In general, the time delay ofann-bit ripple-carry adder is (n ; 1) X i Y i C i Y i X i Y i C i C i X i Y i X i X i Y i C i S i C i+1 Adder C i C i X i C i+1 X i Y i C i S i Y i Figure 6: Logic circuit of one bit adder.

10 C. N. Zhang, CS Carry Lookahead Adder (CLA) Carry generation and carry propagation: S i = X i Y i C i + X i Y i C i + X i Y i C i + X i Y i C i C i+1 = X i Y i +(X i + Y i )C i Let G i = X i Y i be the i th bitofthe carry generate function and P i = X i + Y i be the i th bit of the carry propagation function, i =0 1 ::: n; 1. We have: C i+1 = G i + P i C i = G i + P i (G i;1 + P i;1 C i;1 ) = G i + P i G i;1 + P i P i;1 C i;1 Thus, for n =4, = G i + P i G i;1 + :::+ P i P i;1 :::P 0 C 0 C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 Logic circuit of carry-lookahead adder (4-bit): B 3 P 3 A 3 A 2 G 3 B 2 P 2 A 1 G 2 B 1 P 1 G 1 B 0 P 0 Look-ahead carry generator C 3 P 3 C 2 P 2 C 1 P 1 S 3 S 2 S 1 A 0 G 0 P 0 S 0 C 0 C 0 Figure 7: Logic diagram of 4-bit full adder with look-ahead carry.

11 C. N. Zhang, CS C 3 P 2 G 2 P 1 G 1 C 2 P 0 G 0 C 0 C 1 Figure 8: Logic diagram of carry-lookahead generator. Time delay of carry-lookahead adder (n-bit): Assume that time delay of each gate is 10 ns. { Time delay fromc 0, X i,andy i to G i and P i is 10 ns. { Time delay fromg i and P i to C i+1 is 20 ns. { Time delay fromc i to S i is 10 ns. ) Total time delay is 50 ns. 4 Multiplication 4.1 Multiplication for Unsigned Binary Numbers Pencil and paper approach: Example: Note: it requires a 2n-bit adder x Multiplicand (11) Multiplier (13) Partial Products Product (143) Figure 9: Multiplication by pencil-paper approach.

12 C. N. Zhang, CS Hardware Approach: { Algorithm (M Q): 1. A (n-bit) = 0 C (1-bit) = 0 Counter = n 2. Repeate the following steps until Counter = 0: (a) If Q 0 (LSB of Q) = 1, then CA = A + M (b) Shift C, A, and Q one bit to the right, simultaneously. (c) Counter = Counter ; 1 3. Halt. The result is in A, Q. { Flowchart: START C, A 0 M Multiplicand Q Multiplier Count n No Q = 1? 0 Yes C, A A + M Shift C, A, Q Count Count - 1 No Count = 0? Yes END Figure 10: Flowchart of multiplication algorithm using hardware approach. { Example: M = 1011 and Q = 1101 Table 2: Step by step multiplication using hardware approach. C A Q Initial Values Add First Cycle Shift Shift Second Cycle Add Third Cycle Shift Add Fourth Cycle Shift (Product in A Q)

13 C. N. Zhang, CS {Implementation: Basic Components: 1. Register M (n-bit): stores the multiplicand (M). 2. n-bit Adder: performs addition when the LSB of Q (Q 0 )isone. 3. Register Q (n-bit): stores the multiplier Q. 4. Register A (n-bit): initially is zero, holds the partial product. 5. Register C (1-bit): holds the end-carry of the adder. C, A, and Q can be shifted to the right, simultaneously. 6. Control Logic: includes a count ofdlog 2 ne bits to control the iterations and the logic circuits to control shift and addition operations. Hardware Implementation: Multiplicand M n-1 M 0 n-bit Adder Add Shift and Add Control Logic Shift Right C A n-1 A 0 Q n-1 Q 0 Multiplier Figure 11: Logic circuit for multiplication algorithm using hardware approach. 4.2 Multiplication for Signed Binary Numbers in 2's Complement Representation Approach-1: by modifying the multiplication algorithm for unsigned numbers. 1. S = M n;1 Q n;1 (save sign of M Q) 2. If M<0, then compute the 2's complement ofm 3. If Q<0, then compute the 2's complement ofq 4. Apply multiplication algorithm for unsigned integers 5. If S = 1, then compute the 2's complement of AQ through the following steps: (a) Set C =0 (b) Q = Q +1 (c) A = A + C (C is the end-carry of step 5.b)

14 C. N. Zhang, CS Approach-2: Booth Algorithm. { Algorithm: 1. A (n-bit) = 0 Q ;1 =0 Counter = n 2. Repeat the following steps until Counter = 0: (a) If Q 0 Q ;1 = 10, then A = A ; M (b) If Q 0 Q ;1 = 01, then A = A + M (c) Arithmetic shift A and Q one bit right. 3. The result is in A and Q. Note: Arithmetic shift right (ashr) of A (A n;1 :::A 0 ) is dened as follows: ashr(a) =A n;1 A n;1 A n;2 :::A 1 Example: ashr(0101) = 0010 and ashr(1010) = 1101 { Flowchart: START A 0 M Q Count, Q -1 0 Multiplicand Multiplier n = 10 Q 0 Q -1? = 01 A A - M = 00 = 11 A A + M ashr A and Q Count Count - 1 No Count = 0? Yes END Figure 12: Flowchart of multiplication using Booth algorithm.

15 C. N. Zhang, CS { Example: M = and Q =10011 Table 3: Multiplication using Booth algorithm. A Q Q ;1 Count Operation Initial Sub Ashift Ashift Add Ashift Ashift Sub Ashift { Hardware Implementation: Multiplicand M n-1 M 0 n-bit Adder Add/Sub Control Logic Ashr A n-1 A 0 Q n-1 Q 0 Multiplier Q -1 Figure 13: Logic diagram for multiplication using Booth algorithm.

16 C. N. Zhang, CS Division of Unsigned Binary Integers 5.1 Pencil and Paper Approach Divisor ) Partial Remainders Quotient Dividend Remainder 5.2 Harwdare Approach Figure 14: Division by pencil-paper approach. Let Q (n-bit) be the dividend and M (n-bit) be the divisor. Assuming that Q<M,nd quotient and remainder of Q 2 n div M. Algorithm: 1. A (n + 1-bit) = 0 Counter = n 2. Repeat the following steps until Count =0: (a) Shift AQ together one bit to the left. (b) A = A ; M (c) If A n (MSB of A) = 1, then Q 0 (LSB of Q) = 0 and A = A + M (d) Count = Count ; 1 3. Halt. Quotient isinq and remainder is in A. Flowchart: START A 0 M Divisor Q Dividend Count n Shl A and Q A A - M No A = 1? Yes Q 0 1 Q 0 0, A A + M Count Count - 1 No Count = 0? Yes END Figure 15: Flowchart of division by hardware approach.

17 C. N. Zhang, CS Example: 1 1) Initially Shift Subtract Set q 0 Restore Shift Subtract Set q Restore Shift Subtract Set q Shift Subtract Set q Restore First cycle Second cycle Third cycle Fourth cycle Remainder Quotient Figure 16: Step by step example of division by hardware approach. Hardware Implementation: Shift left A n A n-1 A 0 Q n-1 Q n-2 Q 0 A Dividend Q Quotient setting n + 1 bit Adder Add / Subtract Control Sequencer 0 m n-1 m 0 Divisor M Figure 17: Logic diagram of division by hardware approach.

18 C. N. Zhang, CS Floating-Point Numbers and Operations Basic component of oating-point numbers: Sign: + or - Signicand: S Exponent: E Exponent base: B S B E Normalized oating-point number: A oating-point number (not zero) is normalized if the most signicant digit of the fraction (signicand) is nonzero. Normalized number provides the maximum possible precision for the oating-point number. Biased (excess) exponent: The exponent representation employed in most computers is known as a biased (or excess) representation. The bias is an excess number which is added to the exponent so that internally all exponents become positive. 6.1 IBM-370 Format Exponent base: B =16. There are 32-bit, 64-bit, and 128-bit formats. Biased (excess) number is 64. S Exponent Significand S Exponent S Exponent Significand Significand Significand Figure 18: IBM System/370 formats. 6.2 IEEE Standard 754 There are 32-bit and 64-bit formats. Exponent base: B =2. Biased number is 127 (32-bit format). Mantissa fraction: M =1:f, where f>0and '1' does not appear in the format.

19 C. N. Zhang, CS bits S E M Value represented = + 1.M x 2 E Sign of number: 0 = + 1 = - 8-bit signed exponent in excess-127 representation 23-bit mantissa fraction (a) Single precision Value represented = x 2-87 (a) Example of a single precision number 64 bits S E M Value represented = + 1.M x 2 E Sign 11-bit 52-bit excess-1023 mantissa fraction exponent (a) Double precision Figure 19: IEEE Standard 745 formats. Example: Represent ;2 in IBM-370 and IEEE-754 formats (32-bit). 1. Separate fraction and integer parts of the number: ;2 =81:75 2. Convert the integer and the fraction into the binary representation. integer: (81) 10 = ( ) 2 fraction: (0:75) 10 =(0:11) 2 81:75 = ( :11) 2 =0: Normalize and compute biased exponent: For IBM-370, 32-bit format: 0: =0: =0: E 0 = E + 64 = 66 = IBM-370 format: :::0 For IEEE-754, 32-bit format: 0: =1: E 0 = E = 133 = IEEE-754 format: :::0

20 C. N. Zhang, CS Floating-Point Arithmetic Operations Floating-point arithmetic operations such as oating-point addition, subtraction, multiplication, and division are much more complicated than the xed-point arithmetic operations. For example, the oating-point addition may require the following steps: A + B 1. If A = 0 and/or B = 0, then the result is B, ora, or zero. 2. Compare the values of E 0 A and E 0 B and align the mantissa that has the smallest exponent value. 3. Add two mantisses together. The result is E 0,which is the largest value amongst E 0 A and E 0 B obtained in step Normalize the result. Implementations of the oating-point arithmetic operations: 1. Software. 2. ROMs. 3. Logic circuits (by pipeline in most cases).

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