Digital Integrated Circuits A Design Perspective. Designing Sequential Logic Circuits

Transcription

1 igital Integrated Circuits A esign Perspective esigning Sequential Logic Circuits

2 Mux-Based Positive Latch = 1, latch is transparent = 0, latch retains data Sizing of transistors is not critical for realizing correct functionality since feedback loop will be open when sampling data (no contention). Not power efficient since it presents a load of 4 transistors to the signal

3 Mux-Based Positive Latch M M NMOS only Reduced load to two transistors. rawbacks: Use of NMOS-only pass transistors results in a degraded 1 (V dd -V tn ). This impacts noise margin especially for low V dd values w.r.t. V tn. It also causes static power dissipation in the first inverter since PMOS is not fully turned off.

4 Master-Slave (Positive Edge-Triggered) Register Master Slave M 1 M Cascade of two opposite latches trigger on edge Also called master-slave latch pair When =0, Master is transparent, and passes to M. The slave stage is in hold mode, keeping the previous value by using feedback. When =1, the slave stage samples the output of the master stage ( M ), while master goes into hold mode. The value of is the value of right before the rising edge of the clock, achieving the (+ve) edge triggered effect.

5 Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3 When =0, Master is transparent, and passes to M. The slave stage is in hold mode, keeping the previous value by using feedback. When =1, the slave stage samples the output of the master stage ( M ), while master goes into hold mode. rawback: high load presented to the clock signal (8 transistors) - > high power dissipation

6 Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3 Assuming delay of clock inverter = 0 t pd_inv = delay of each inverter, t pd_tx = delay of transmission gate The setup time is the time before the rising edge of the clock that the input must be valid. How long before the rising edge of the clock must be stable such that M samples the value reliably? Setup time = 3t pd_inv + t pd_tx Propagation delay is the time it takes M to propagate to output. t c-q = t pd_tx + t pd_inv. The hold time is the time that the input must be held stable after the rising edge of the clock. T 1 turns off when the clock goes high. Any changes in the input after the clock goes high do not affect the output. Hold time = 0

7 Reduced Clock Load Master-Slave Register T 1 I 1 T 2 I 3 I 2 I 4 Feedback transmission gate is eliminated by directly cross-coupling the inverters - > lower clock loading. rawbacks: T 1 and its source driver must overpower the feedback inverter (I 2 ) to switch state of the cross coupled inverter. The input of I 1 must be brought below its switching threshold in order to make a transition. I 2 must be made weak (minimum sized, or increasing its L if T 1 is minimum sized which is desirable to reduce power dissipation in latches and clock distribution network) Reverse conduction the second stage can affect the state of the first latch. When slave stage is on, it is possible for the combination of T 2 and I 4 to influence the data stored in the I 1 -I 2 latch. As long as I 4 is weak, this is not a major problem.

8 Avoiding Clock Overlap Assumptions: elay of generating inverter is zero. No variations exist in wires used to route the 2 clock signals. This effect is called clock skew, which causes the clock signals to overlap. Two failures: A X (a) B Schematic diagram of negative master-slave register (1) When goes high, the slave stage should stop sampling the master stage output and go into hold mode. With overlap, both sampling pass transistors conduct and there is a direct path from to. Thus data at the output can change on the rising edge of the clock, which is undesirable for a (-ve edgetriggered register) Race condition (2) The primary advantage of the MUX-based register is that feedback loop is open during sample period. Thus sizing of devices is not critical to function correctly. With overlap, node A can be driven by both and B (would impact speed). (b) Overlapping clock pairs

9 Overpowering the Feedback Loop - Cross-Coupled Coupled Pairs NOR-based set-reset S R S R S R Forbidden State When both S and R are 0, the flip-flop is in quiescent state and both outputs retain their values (cross coupled NORs look like cross coupled inverters). If a positive pulse is applied to S, output is forced into a 1 state. A positive pulse applied to R resets the flip-flop, and goes to 0. Asynchronous!

10 Ratioed CMOS SR Latch It consists of a cross-coupled inverter pair + 4 extra transistors to drive the flip-flop from one state to another and to provide synchronization. In steady state, one inverter resides in high state, while other in low. Transistor sizing is essential to ensure that the flipflop can transition from one state to the other when requested. Synchronous V M 2 M 4 Case: If is 1 and R pulse is applied. In order to make latch switch, we must bring below the switching threshold of the inverter M1-M2, and quickly. Once this is achieved, the positive feedback causes the flip-flop to invert states. Thus, M5, M6, M7, M8 should be sized up. The combination between M4, M7, M8 form a ratioed inverter. kn S M 6 M 5 M 1 M 3 M 8 M 7 R To switch the latch from =0 to =1, it is essential that the low level of the ratioed inverter (M5-M6)-M2 be below the switching threshold of M3-M4 (V /2). Boundary condition occurs when V =V /2. W kn' L ( V V = k W ' ( V L 2 (W/L) 5-6 is the effective ratio of the series-connected devices. V 2 2 SATn SATp VTn) VSATn p VTp) VSATp