Chapter 11 - Digital Logic

Transcription

1 Chapter 11 - Digital Logic Luis Tarrataca luis.tarrataca@gmail.com CEFET-RJ L. Tarrataca Chapter 11 - Digital Logic 1 / 73

2 Table of Contents I 1 Introduction 2 Boolean Algebra 3 Gates 4 Combinatorial Circuit Implementation of Boolean Functions Algebraic simplification Karnaugh Maps Multiplexers Decoders Adders L. Tarrataca Chapter 11 - Digital Logic 2 / 73

3 Table of Contents I 5 Sequential Circuits Flip-flops SR flip-flops D flip-flops J-K flip-flops J-K flip-flops J-K flip-flops Registers Parallel Registers Shift Registers Counters L. Tarrataca Chapter 11 - Digital Logic 3 / 73

4 Table of Contents II Asynchronous counters Synchronous counters L. Tarrataca Chapter 11 - Digital Logic 4 / 73

5 Introduction Introduction Today s class will be a revision of digital logic elements: Boolean algebra. Gates: AND, OR, NOT, XOR,... Combinatorial logic: Multiplexers, Decoders, Adders,... Sequential logic: Flip-flops, registers, counters,... L. Tarrataca Chapter 11 - Digital Logic 5 / 73

6 Introduction Computer architecture builds on these concepts to develop new ones. Lets see how to review an entire semestre of concepts in a single class =) L. Tarrataca Chapter 11 - Digital Logic 6 / 73

7 Boolean Algebra Boolean Algebra Boolean algebra makes use of variables and operations: The variables and operations are logical variables and operations. A variable may take on the value 1 (TRUE) or 0 (FALSE). L. Tarrataca Chapter 11 - Digital Logic 7 / 73

8 Boolean Algebra Figure: Boolean operators of two input variables (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 8 / 73

9 Boolean Algebra What if we have more than two variables? Figure: Boolean operators extended to more than two inputs (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 9 / 73

10 Boolean Algebra Figure: Basic identities of boolean algebra (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 10 / 73

11 Gates Gates The fundamental building block of all digital logic circuits is the gate. Logical functions are implemented by the interconnection of gates. The basic gates used in digital logic are AND, OR, NOT, NAND, NOR, and XOR. L. Tarrataca Chapter 11 - Digital Logic 11 / 73

12 Gates Figure: Basic logic L. Tarrataca gates (Source: Chapter [Stallings, 11 - Digital2015]) Logic 12 / 73

13 Gates The NAND and NOR gates are also known as universal gates: Any Boolean function can be implemented using only them (1/3). Figure: The use of NAND gates (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 13 / 73

14 Gates The NAND and NOR gates are also known as universal gates: Any Boolean function can be implemented using only them (2/3). Figure: The use of NAND gates (Source: [Stallings, 2015]) A.B = A.B L. Tarrataca Chapter 11 - Digital Logic 14 / 73

15 Gates The NAND and NOR gates are also known as universal gates: Any Boolean function can be implemented using only them (3/3). Figure: The use of NAND gates (Source: [Stallings, 2015]) A+B = A+B = A.B (DeMorgan Law) L. Tarrataca Chapter 11 - Digital Logic 15 / 73

16 Combinatorial Circuit Combinatorial Circuit A set of interconnected gates output at any time is a function only of the input at that time; consists of n binary inputs and m binary outputs Can be defined in three ways: Truth table; Graphical symbols; Boolean equations L. Tarrataca Chapter 11 - Digital Logic 16 / 73

17 Combinatorial Circuit Implementation of Boolean Functions Example Consider the following truth table for a boolean function of three variables: Figure: A boolean function of three variables (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 17 / 73

18 Combinatorial Circuit Implementation of Boolean Functions F can be expressed by itemizing the combinations that cause F to be 1: F = ĀB C + ĀBC + AB C Figure: Circuit implementation (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 18 / 73

19 Combinatorial Circuit Algebraic simplification F = ĀB C + ĀBC + AB C = ĀB( C + C)+AB C = ĀB.1+AB C = B(Ā+A C) = B((Ā+A)(Ā+ C)) = B(1(Ā+ C)) = ĀB+ B C Besides algebraic simplification we can also employ Karnaugh maps to obtain simpler expressions. L. Tarrataca Chapter 11 - Digital Logic 19 / 73

20 Combinatorial Circuit Karnaugh Maps Karnaugh Maps The algebraic simplification procedure is awkward: Lacks specific rules to predict each succeeding step; Difficult to determine if the simplest expression has been obtained; The Karnaugh map method provides a method for simplifying boolean expressions: Up to four variables; More than this becomes cumbersome to use. This section is based on [Mano and Kime, 2002]. L. Tarrataca Chapter 11 - Digital Logic 20 / 73

21 Combinatorial Circuit Karnaugh Maps The map is a diagram made up of squares: each square represents one minterm of the function; Visual diagram of all possible ways a function may be expressed; L. Tarrataca Chapter 11 - Digital Logic 21 / 73

22 Combinatorial Circuit Karnaugh Maps Lets take a look at a three-variable map. Only one bit changes in value from one column to the other; Any two adjacent squares differ in only a single variable; Figure: Three Variable Map (Source: [Mano and Kime, 2002]) Any two minterms in adjacent squares produce a product of two variables. Why? L. Tarrataca Chapter 11 - Digital Logic 22 / 73

23 Combinatorial Circuit Karnaugh Maps Lets see why... Figure: Three Variable Map (Source: [Mano and Kime, 2002]) E.g.: m 5 + m 7 = XȲZ + XYZ I.e. m 5 + m 7 = XȲ Z + XYZ = XZ(Ȳ + Y) = XZ The two squares differ in variable Y, which can be removed. L. Tarrataca Chapter 11 - Digital Logic 23 / 73

24 Combinatorial Circuit Karnaugh Maps Karnaugh Map Example 1 Figure: m(2, 3, 4, 5) = XY + XȲ (Source: [Mano and Kime, 2002]) L. Tarrataca Chapter 11 - Digital Logic 24 / 73

25 Combinatorial Circuit Karnaugh Maps Karnaugh Map Example 2 Two squares can also be adjacent without touching each other: Figure: m(0, 2, 4, 6) = X Z + X Z (Source: [Mano and Kime, 2002]) The minterms continue to differ by one variable; L. Tarrataca Chapter 11 - Digital Logic 25 / 73

26 Combinatorial Circuit Karnaugh Maps Karnaugh Map Example 3 It is also possible to combine 4 squares: Figure: m(0, 2, 4, 6) = X Z + X Z = ( X + X) Z = Z (Source: [Mano and Kime, 2002]) L. Tarrataca Chapter 11 - Digital Logic 26 / 73

27 Combinatorial Circuit Karnaugh Maps Karnaugh Map Example 4 It is also possible to have several combinations: Figure: m(0, 1, 2, 3, 6, 7) = X + Y (Source: [Mano and Kime, 2002]) L. Tarrataca Chapter 11 - Digital Logic 27 / 73

28 Combinatorial Circuit Karnaugh Maps The more squares are combined the fewer literals are used: One square represents three literals; Two squares represents a product term of two literals; Four squares represents a product term of one literal; Eight squares (entire map) is equal to value 1. L. Tarrataca Chapter 11 - Digital Logic 28 / 73

29 Combinatorial Circuit Multiplexers Multiplexers The multiplexer connects multiple inputs to a single output. At any time, one of the inputs is selected to be passed to the output. Figure: A 4-to-1 Multiplexer representation (Source: [Stallings, 2015]) Figure: A 4-to-1 Multiplexer truth table (Source: [Stallings, 2015]) Four input lines (D0, D1, D2, and D3); Two selection lines (S0 and S1); L. Tarrataca Chapter 11 - Digital Logic 29 / 73

30 Combinatorial Circuit Multiplexers Figure: Multiplexer Implementation (Source: [Stallings, 2015]) Multiplexeres are useful for: to control signal and data routing; E.g. loading PC from different sources; L. Tarrataca Chapter 11 - Digital Logic 30 / 73

31 Combinatorial Circuit Decoders Decoders Combinational circuit with a number of output lines: only one of which is asserted at any time, dependent on input; n inputs, 2 n output lines; L. Tarrataca Chapter 11 - Digital Logic 31 / 73

32 Combinatorial Circuit Decoders Figure: Decoder with 3 inputs and 2 3 = 8 outputs (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 32 / 73

33 Combinatorial Circuit Adders Adders Binary addition differs from Boolean algebra in that the result includes a carry term. L. Tarrataca Chapter 11 - Digital Logic 33 / 73

34 Combinatorial Circuit Adders Figure: Binary addition truth tables (Source: [Stallings, 2015]) The two outputs can be expressed: Sum = C in AB+ C in AB+ C in AB+ C in AB C out = C in AB+ C in AB+ CAB+ CAB L. Tarrataca Chapter 11 - Digital Logic 34 / 73

35 Combinatorial Circuit Adders Figure: 4 bit adder (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 35 / 73

36 Combinatorial Circuit Adders Figure: Implementation of an adder using AND, OR and NOT gates (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 36 / 73

37 Sequential Circuits Sequential Circuits Combinational circuits implement the essential functions of a computer. However, they provide no memory or state information, This is where sequential circuits come in: The current output of a sequential circuit depends not only on the current input and the current state of that circuit. Useful examples of sequential circuits: Flip-flops; Registers; Counters. L. Tarrataca Chapter 11 - Digital Logic 37 / 73

38 Sequential Circuits Flip-flops Flip-flops The simplest form of sequential circuit is the flip-flop. There are a variety of flipflops, all of which share two properties: Can maintain a binary state indefinitely (as long as powered is deliver to the circuit): Until directed by an input signal to switch states. The flip-flop can function as a 1-bit memory. Has two outputs, these are generally labeled Q and Q. L. Tarrataca Chapter 11 - Digital Logic 38 / 73

39 Sequential Circuits Flip-flops SR flip-flops The circuit has two inputs S (Set) and R (Reset) And two outputs Q and Q, and consists of two NOR gates connected in a feedback arrangement. Figure: The S-R Latch implemented with NOR Gates (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 39 / 73

40 Sequential Circuits Flip-flops This circuit can function as a 1-bit memory: The inputs S and R serve to write the values 1 and 0, respectively, into memory. Consider the state Q = 0, Q = 1, S = 0, R = 0 Figure: S-R Latch implemented with NOR Gates (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 40 / 73

41 Sequential Circuits Flip-flops Suppose that S changes to the value 1. Figure: S-R Latch implemented with NOR Gates (Source: [Stallings, 2015]) Figure: NOR S-R Latch timing Diagram (Source: [Stallings, 2015]) 1 Now the inputs to the lower NOR gate are S = 1, Q = 0. 2 After some time delay t, the output of the lower NOR gate will be Q = 0. L. Tarrataca Chapter 11 - Digital Logic 41 / 73

42 Sequential Circuits Flip-flops Figure: S-R Latch implemented with NOR Gates (Source: [Stallings, 2015]) Figure: NOR S-R Latch timing Diagram (Source: [Stallings, 2015]) 3 the inputs to the upper NOR gate become R = 0, Q = 0. 4 After another gate delay of t, the output Q becomes 1. L. Tarrataca Chapter 11 - Digital Logic 42 / 73

43 Sequential Circuits Flip-flops Figure: S-R Latch implemented with NOR Gates (Source: [Stallings, 2015]) Figure: NOR S-R Latch timing Diagram (Source: [Stallings, 2015]) 5 This is a stable state. The inputs to the lower gate are now S = 1, Q = 1, which maintain the output Q = 0. As long as S = 1 and R = 0, the outputs will remain Q = 1, Q = 0. Furthermore, if S returns to 0, the outputs will remain unchanged. L. Tarrataca Chapter 11 - Digital Logic 43 / 73

44 Sequential Circuits Flip-flops Figure: S-R Latch implemented with NOR Gates (Source: [Stallings, 2015]) Figure: NOR S-R Latch timing Diagram (Source: [Stallings, 2015]) 6 The R output performs the opposite function. When R goes to 1, it forces Q = 0, Q = 1 Regardless of the previous state of Q and Q. Again, a time delay of 2 t occurs before the final state is established L. Tarrataca Chapter 11 - Digital Logic 44 / 73

45 Sequential Circuits Flip-flops This behaviour can be described by a characteristic table: Figure: (Source: [Stallings, 2015]) Inputs S = 1, R = 1 are not allowed, because these would produce an inconsistent output: Q = Q = 0 L. Tarrataca Chapter 11 - Digital Logic 45 / 73

46 Sequential Circuits Flip-flops It is also possible to derive a simplified version: Figure: (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 46 / 73

47 Sequential Circuits Flip-flops Example Lets look at a particular example: Figure: (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 47 / 73

48 Sequential Circuits Flip-flops Typically events in the digital computer are synchronized to a clock pulse, So that changes occur only when a clock pulse occurs; The R and S inputs are passed to the NOR gates only during the clock pulse. Figure: Clocked SR flip-flops (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 48 / 73

49 Sequential Circuits Flip-flops D flip-flops One problem with S-R flip-flop is that the condition R = 1, S = 1 must be avoided. One way to do this is to allow just a single input. Figure: (D flip-flops [Stallings, 2015]) By using an inverter, the nonclock inputs to the two AND gates are guaranteed to be the opposite of each other. L. Tarrataca Chapter 11 - Digital Logic 49 / 73

50 Sequential Circuits Flip-flops Figure: D flip-flops [Stallings, 2015] Figure: D flip-flops Characteristic Table [Stallings, 2015] The flip-flop captures the value of the D-input during the clock cycle; That captured value becomes the Q output. At other times, the output Q does not change. L. Tarrataca Chapter 11 - Digital Logic 50 / 73

51 Sequential Circuits Flip-flops J-K flip-flops (1/3) Has two inputs. However, in this case all possible combinations of input values are valid: Figure: J-K flip-flops [Stallings, 2015] Figure: J-K flip-flops Characteristic Table [Stallings, 2015] Note that the first three combinations are the same as for the SR flip-flop; With no input asserted, the output is stable; L. Tarrataca Chapter 11 - Digital Logic 51 / 73

52 Sequential Circuits Flip-flops J-K flip-flops (2/3) Figure: J-K flip-flops [Stallings, 2015] Figure: J-K flip-flops Characteristic Table [Stallings, 2015] If only the J input is asserted, the result is a set function, causing the output to be 1; if only the K in put is asserted, the result is a reset function, causing the output to be 0. L. Tarrataca Chapter 11 - Digital Logic 52 / 73

53 Sequential Circuits Flip-flops J-K flip-flops (3/3) Figure: J-K flip-flops [Stallings, 2015] Figure: J-K flip-flops Characteristic Table [Stallings, 2015] When both J and K are 1, the output is reversed; Thus, if Q is 1 and 1 is applied to J and K, then Q becomes 0. L. Tarrataca Chapter 11 - Digital Logic 53 / 73

54 Sequential Circuits Flip-flops In summary: Figure: Basic flip-flops summary [Stallings, 2015] L. Tarrataca Chapter 11 - Digital Logic 54 / 73

55 Sequential Circuits Registers Registers A register is a digital circuit used within the CPU to store one or more bits of data. Two basic types of registers are commonly used: parallel registers; shift registers. Lets have a quick look at each one of these... L. Tarrataca Chapter 11 - Digital Logic 55 / 73

56 Sequential Circuits Registers Parallel Registers Register consisting of a set of 1-bit memories that can be read or written simultaneously. Figure: 8 Bit Parallel Register (Source: [Stallings, 2015]) Makes use of D flip-flops Load control signal controls writing into the register from signal lines, D11 through D18. L. Tarrataca Chapter 11 - Digital Logic 56 / 73

57 Sequential Circuits Registers Shift Registers (1/2) A shift register accepts and/or transfers information serially: Figure: 5 Bit Shift Register (Source: [Stallings, 2015]) A 5-bit shift register constructed from clocked D flip-flops; Data are input only to the leftmost flip-flop; With each clock pulse, data are shifted to the right one position; and the rightmost bit is transferred out. L. Tarrataca Chapter 11 - Digital Logic 57 / 73

58 Sequential Circuits Registers Shift Registers (2/2) A shift register accepts and/or transfers information serially: Figure: 5 Bit Shift Register (Source: [Stallings, 2015]) Shift registers can be used to interface to serial I/O devices. In addition, they can be used within the ALU to perform logical shift and rotate functions. L. Tarrataca Chapter 11 - Digital Logic 58 / 73

59 Sequential Circuits Counters Counters A counter is a register whose value is easily incremented by 1 modulo the capacity of the register: A register made up of n flip-flops can count up to 2 n 1. After value 2 n 1 the next increment sets the counter value to 0. An example of a counter in the CPU is the program counter. L. Tarrataca Chapter 11 - Digital Logic 59 / 73

60 Sequential Circuits Counters Counters can be designated as asynchronous or synchronous: Asynchronous counter: relatively slow because the output of one flip-flop triggers a change in the status of the next flip-flop. Synchronous counter: all of the flip-flops change state at the same time. the kind used in CPUs. Lets have a look at each one of these... L. Tarrataca Chapter 11 - Digital Logic 60 / 73

61 Sequential Circuits Counters Asynchronous counters (1/3) Figure: 4-Bit Counter (Source: [Stallings, 2015]) The output of the leftmost flip-flop(q 0 ) is the least significant bit. Extensible to an arbitrary number of bits by cascading more flip-flops. The counter is incremented with each clock pulse. L. Tarrataca Chapter 11 - Digital Logic 61 / 73

62 Sequential Circuits Counters Asynchronous counters (2/3) Figure: 4-Bit Counter (Source: [Stallings, 2015]) The J and K inputs to each flip-flop are held at a constant 1. I.e. when there is a clock pulse, the output at Q will be inverted; The change in state occurs with the falling edge of the clock pulse A.k.a. edge-triggered flip-flop This timing is very important for the correct functioning of the counter. L. Tarrataca Chapter 11 - Digital Logic 62 / 73

63 Sequential Circuits Counters Asynchronous counters (3/3) Figure: 4-Bit Counter (Source: [Stallings, 2015]) The state of each individual bit is initially set to zero If one looks at patterns of output for this counter, it can be seen that it cycles through 0000, 0001,..., 1110, 1111, 0000 Note the transitional delay from each flip-flops L. Tarrataca Chapter 11 - Digital Logic 63 / 73

64 Sequential Circuits Counters Synchronous counters (1/9) Asynchronous counters have a disadvantageous built-in delay: proportional to the length of the counter. CPUs make use of synchronous counters: all of the flip-flops of the counter change at the same time. Lets take a look at how to build a 3-bit synchronous counter. L. Tarrataca Chapter 11 - Digital Logic 64 / 73

65 Sequential Circuits Counters Synchronous counters (2/9) For a 3-bit counter, three flip-flops will be needed: Let us use J-K flip-flops. Label the uncomplemented output of the three flip-flops A, B, C respectively, with C representing the least significant bit. It is helpful to recast the characteristic table for the J-K flip-flop: Figure: Original Figure: Recast L. Tarrataca Chapter 11 - Digital Logic 65 / 73

66 Sequential Circuits Counters Synchronous counters (3/9) It is helpful to recast the characteristic table for the J-K flip-flop: Figure: Original Figure: Recast If Q n = 0 and we want to transition to Q n+1 = 0 Then J = 0 and K = 0, 1 If Q n = 0 and we want to transition to Q n+1 = 1 Then J = 1 and K = 0, 1 L. Tarrataca Chapter 11 - Digital Logic 66 / 73

67 Sequential Circuits Counters Synchronous counters (4/9) It is helpful to recast the characteristic table for the J-K flip-flop: Figure: Original Figure: Recast If Q n = 1 and we want to transition to Q n+1 = 0 Then K = 1 and J = 0, 1 If Q n = 1 and we want to transition to Q n+1 = 1 Then K = 0 and J = 0, 1 L. Tarrataca Chapter 11 - Digital Logic 67 / 73

68 Sequential Circuits Counters Synchronous counters (5/9) Figure: Synchronous Counter Truth Table (Source: [Stallings, 2015]) Consider the transition from 000 to 001 We want the value of A to remain 0, the value of B to remain 0, and the value of C to go from 0 to 1 with the next application of a clock pulse; The excitation table shows that to maintain an output of 0, we must have inputs of J = 0 and don t care for K. To effect a transition from 0 to 1, the inputs must be J = 1 and K = d. L. Tarrataca Chapter 11 - Digital Logic 68 / 73

69 Sequential Circuits Counters Synchronous counters (6/9) With this in mind we can construct a truth table that relates the J-K inputs and outputs Figure: Synchronous Counter Truth Table (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 69 / 73

70 Sequential Circuits Counters Synchronous counters (7/9) With the aid of Karnaugh maps, we can develop Boolean expressions for these six functions: Figure: Synchronous Counter Karnaugh Maps (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 70 / 73

71 Sequential Circuits Counters Synchronous counters (8/9) For example, the Karnaugh map for the variable Ja: The J input to the flip-flop that produces the A output; yields the expression Ja = BC. When all six expressions are derived, it is a straightforward matter to design the actual circuit. L. Tarrataca Chapter 11 - Digital Logic 71 / 73

72 Sequential Circuits Counters Synchronous counters (9/9) The actual circuit: Figure: Synchronous Counter Design (Source: [Stallings, 2015]) L. Tarrataca Chapter 11 - Digital Logic 72 / 73

73 References References I Mano, M. and Kime, C. R. (2002). Logic and Computer Design Fundamentals: 2nd Edition. Prentice Hall, Englewood Cliffs, NJ, USA. Stallings, W. (2015). Computer Organization and Architecture. Pearson Education. L. Tarrataca Chapter 11 - Digital Logic 73 / 73