Applied Circuit and PCB Design. Alfonso Blanco Fontao 28/02/2017
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1 Applied Circuit and PCB Design Alfonso Blanco Fontao 28/02/2017
2 DEFINITIONS WORK ENVIRONMENT COMPONENTS
3 Work environment Licensing
4 Licensing IDES license ETH network license. Not possible to work without connection to the ETH network Cost: CHF 300 / year Student license Local installation. 1 year Cost: CHF 150 / year Full license Local installation. 1 year with possibility to extend the contract Cost: ~CHF After first year ~CHF 2000 / year
5 Alternatives Eagle: local installation without license Advantage: partly free, many libraries Disadvantage: only one schema page, restriction in number of components OrCad: local installation without license Advantage: partly free, many libraries Disadvantage: only one schema page, restriction in number of components KiCad: local installation without license Advantage: free software, no restrictions Disadvantage: few libraries, development not finished CERN developers work on the integration of a simulation system
6 EDA software restrictions Stick to ETH terms (IDES) Only authorized users (licenses) Handle data confidentially No commercial use allowed Discretion (don t provide reviews) Responsible users No pirate software
7 Work environment Preferences Altium Designer
8 System View General Open Internet Links in external Web Browser Default Locations Document Path Library Path H:\PCB-Projects C:\Users\Public\Documents\Altium\AD16\Library\
9 Data management Templates Template Location H:\PCB-Templates Installed Libraries Library Path relative to C:\Users\Public\Documents\Altium\AD16\Library\
10 General Options Schematic Convert Cross-Junctions Display Cross-Overs Graphical Editing Options Convert Special Strings Default Units Imperial Unit System Imperial Unit used Use Imperial Unit System Dxp Defaults
11 PCB editor General Editing Options Auto Pan Options Online DRC Smart Track Ends Speed: 300 Pixels/Sec Other Cursor Type: Large 90
12 Work environment Project options
13 Menu Project Project options Error Reporting Violations associated with nets Nets with only one pin Error Class Generation Generate Rooms (to replicate channels)
14 Project take-over Open project and note error messages (usually missing documents) Check and adjust the project options Compile project and check errors Study schema Check libraries currentness
15 Work environment Working on the schematic
16 Design flow Create schematics library Create footprint library Link libraries Use schematics symbols in schema Create PCB
17 Caution Never change a footprint on a PCB layout Never change a schematic symbol on the schema Changes will take effect after updating from libraries Exceptions: I/O assignments (be careful when updating)
18 Changes Change on symbol s library Update schematics from library Update PCB layout from schema Update PCB layout from the footprint library
19 Definitions
20 Symbol Graphical representation of a component Pin(s): only mandatory element(s) Symbol body: no constraint, but should be meaningful
21 Pin Component s interface to the world One pin per component s lead Defined through a designator and a pin description
22 Footprint or Land Pattern Physical and electrical component s connection Pads are mandatory Also Silkscreen, Courtyard, Solder Mask, Paste Mask
23 Pads / Through Holes Each of the copper surfaces / through holes to which a lead is soldered One pad per component s lead Defined through a designator: must match its pin s designator
24 Solder Mask or Solder Resist Thin lacquer-like layer of polymer that is usually applied to the copper traces of a printed circuit board (PCB) for protection against oxidation and to prevent solder bridges from forming between closely spaced solder pads (Google) Each pad has a solder mask void defined (usually slightly larger than the pad): otherwise, no soldering possible
25 Silkscreen or Overlay Information printing on the board Component s position, orientation and reference Mandatory on the footprint, not for fabrication. Helpful though
26 Paste Mask Defines the areas where solder paste needs to be laid One opening per SMD pad (of its same size) Only required for SMD components machine soldering Not needed for though hole pads
27 Courtyard Area around a component where no other component should be placed Not fabricated: only a reference to the designer
28 Component Set of Symbol, Footprint and Models that completely define an electronic part from the PCB point of view
29 Via Consists of two pads in corresponding positions on different layers of the board, that are electrically connected by a hole through the board (Google)
30 Thermal relief A thermal relief pad is a PCB pad connected to a copper pour using a thermal connection (Google) It looks like a normal pad with copper "spokes" connecting it to the surrounding copper (Google) Allows for a better solderability
31 Antipad Void around a via or through hole pad to isolate it from a plane where a connection is not needed
32 Stackup Build up of copper layers, dielectric materials and masks to conform a PCB
33 Components Libraries
34 Components Sources Local libraries Avoid as much as possible Altium Container Vault Big set of parts Only available with subscription ETH Vault Replaces the local libraries To be used for components not present on the Altium Container Vault
35 Components Vaults IPC-compliant footprints and symbols Always up to date Suppliers information included Common for all the Altium users
36 Components Vaults
37 Components Vaults
38 Components generation Time consuming, but worthwhile Libraries grow with the company Collaboration with business partners Organize parts by function
39 Footprints generation Pay attention to layer use Consider shielding and special contacts Check exact dimensions (datasheet) Use footprint wizard, but never trust it. Check results Set to metric system (shortcut Q) Use grids (shortcut G)
40 Create footprint manually Lay pads Special pad shapes several pads with same designator Lines as guides if needed Form on assembly layer (Mechanical 12) Silkscreen (Top / Bottom overlay) Courtyard and center (Mechanical 15) 3D body / STEP model (Mechanical 13)
41 Symbols generation Pay attention to documentation (datasheets, vendor links) Give meaningful names Set parts (subcircuits) Different models different footprints different components Place footprint model Place simulation model (if available)
42 Create symbol manually Shape and appearance: IEC60617 DB Place pins: number, name, I/O Add text and graphics Parameter comment =value (not visible) Parameter value visible 1 order number per footprint Units Imperial
43 Components Packaging
44 Components packages MC78xxABD (SOP-8)
45 Components packages MC78xxABP (TO-92)
46 Components packages MC78xxABDT (DPAK)
47 Components packages MC78xxABD2T (D2PAK)
48 Components packages MC78xxABT (TO220)
49 Components Pins & Pads
50 Complete and correct? No working device without a correct components library Check unknown symbols before use Are the number of pins of the standard and of the datasheet the same? Are the number of pins of the symbol and of the footprint the same? Make sure that: All datasheets are attached to the project (paper or PDF) Latest datasheet versions online
51 Example: pin numbering Parts (for example pin headers) with different numbering systems!
52 Components library Pads Do holes and though hole pads match the current regulations? Do the SMD pads match the current regulations? Are the SMD parts solderable by hand? Is it possible to assemble and solder the SMD parts by machine?
53 Components library Pads While all can manually be soldered (except for BGA, CSP, etc.), the soldering equipment places high demands on the pad surfaces Different soldering processes (wave, reflow ) require different pad surfaces Create different footprints for manual and automatic soldering for the same component Wrong pad surfaces can lead to tombstone effect
54 Tombstone effect Design Caused by the components library Different-sized contact surfaces. Contact surfaces too large and widely spaced Caused by the placement Component partially in the shadow zone of a larger neighboring component Caused by the PCB design Different heat dissipation on both sides Adjacent parts with high heat capacity (mostly large components)
55 IPC-7351A levels: RESC2012X06M/N/L Level A: maximal overlap of the landing surface (M as last character in the component s description) Level B: medium overlap of the landing surface (N as last character in the component s description) Level C: minimal overlap of the landing surface (L as last character in the component s description)
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