LXT1000 Gigabit Ethernet Transceiver Design and Layout Guide

Transcription

1 LXT1000 Gigabit Ethernet Transceiver Design and Layout Guide Application Note January 2001 Order Number: As of January 15, 2001, this document replaces the Level One document known as AN104.

2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT1000 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at Copyright Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Application Note

3 Contents 1.0 General Description Design and Layout Checklist LXT1000 Interface Design Guidelines General Guidelines Guidelines for Differential Signals Power and Ground Power and Ground Planes Analog VCC Plane Digital VCC Plane Ground Plane Chassis Ground Ground and Power Plane Layout Filtering Analog Power Using a Ferrite Bead Power and Ground Balls Designing for Thermal Efficiency Introduction Design Recommendations Twisted-Pair Interface Return Loss Considerations Introduction Local Echo Remote Echo Echo Cancellation is Expensive Dealing with Return Loss Magnetic and Clock Reference Magnetics Information Clock Source Additional Layout Considerations RBIAS GBIAS Hardware Control Interface LED Balls Quick Status Output MAC Interface GMII Considerations AC Specifications DC Specifications Timing GTX_CLK Test Output Signals...26 Application Note 3

4 Figures Tables 8.8 5V Tolerance Considerations XI/XO Interface LXT1000 Interface Diagram Signal Layer Filling Power and Ground Plane Division Filtering the Analog Power Supply LXT1000 Ball Grid Array (Power balls indicated with hash marks) Recommended PCB Layout - Top View Thermal Relief and Solid Connection - Top View Recommended PCB Stack-up - Cross-sectional View Transmit Interface Circuitry Impedance Mismatch Return Loss Return Loss Reflected Back to Transceiver LXT1000 Echo Reduction Far-End Echo LED Termination Circuitry GMAC Specifications Recommended LXT1000 GMII Output Circuit Magnetics Requirements Magnetic Manufacturers Clock Requirements Crystal Manufacturers Application Note

5 1.0 General Description This application note provides design and layout guidelines for the LXT1000 Gigabit Ethernet Transceiver, including component selection information and recommendations for signal placement and routing. The LXT1000 supports Gigabit Ethernet over CAT-5 twisted-pair copper connections up to 100 meters long, with fallback support for 10/100 operation. The LXT1000 requires a 3.3V power supply and a 25 MHz reference clock. See the LXT1000 data sheet for complete device functions and capabilities. The LXT1000 provides the following interfaces: MAC - Provides connection to an Ethernet controller and supports the Gigabit Media Independent Interface (GMII, 802.3ab). For 10/100 operation, the MAC interface defaults to an MII mode. Twisted-Pair - Directly drives a Gigabit Ethernet twisted-pair connection. Hardware Control - Sets the initial state of the LXT1000 at power-up. LEDs and QuickStatus - Provide link information. 1.1 Design and Layout Checklist Achieving the highest performance from the LXT1000 requires good design and layout practices. The following brief checklist summarizes some key guidelines required for a successful design. See General Guidelines on page 7 for a more detailed list. Create a separate analog VCC plane that is isolated from the digital VCC plane. Use a single common ground plane for all analog and digital functions. Provide a series termination resistor for each GMII signal. Route high-speed signals next to a continuous, unbroken ground plane. Except for twisted-pair outputs and LEDs, do not route signals between the LXT1000 and the RJ-45 connector. Do not route any signals beneath any part of the chassis ground plane. Application Note 5

6 1.2 LXT1000 Interface Figure 1. LXT1000 Interface Diagram Media Access Controller MAC 25 MHz RBIAS GBIAS 3.3V Mgmt Data MAC Interface LXT1000 Network Interface Twisted-Pair Port Hardware Control LEDs, Quick Status Magnetics 1000BASE-TX 6 Application Note

7 2.0 Design Guidelines 2.1 General Guidelines Meeting EMI and ESD system requirements and ensuring the best Bit Error Rate (BER) and linelength performance requires good engineering practices throughout the entire design. System requirements and line performance both face a common enemy: noise emanating from high-speed digital logic, oscillators, and switching power supplies. This noise permeates the power and ground planes and proceeds to the communications system as common-mode noise. The following guidelines help fight against the noise problem: The power supply must deliver the maximum current required by the design with minimal output ripple (<50 mv). The power and ground planes must have enough mass (number, size, and weight of copper) to provide dissipation for high-frequency switching currents and shielding for electromagnetic fields. See Power and Ground on page 9 for more detail. Keep power and ground plane connections as short as possible. Place a bypass capacitor on every VCC input of every device. The self-resonant frequency of each cap should be higher than the highest switching frequency of its corresponding VCC ball. If using ferrite beads, they should be rated for at least 150% of the required current. Use bulk capacitors ( µf) near high-speed busses (>25 MHz), regulators, and on each side of a ferrite bead. Provide termination on all high-speed switching signals and clock lines. Provide a series termination resistor for each GMII signal. (For the GMII signals driven by the LXT1000, the correct value to use is 42Ω.) Ensure GMII signal traces are < 9 inches long, with a differential of < 1 inch. Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane not located adjacent to the signal layer. Refer to signal layer filling diagram in Figure 2. Ensure good solid connections between the chassis ground and safety or earth ground. Provide low- impedance AC paths between the line-side center taps of the magnetics and chassis ground. Figure 2. Signal Layer Filling Layer Name Signal 1 GND Layer Signal 2 Signal 3 VCC Layer Signal 4 Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 Plane Fill VCC VCC GND GND Application Note 7

8 2.2 Guidelines for Differential Signals The following guidelines apply to all differential signals, including the twisted-pair signals: Route differential pairs side by side, with nothing in between. Put extra space between a differential pair and other signals. Keep both traces of each differential pair as close to the same length as possible. Avoid vias and layer changes as much as possible. 8 Application Note

9 3.0 Power and Ground 3.1 Power and Ground Planes LXT1000 designs require correct placement of the power and ground planes. The power and ground planes can be divided into four regions as shown in Figure 3: Analog VCC Plane Digital VCC Plane Ground Plane Chassis Ground Figure 3. Power and Ground Plane Division Keep all highspeed digital logic signals out of the analog power plane RJ45 LEDs Magnetics Analog VCC Plane LXT1000 Chassis Ground Ground Plane Digital VCC Plane Ferrites Ferrites MAC Control Logic RAM Keep all highspeed digital logic signals inside the digital power plane Tie to Safety/ Earth Ground Void area to prevent loop antenna effect Filter the analog power plane with ferrite beads Optional Isolation Area Analog VCC Plane The analog VCC plane supplies power to the analog portions of the LXT1000. The Analog VCC balls on the LXT1000 are supplied by this plane, along with the device-side center taps of the magnetics. Physically, this plane extends from the magnetics to the front half of the LXT1000. Unnecessary signals, especially high-speed digital busses, should not be routed through this region. For best results, isolate this plane from digital power. The analog power plane can be supplied from its own regulator, or by filtering the digital supply through a ferrite bead. In multi-port LXT1000 designs, a single analog power plane can supply all LXT1000 devices Digital VCC Plane The digital VCC plane supplies power to the back-end of the LXT1000 and to all other devices. This plane extends to all areas not covered by the analog power plane, but should not extend under the chassis ground region. Application Note 9

10 3.1.3 Ground Plane The ground plane is the return path for all digital and analog functions. This plane should occupy the same area as occupied by the digital and analog power planes combined Chassis Ground The chassis ground plane provides an electrical connection to the external chassis, any cable shields, and safety ground. This plane provides a safe discharge path for EOS and ESD events. It provides some amount of shielding for the board, and provides a final discharge path for common mode noise. The chassis ground plane extends forward from the magnetics to the front edge of the card, and around the perimeter of the card, with a gap at one point to prevent a ground loop. Do not pass any signals through this region except for twisted-pair inputs/outputs and LEDs. In multi-point ground systems, chassis and logic ground are continuously joined. In single-point ground systems, chassis and logic ground are joined at one point, typically with a 2 kv discharge cap Ground and Power Plane Layout Ensure all power and ground planes are solid regions. Do not loop one plane around another. The analog power plane does not require a separate layer. Instead, use a moat to divide a single large plane into two regions. Use this same moat method for dividing chassis and logic ground in singlepoint grounding systems Filtering Analog Power Using a Ferrite Bead Figure 4 illustrates how analog power is filtered by using a ferrite bead to bridge the digital and analog power planes. Place bulk capacitors to ground on either side of the bead. The bead should be rated for at least 1A (nominal load is 780 ma). In multi-port designs, one bead per LXT1000 is recommended. Alternatively, the analog power plane can be supplied from its own regulator. A bead can still be used at the output of the regulator to filter noise. Figure 4 shows how to design the inputs to the GBIAS and RBIAS balls. 10 Application Note

11 Figure 4. Filtering the Analog Power Supply GBIAS GBIAS GBIAS GND VCCA RBIAS GND 10.7 kω 1% 0.1 µf.01 µf LXT1000 Analog VCC Plane 10µF + Ferrite Beads VCCD GNDD Digital VCC Plane.01 µf 10µF +3.3V 3.2 Power and Ground Balls Figure 5 shows how the power and ground balls on the LXT1000 correlate to its internal functions. Each power/ground pair should have its own.01 µf high-frequency bypass cap, with a selfresonant frequency of at least 125 MHz (digital VCC/ground) or 250 MHz (analog VCC/ground). Note: The following balls need special attention: F4 is a Pull-down (P/D). Tie independently to ground or through its own resister. L23 must be pulled down separately. K23 is a No connect (N/C). Let ball float. Do not connect to anything. Application Note 11

12 Figure 5. LXT1000 Ball Grid Array (Power balls indicated with hash marks) A A B rx_ gtx_ rxd5 rxd7 gbias p/d master clk clk B C rxd3 rxd6 rx_ dv gbias tx_er txd7 qstat C D p/d p/d rxd1 gbias gbias gbias tx_ clk qclk txd5 D E rxd0 MDC rxd2 0 rx_ rxd4 gbias er col tx_ crs txd6 en E F p/d txd3 F G mdc SPD 0 txd4 G H J p/d SPD 2 SPD 1 mdio Digital / Analog Split txd2 txd1 txd0 H J K mdint an_ en nc2 K L ar_ rstrt mddis nc1 L M tms ser10 anisol M N tdi tck reset N P trst tdo vcca P R smart _spd R T cross vcca T U ledl ledt vcca vcca pwr dwn U V vcca vcca V W ledr ledf vcca W Y duplex/ vcca leds tx_tclk n Y AA pause/ ledc ledg vcca vcca vcca tx_tclk n AA AB vcca vcca rbias vcca vcca AB A C vcca A C A D vcca vcca A D AE vcca AE AF vcca tpap tpan vcca vcca tpbn tpbp vcca vcca tpcp tpcn vcca vcca tpdn tpdp vcca AF Application Note

13 4.0 Designing for Thermal Efficiency 4.1 Introduction When the package is in a still air environment and without heat sink, the primary heat path for conducting heat out of the PBGA package is through the vias directly under the die, internal planes, and into the ground planes of the PCB. Increasing the number of ground planes in the PCB and their copper thickness increases heat conduction, thus lowering the temperature of the package. The following section lists a few design recommendations for maximizing thermal performance. Following the design recommendations, Figures 6-8 illustrate recommended PCB layout. 4.2 Design Recommendations This section lists a few selected PCB design guidelines that maximize PBGA thermal performance: Use two 2-oz-copper thickness ground planes. Do not use thermal-relief patterns when connecting ground (thermal) vias to the ground plane(s). (Thermal-relief patterns are designed to limit heat transfer between the vias and the copper planes thus constricting the heat flow path from the component to the ground planes in the PCB.) Avoid placing LXT1000 adjacent to high power-dissipation devices. (Board temperature also has an effect on the thermal performance of the package.) Avoid placing the components downstream, behind larger devices or devices with heat sinks that obstruct the air flow or supply excessively heated air. Figure 6. Recommended PCB Layout - Top View Application Note 13

14 Figure 7. Thermal Relief and Solid Connection - Top View Not recommended: VIA Thermal Relief Recommended: Solid Connection Figure 8. Recommended PCB Stack-up - Cross-sectional View 14 Application Note

15 5.0 Twisted-Pair Interface The LXT1000 twisted-pair interface consists of four differential pairs (A, B, C, and D). The LXT1000 simultaneously transmits and receives signals on each of the four pairs. To recover the incoming signal, the receiver on each pair of the LXT1000 internally cancels the echo of its own transmitter and the local and remote crosstalk from the other three channels. Figure 9 shows a typical twisted-pair interface circuit. The termination circuit for each pair consists of a single 100Ω, 1% resistor across the pair and a simple magnetic, with the termination resistor placed as close as possible to the LXT1000. Use magnetics with a simple 1:1 winding, center taps, and a common-mode choke. (The LXT1000 does not require or use hybrid magnetics.) Attach the device-side center tap of the magnetic to the analog voltage plane with a.01 µf bypass capacitor to the analog ground plane. Attach the line-side center tap to chassis ground via a 2 kv, 1000 pf capacitor. Use a capacitor with a self-resonant frequency of at least 125 MHz. Figure 9. Transmit Interface Circuitry LXT1000 VCCA Quad Txfmr RJ-45 TPOPA 1 TPONA 100Ω 1% 0.01 µf 75Ω 2 2 kv 1000 pf Pair A To Twisted-Pair Network Detail B - Isolation Scheme 8 Detail A - Magnetics 75Ω Pair A To/From RJ-45 Main Winding CM Choke To Chassis GND Pair B Pair C Pair D 2 kv 1000 pf 1. Repeat termination circuit for each pair (A, B, C, and D). 2. Use of a 75Ω resistor (in shaded area) is optional. If not used, tie 2 kv, 1000 pf capacitor directly to center tap and ground. The line-side center taps must be terminated to chassis ground via a 2 kv, 1000 pf capacitor. There are two possible solutions: Provide a separate 2 kv, 1000 pf capacitor for each line-side center tap. Route the traces from the center taps to the capacitor as simply as possible. Optionally, provide a 75Ω resistor in series with the 2kV capacitor. (The 75Ω resistor provides common-mode impedance matching.) Mount the 75Ω resistor and capacitor to the same side of the board as the magnetics and route all signals on one layer with no vias. This solution is more costly than the other option, but provides the best EOS/ESD protection and line performance. Application Note 15

16 Tie each center-tap to its own 75Ω resistor, then tie the resistors together to a single 2 kv capacitor. This solution is more economical than the other option, but does not provide the same high level of EOS/ESD line protection and line performance (see Figure 9, Detail B). 16 Application Note

17 6.0 Return Loss Considerations 6.1 Introduction An important issue in Gigabit Ethernet designs is how closely the impedance of the entire interface matches the ideal value of 100Ω. This difference, also known as impedance mismatch, determines the design s characteristic return loss, or how much of the transmitted signal is echoed back to the receiver. As a system impairment, echo can be both the largest and latest to arrive an extremely important factor in Gigabit Ethernet designs. Figure 10 shows a typical Gigabit Ethernet link, consisting of two patch cords, a 100 meter cable, and four RJ-45 connection points. As illustrated in the figure, echoes can occur at four points along the connection: At the local twisted pair interface At the two patch-cable connectors At the remote interface between the cable plant and the link partner. Reflections from the patch-cable connectors are typically small and are cable-plant issues not under the control of the product designer. Reflections from the junctions between the cable plant and the end-nodes can be significant and are under the designer s control. These are covered separately in the next two subsections, which discuss local and remote echo. Figure 10. Impedance Mismatch Return Loss End Node / DTE LXT 1000 Patch Cable (CAT5) 100M Cable (CAT5) LXT 1000 Transmit Local Remote Echo due to Impedance Mismatch Application Note 17

18 6.2 Local Echo The amplitude of the local echo is approximately equal to the return loss of the interface. Return loss is defined as -20log10((Zo-ZL)/(Zo+ZL)), where Zo is the nominal impedance of the cable (100Ω) and ZL is the termination impedance of the interface. Return loss is usually thought of as the amount of signal reflected back onto the cable. However, it is also the amount of signal reflected back to the transceiver (see Figure 11). The IEEE standard requires that the return loss be no more than 10 db at 80 MHz achievable with careful design practices. In a welldesigned product, the local echo is about 10 db weaker than (about 1/3 the size of) the transmitted signal. Figure 11. Return Loss Reflected Back to Transceiver End Node / DTE LXT M Cable (CAT5) Hybrid Echo Cancellor Local Echo 10 db Attenuation Receive Signal 20 db Attenuation In comparison, the signal coming from the link partner over 100 meters of cable is attenuated by about 20 db, or a factor of 10. In a well-designed system, the local echo can potentially be 10 db higher about three times stronger than the received signal. Two blocks inside the LXT1000, the hybrid and the echo canceller, work together to attenuate the local echo to acceptable levels, provided that it roughly meets the return loss requirements. However, as shown in Figure 12, if the system return loss grossly violates the IEEE standard, the overall signal-to-noise ratio (SNR) of the system will be poor, resulting in a higher bit-error rate (BER) and marginal performance. 18 Application Note

19 Figure 12. LXT1000 Echo Reduction Transmitted Signal Received Signal Original Strength 0 db 0 db Original Strength Local Return Loss = 10 db Local Echo -10 db Attenuation of 100 m of cable = 20 db Echo : Receive, uncorrected, = +10 db Attenuation provided by hybrid + echo canceller = db -20 db Incoming Signal Effective SNR is more than 20 db Other non-cancellable impairments Transmitted Signal Received Signal Original Strength 0 db 0 db Original Strength Local Echo -6 db Local Return Loss = 6 db Attenuation of 100 m of cable = 20 db Attenuation provided by hybrid + echo canceller = db Echo : Receive, uncorrected, = +16 db -20 db Incoming Signal Effective SNR is less than 20 db Other non-cancellable impairments Application Note 19

20 6.3 Remote Echo The remote echo coming from the link partner should be extremely weak. It is attenuated by as much as 30 db (20 db of cable loss and 10 db of return loss) relative to the received signal. In most cases, the remote echo is so weak that system performance is not affected by it and it does not even need to be cancelled by the DSP. However, a gross violation of the return loss requirement at the far end can degrade signal-to-noise (SNR) ratio slightly (1 or 2 db). If remote echo has to be cancelled, it requires the DSP to maintain upwards of 120 taps a history going back 120 baud periods. This is because a round-trip on 100 meters of CAT5 cable takes about a microsecond, or nanosecond baud periods. Although this is feasible, having to maintain 120 taps in the DSP uses more power than might otherwise be necessary. Figure 13. Far-End Echo 100M Cable (CAT5) Roundtrip Delay = 1µs 1 µs = 120 baud periods Echo Cancellation is Expensive Not meeting return loss drops right to the bottom line. For example, a product with 6 db return loss has a final SNR 4 db worse than a product meeting the IEEE standard. The DSP may have enough power to cancel the additional echo, but may not be able to cancel other impairments, such as crosstalk, inter-symbol interference, and injected tones. Echo cancellation eats away all available bandwidth. The product may marginally function, but be extremely sensitive to non-ideal system conditions, such as a cable, that is slightly out of specification. 6.4 Dealing with Return Loss Eliminating local and remote echo at their source is the single-best way of ensuring design robustness. Specific steps that help reduce return loss include: 1. Be aware of the return loss issue. Careful consideration will go along way in prevention. 2. Carefully select and design all components. Return loss problems are usually created by parasitic inductances and capacitances that can be reduced by careful component selection and design: Carefully select magnetics. Keep trace lines as short as possible. Keep vias to a minimum. 3. Measure final product return loss with a network analyzer and make any necessary modifications to ensure it meets the requirement. 20 Application Note

21 7.0 Magnetic and Clock Reference 7.1 Magnetics Information The LXT1000 requires simple 1:1 (non-hybrid) magnetics with 4 channels. All channels are used simultaneously for transmit and receive of 4DPAM5 waveforms. Table 1 and Table 2 list requirements and manufacturers, respectively. The manufacturers list is only a reference, not a recommendation. The system designer must ensure that all components are suitable for the intended application. Table 1. Magnetics Requirements Parameter Min Nom Max Units Test Condition Turns Ratio 1:1 Insertion Loss db MHz MHz MHz MHz Primary Inductance 350 µh Transformer Isolation 1.5 kv Differential to common mode rejection db MHz MHz MHz Common to common mode rejection 30 db MHz Return Loss db MHz MHz MHz MHz Crosstalk db MHz MHz MHz Rise Time ns 10% to 90% Table 2. Magnetic Manufacturers Vendor Belfuse Delta Halo Pulse PCA Part Number S M9 LF9202 TG1G-S001NZ H5004, H5007 EPG4001S Application Note 21

22 7.2 Clock Source The LXT1000 requires a 25 MHz clock source that meets the requirements shown in Table 3. The recommended source is a fundamental-mode, parallel-resonant crystal. Crystal manufacturers and part numbers are listed in Table 4. Designers should test and validate all crystals before committing to a specific component. Table 3. Clock Requirements Parameter Min Nom Max Units Test Condition Frequency 25.0 MHz Frequency Stability ±100 ppm -40 o C +85 o C Jitter ps Rise Time 6 ns Table 4. Crystal Manufacturers Manufacturer Epson America Caliber Electronics Part Number MA M AA18C MHz 22 Application Note

23 8.0 Additional Layout Considerations 8.1 RBIAS The RBIAS input of the LXT1000 requires a 1%, 10.7 kω resistor. Follow these guidelines: Place the resistor as close as possible to the RBIAS ball. Connect one side of the resistor to the RBIAS ball with a short, direct trace without any vias. Attach the other side of the resistor to ground. Do not run high-speed signals through this area. 8.2 GBIAS Tie the GBIAS balls together and place a 0.1 µf ceramic capacitor between the tie-point and ground. 8.3 Hardware Control Interface The Hardware Control Interface balls configure the LXT1000 at power-up. In general, hard-tie them to the power or ground planes. (This does not include the LED balls.) 8.4 LED Balls The LXT1000 provides seven bi-directional 10 ma LED outputs, which also function as configuration inputs at power-up. Never hard-wire the LED balls directly to power or ground. If the LED output function of any of these balls is not used, tie to VCC or ground using a 10 kω pull-up or pull-down resistor. If the LED function is used, place a 180 Ω pull-up or pull-down resistor in series with the LED. The correct circuit for all four configurations is shown in Figure 14. For information on LED use and function, refer to the LXT1000 Data Sheet. Application Note 23

24 Figure 14. LED Termination Circuitry LED Output Function +3.3 V +3.3 V Pull-Up with LED 180 Ω Pull-Up without LED 10K Ω 100 ΚΩ LED Output LED Pin LED Output LED Pin Pull-Down with LED 180 Ω Pull-Down without LED 10K Ω 8.5 Quick Status Output The LXT1000 provides a Quick Status feature for monitoring the status and speed of autonegotiation. Quick Status also reports RX, TX, and COL. The LXT1000 provides continuous information on the current state of the device via the Quick Status data ball (QSTAT). A separate, 25 MHz input clock line (QCLK) provides synchronization for the data ball. The LXT1000 sources this information on the falling edge of the QCLK. Quick Status information is unsolicited (no need to issue read requests), which is ideal for hardware applications requiring constant monitoring. Refer to the LXT1000 data sheet for Quick Status Register details. 8.6 MAC Interface The LXT1000 MAC Interface facilitates system integration with Media Access Controllers (MACs) with the Gigabit Media Independent Interface (GMII). This interface is a superset of the MII interface providing support for 1000BASE-T, with fallback support to 100BASE-TX and 10BASE-T. 24 Application Note

25 8.6.1 GMII Considerations The LXT1000 meets the following IEEE electrical specifications: Clause 35.4 GMII electrical characteristics Clause 22.4 MII electrical characteristics AC Specifications The GMII AC specifications are shown in Figure 15. These specifications require that any GMII output driver have a rise/fall time of less than 1 ns when switching a 5 pf load from the low voltage (0.7V) to the high voltage (1.9V), when driving through a 50Ω, 1-ns-long transmission line. All of the LXT1000 GMII outputs meet this requirement (which implies a switching current of at least 6 ma). Placing significantly larger loads on the bus may result in the output not meeting the 1 ns rise/ fall time requirement. Figure 15. GMAC Specifications V H_AC V L_AC T R T F T R, T F < 1 ns V L_AC = 0.7V V H_AC = 1.9V DC Specifications The GMII DC specifications require a minimum VOH of 1.9V; the MII DC specifications require a minimum VOH of 2.4V. The GMII/MII output of the LXT1000 meets both requirements by providing a typical/minimum VOH of 2.6V. An on-chip regulator provides a separate 2.6V power supply for this purpose to the GMII balls. This allows the LXT1000 to meet the requirements of the standard, while minimizing signal swing on the GMII bus, which helps reduce power requirements and EMI emissions Timing The GMII specification assumes a 50Ω transmission line and 50Ω source impedance for any output drivers. The LXT1000 GMII output drivers have a typical source impedance of 8-12Ω; therefore, it is advised that a 42Ω series resistor be added to all GMII outputs, placed as close as possible to the LXT1000 (RX_D, RX_DV, RX_ER, RX_CLK, CRS, and COL). Application Note 25

26 Figure 16. Recommended LXT1000 GMII Output Circuit Driver 42Ω 50Ω 1 ns 5 pf Source 8-12Ω GTX_CLK The GMII specification requires that all output balls provide at least 2.5 ns of setup and 0.5 ns of hold time with regard to their respective clock, and that all input balls require no more than 2.0 ns of setup and 0.0 ns of hold. In order to meet this requirement, the PCB designer must ensure that the differential delay between any GMII signal and its respective clock is no more than 500 ps. Even though the LXT1000 does not directly use GTX_CLK to drive its transmitter timing (it uses an internal transmit PLL that is synchronized to the XI/XO input), GTX_CLK must meet the same frequency tolerance specifications (125 MHz +/- 100 ppm) required for the transmitter. 8.7 Test Output Signals The PAUSE and DUPLEX balls have a special test function in addition to their normal function as configuration balls. Enable this test mode by setting MII Register Bit = 1. When enabled, the PAUSE and DUPLEX balls become TX_TCLKP and TX_TCLKN, respectively, as defined in section of IEEE 802.3ab standard. During this test mode, the LXT1000 emits a 125 MHz timing reference on TX_TCLKP and TX_TCLKN, which can be used to measure transmit jitter and other PMD parameters. This test mode is optional. Follow these guidelines if taking advantage of this test mode function: Run short 50Ω traces from the DUPLEX and PAUSE balls to test points (such as SMA connectors) for monitoring this signal pair. Follow the same guidelines used for any high-speed differential signals: run the traces differentially, with no breaks or vias, and with no breaks in ground or VCC planes adjacent to the traces. Attach a 50Ω, 1% resistor from each trace to the analog VCC plane. In most applications, the desired setting for these balls as configuration inputs is High. If the desired configuration input setting is Low, pull the DUPLEX and PAUSE balls to ground with a 10K Ω resister and insert jumpers between the traces and the 50Ω pull-up resistors. To run the device in test mode, install the jumpers; for normal operation, remove them. 26 Application Note

27 8.8 5V Tolerance Considerations The inputs of the LXT1000 are 5V-compliant, therefore, they tolerate 5V signal levels, even though the device is powered to 3.3V. This also applies to the inputs on the GMII interface. Driving the GMII pads with 5V logic, however, may affect set-up and hold times, which must be calculated at the 1.5V threshold of the GMII. On the output side, the MAC Interface always drives GMIIcompatible signals in all modes - GMII, MII, and Serial (10 Mbps). Note that 5V logic on the other side of the GMII interface may not be able to detect signals because the switching thresholds are too low. 8.9 XI/XO Interface The XI/XO interface is the timing source for the LXT1000 device. This timing source must meet its requirements, especially if the LXT1000 is likely to be the link MASTER. As the MASTER, the LXT1000 provides the timing source not only for itself, but its link partner as well. This is especially the case for switch applications, which are intended by the standard to generally be the MASTER side of the link. The LXT1000 XI/XO input can be supplied either from a crystal or by a clock driver circuit into the XI ball. In either case, the supplied frequency must be 25 MHz +/- 100 ppm under all conditions. The clock source must have an ultra-low jitter. The LXT1000 transmit PLL must have an unfiltered peak-to-peak jitter of no more than 1.4 ns. When filtered with a 5 khz high-pass filter, however, it can have a total peak-to-peak jitter of no more than 300 ps. To meet this requirement, the jitter present at the XI input must be far less; ps is advised. When selecting a crystal, use a fundamental-mode, parallel-resonant device with an effective series resistance of no more than 50Ω. The input capacitance of the LXT1000 XI/XO balls is approximately 3 pf. To derive the values of the external load capacitors, double the rated load capacitance of the crystal (typically 18 pf) and subtract the load capacitance of the ball (3 pf), for a typical value of pf. Ensure the signal traces between the crystal and LXT1000 are as short as possible, with no vias if possible. When selecting a crystal oscillator or clock driver, ensure the signal meets the jitter requirements and is monotonic. For clock-driver applications, provide a separate clock line to each individual transceiver, rather than T-ing one clock line to several devices, which often creates reflections and glitches in the signal. In addition, offset the traces so each device is out-of-phase with its neighbors For EMI reasons, do not run all devices at exactly the same phase. Application Note 27

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