RISC Processor Design

Transcription

1 RISC Processor Design Single Cycle Implementation - MIPS Virendra Singh Indian Institute of Science Bangalore virendra@computer.orgorg Lecture 13 SE-273: Processor Design

2 Courtesy: Prof. Vishwani Agrawal Feb 13,

3 MIPS Instructions ti MIPS assembly language Category Instruction Example Meaning Comments add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers add immediate addi $s1, $s2, 100 $s1 = $s Used to add constants load w ord lw $s1, 100($s2) $s1 = Memory[$s Word from memory to register store w ord sw $s1, 100($s2) Memory[$s ] = $s1 Word from register to memory Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s Byte from memory to register store byte sb $s1, 100($s2) Memory[$s ] = $s1 Byte from register to memory load upper lui $s1, 100 $s1 = 100 * 2 16 Loads constant in upper 16 bits immediate branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC branch on not equal bne $s1, $s2, 25 if ($s1!= $s2) go to Conditional PC branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0 set less than immediate slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0 Equal test; PC-relative branch Not equal test; PC-relative Compare less than; for beq, bne Compare less than constant jump j 2500 go to Jump to target address Uncondi- jump register jr $ra go to $ra For sw itch, procedure return tional jump jump and link jal 2500 $ra = PC + 4; go to For procedure call Feb 13, 2010 SE-273@SERC 3

4 MIPS Registers and Memory $s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always ays equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. Memory[0], Accessed only by data transfer instructions. MIPS uses byte 2 30 memorymemory[4],..., addresses, so sequential words differ by 4. Memory holds data words Memory[ ] structures, such as arrays, and spilled registers, such as those saved on procedure calls. Feb 13, 2010 SE-273@SERC 4

5 Example Addressing Modes addi 1. Im mediate addressing op rs rt Immediate add 2. Register addressing o p rs r t rd... fu n c t R egis ters Register lw, sw 3. Base addressing op rs rt Address Register + Memory Byte Halfword Word beq, bne 4. P C -re la tiv e a d d re s s in g op rs rt Address Memory PC + Word j 5. Pseudodirect addressing op Address PC Memory Word 2004 Morgan Kaufman Publishers Feb 13, 2010 SE-273@SERC 5

6 MIPS Instruction Set MIPS Instruction Subset Arithmetic and Logical Instructions add, sub, or, and, slt Memory reference Instructions lw, sw Branch beq, j Feb 13, 2010 SE-273@SERC 6

7 Overview of MIPS simple instructions, ti all 32 bits wide very structured, no unnecessary baggage only three instruction formats R I J op rs1 rs2 rd shmt op rs1 rd 16 bit address op 26 bit address funct rely on compiler to achieve performance 2004 Morgan Kaufman Publishers Feb 13, 2010 SE-273@SERC 7

8 Where Does It All Begin? In a register called program counter (PC). PC contains the memory address of the next instruction to be executed. In the beginning, PC contains the address of the memory location where the program begins. Feb 13, 2010 SE-273@SERC 8

9 Where is the Program? Processor Memory Program counter (register) Start address Machine code of program Feb 13,

10 How Does It Run? Start PC has memory address where program begins Fetch instruction word from memory address in PC and increment PC PC + 4 for next instruction Decode and execute instruction No Program complete? Yes STOP Feb 13, 2010 SE-273@SERC 10

11 Datapath and Control Datapath: Memory, registers, adders, ALU, and communication buses. Each step (fetch, decode, execute) requires communication (data transfer) paths between memory, registers and ALU. Control: Datapath for each step is set up by control signals that set up dataflow directions on communication buses and select ALU and memory functions. Control signals are generated by a control unit consisting of one or more finite-state machines. Feb 13, 2010 SE-273@SERC 11

12 Datapath for Instruction Fetch 4 Add PC Address Instruction Memory Instruction word to control unit and registers Feb 13, 2010 SE-273@SERC 12

13 Register File: A Datapath Component Read registers Write register reg 1 reg 2 32 Registers (reg. file) reg 1 data reg 2 data Write data 32 RegWrite from control Feb 13, 2010 SE-273@SERC 13

14 Multi-Operation ALU Operation select ALU function 000 AND 001 OR 010 Add 110 Subtract 111 Set on less than Operation select from control 3 zero ALU result overflow zero = 1, when all bits of result are 0 Feb 13, 2010 SE-273@SERC 14

15 R-Type Instructions Also known as arithmetic-logical instructions add, sub, slt Example: add $t0, $s1, $s2 Machine instruction word opcode $s1 $s2 $t0 function Read two registers Write one register Opcode and function code go to control unit that generates RegWrite and ALU operation code. Feb 13,

16 Datapath for R-Type Instruction Operation opcode $s1 $s2 $t0 function (add) select from control (add) Read 5 $s1 register 32 3 numbers 5 zero $s2 32 Registers ALU Write reg. (reg. file) number 32 5 overflow $t result Write data 32 RegWrite from control activated Feb 13, 2010 SE-273@SERC 16

17 Load and Store Instructions I-type instructions lw $t0, 1200 ($t1) # incr. in bytes opcode $t1 $t sw $t0, 1200 ($t1) # incr. in bytes opcode $t1 $t Feb 13, 2010 SE-273@SERC 17

18 Datapath for lw Instruction Read register numbers opcode $t1 $t Write reg. number 5 Write data $t1 $t0 32 Registers (reg. file) 032 RegWrite from control activated 16 Sign extend 32 ALU 3 Operation select from control (add) zero overflow result mem. data to $t0 Addr. Write data MemWrite Read data Data memory MemRead activated Feb 13, 2010 SE-273@SERC 18

19 Datapath for sw Instruction Read register numbers Write reg. number opcode $t1 $t Write data $t1 $t Registers (reg. file) RegWrite from control Sign extend ALU 3 Operation select from control (add) zero overflow 32 result $t0 data to mem. MemWrite activated Addr. Write data Read data Data memory MemRead Feb 13, 2010 SE-273@SERC 19

20 Branch Instruction (I-Type) beq $s1, $s2, 25 # if $s1 = $s2, advance PC through 25 instructions 16-bits opcode $s1 $s2 25 Note: Can branch within ± 2 15 words from the current instruction address in PC. Feb 13, 2010 SE-273@SERC 20

21 Datapath for beq Instruction Read register numbers Write reg. number Write data $s1 $s2 Sign extend 32 Registers (reg. file) RegWrite from control 32 Shift left opcode $s1 $s Operation select from control (subtract) 3 ALU zero overflow PC+4 From instruction fetch datapath 32 result 32 To branch control logic Add Branch target 32 Feb 13, 2010 SE-273@SERC 21

22 J-Type Instruction j 2500 # jump to instruction 2, bits opcode 2, bit jump address bits from PC+4 Feb 13, 2010 SE-273@SERC 22

23 Datapath for Jump Instruction Branch Branch 4 addr. 1 mux Add 32 0 PC+4 Jump mux 1 4 PC Address Instruction Memory Shift left 2 28 opcode (bits 26-31) to control 6 Instruction word to control and registers Feb 13, 2010 SE-273@SERC 23

24 PC 4 Ad dd Instr. mem. Combined Datapaths Reg gdst Shift Jump opcode left 2 CON NTROL mux 0 1 Reg. File Sign Shift ext. left 2 Branch 1 mux 0 ALU AL LU ALU Cont. 1 mux 0 0 mux 1 zero MemWrite MemRead Data mem. MemtoReg 0 mux 1 Feb 13, 2010 SE-273@SERC 24

25 Control Instruction bits opcode Instruction bits 0-5 funct. Control Logic ALUOp 2 RegDst Jump Branch MemRead MemtoReg MemWrite ALUSrc RegWrite ALU Control Feb 13, 2010 SE-273@SERC 25 to ALU

26 Control Logic: Truth Table Instr type Inputs: instr. opcode bits Outputs: t control signals RegD st Jump ALUS rc MemtoR Reg RegWr rite MemRe ead MemW Write Branc ch ALOO p1 ALUOp p2 R lw sw X 0 1 X beq X 0 0 X j X 1 X X X X X X X X Feb 13, 2010 SE-273@SERC 26

27 How Long Does It Take? Assume control logic is fast and does not affect the critical timing. Major time delay components are ALU, memory read/write, and register read/write. Arithmetic-type type (R-type) Fetch (memory read) Register read ALU operation Register write Total 2ns 1ns 2ns 1ns 6ns Feb 13,

28 Time for lw and sw (I-Types) ALU (R-type) Load word (I-type) Fetch (memory read) 2ns Register read 1ns ALU operation 2ns Get data (mem. Read) 2ns Register write 1ns Total Store word (no register write) 7ns 6ns 8ns Feb 13,

29 Time for beq (I-Type) ALU (R-type) Load word (I-type) Store word (I-type) Branch on equal (I-type) Fetch (memory read) Register read ALU operation Total 6ns 8ns 7ns 2ns 1ns 2ns 5ns Feb 13,

30 Time for Jump (J-Type) ALU (R-type) 6ns Load word (I-type) 8ns Store word (I-type) 7ns Branch on equal (I-type) 5ns Jump (J-type) Fetch (memory read) 2ns Total 2ns Feb 13,

31 How Fast Can the Clock Be? If every instruction is executed in one clock cycle, then: Clock period must be at least 8ns to perform the longest instruction, i.e., lw. This is a single cycle machine. It is slower because many instructions take less than 8ns but are still allowed that t much time. Method of speeding up: Use multicycle datapath. th Feb 13, 2010 SE-273@SERC 31

32 A Single Cycle Example a31... a2 a1 a0 b31... b2 b1 b0 0 Delay of 1-bit full adder = 1ns Clock period 32ns 1-b full adder 1-b full adder 1-b full adder 1-b full adder Time of adding words ~ 32ns Time of adding bytes ~ 32ns c32 s31... s2 s1 s0 Feb 13, 2010 SE-273@SERC 32

33 A Multicycle Implementation Sh hift Shift a31... a2 a1 a0 b31... b2 b1 b0 Delay of 1-bit full adder = 1ns Clock period 1ns Time of adding words ~ 32ns Time of adding bytes ~ 8ns c32 1-b bfull adder FF Initialize to 0 s31... s2 s1 s0 Feb 13, 2010 SE-273@SERC 33 Shift

34 Multicycle Datapath PC Memory Instr. reg. Data (MDR) Register file ALU A Reg. ALUOut Reg. (IR) Addr. Data 4 Mem. B Reg. One-cycle data transfer paths (need registers to hold data) Feb 13, 2010 SE-273@SERC 34

35 Multicycle Datapath Requirements Only one ALU, since it can be reused. Single memory for instructions and data. Five registers added: Instruction register (IR) Memory data register (MDR) Three ALU registers, A and B for inputs and ALUOut for output Feb 13, 2010 SE-273@SERC 35

36 Multicycle Datapath Shift left 2 PCSource C Memory Instr. reg. (IR) Register file A Reg. PCWrite etc. ALUOut Reg to Control FSM RegWrite B Reg. (MDR) ALU P Addr ALUSrcA ALUSrcB IorD Mem. Data MUX out in1 in2 control Data IRWrite RegDst 4 MemRead MemWrite MemtoReg Sign extend Shift left 2 ALU control Feb 13, 2010 SE-273@SERC 36 ALUOp

37 Step Instruction fetch 3 to 5 Cycles for an Instruction R-type Mem. Ref. Branch type J-type (4 cycles) (4 or 5 cycles) (3 cycles) (3 cycles) IR Memory[PC]; PC PC+4 Instr. decode/ A Reg(IR[21-25]); B Reg(IR[16-20]) Reg. fetch ALUOut PC + (sign extend IR[0-15]) << 2 Execution, addr. Comp., branch & jump completion ALUOut A op B Mem. Access Reg(IR[11- MDR M[ALUout] or R-type 15]) or M[ALUOut] B completion ALUOut Memory read Reg(IR[16-20]) completion MDR ALUOut A+sign extend If (A= =B) then PC PC[28-31] (IR[0-15]) PC ALUOut (IR[0-25]<<2) Feb 13, 2010 SE-273@SERC 37

38 Cycle 1 of 5: Instruction Fetch (IF) Read instruction into IR, M[PC] IR Control signals used: IorD = 0 select PC MemRead = 1 read memory IRWrite = 1 write IR Increment PC, PC + 4 PC Control signals used: ALUSrcA = 0 select PC into ALU ALUSrcB = 01 select constant 4 ALUOp = 00 ALU adds PCSource = 00 select ALU output PCWrite = 1 write PC Feb 13, 2010 SE-273@SERC 38

39 Cycle 2 of 5: Instruction Decode (ID) R I opcode reg 1 reg 2 reg 3 shamt fncode opcode reg 1 reg 2 word address increment J opcode word address jump Control unit decodes instruction Datapath prepares for execution R and I types, reg 1 A reg, reg 2 B reg No control signals needed Branch type, compute branch address in ALUOut ALUSrcA = 0 select PC into ALU ALUSrcB = 11 Instr. Bits 0-15 shift 2 into ALU ALUOp = 00 ALU adds Feb 13, 2010 SE-273@SERC 39

40 Cycle 3 of 5: Execute (EX) R type: execute function on reg A and reg B, result in ALUOut Control signals used: ALUSrcA = 1 A reg into ALU ALUsrcB = 00 B reg into ALU ALUOp = 10 instr. Bits 0-5 control ALU I type, lw or sw: compute memory address in ALUOut A reg + sign extend IR[0-15] Control signals used: ALUSrcA = 1 A reg into ALU ALUSrcB = 10 Instr. Bits 0-15 into ALU ALUOp = 00 ALU adds Feb 13, 2010 SE-273@SERC 40

41 Cycle 3 of 5: Execute (EX) I type, beq: subtract reg A and reg B, write ALUOut to PC Control signals used: ALUSrcA = 1 A reg into ALU ALUsrcB = 00 B reg into ALU ALUOp = 01 ALU subtracts If zero = 1, PCSource = 01 ALUOut to PC If zero = 1, PCwriteCond =1 write PC Instruction complete, go to IF J type: write jump address to PC IR[0-25] shift 2 and four leading bits of PC Control signals used: PCSource = 10 PCWrite = 1 write PC Instruction complete, go to IF Feb 13, 2010 SE-273@SERC 41

42 Cycle 4 of 5: Reg Write/Memory R type, write destination register from ALUOut Control signals used: RegDst = 1 Instr. Bits specify reg. MemtoReg = 0 ALUOut into reg. RegWrite = 1 write register Instruction complete, go to IF I type, lw: read M[ALUOut] into MDR Control signals used: IorD = 1 select ALUOut into mem adr. MemRead ead = 1 read memory to MDR I type, sw: write M[ALUOut] from B reg Control signals used: IorD = 1 select ALUOut into mem adr. MemWrite = 1 write memory Feb 13, 2010 SE-273@SERC 42 Instruction complete, go to IF

43 Cycle 5 of 5: Reg Write I type, lw: write MDR to reg[ir(16-20)] Control signals used: RegDst = 0 instr. Bits are write reg MemtoReg = 1 MDR to reg file write input RegWrite = 1 read memory to MDR Instruction complete, go to IF For an alternative method of designing datapath, see N. Tredennick, Microprocessor Logic Design, the Flowchart Method, Digital Press, Feb 13, 2010 SE-273@SERC 43

44 1-bit Control Signals Signal name Value = 0 Value =1 RegDst Write reg. # = bit Write reg. # = bit RegWrite No action Write reg. Write data ALUSrcA First ALU Operand PC First ALU Operand Reg. A MemRead No action Mem.Data Output M[Addr.] t MemWrite No action M[Addr.] Mem. Data Input MemtoReg Reg.File Write In ALUOut Reg.File Write In MDR IorD Mem. Addr. PC Mem. Addr. ALUOut IRWrite No action IR Mem.Data Output PCWrite No action PC is written PCWriteCond No action PC is written if zero(alu)=1 zero(alu) PCWriteCond PCWrite PCWrite etc. Feb 13, 2010 SE-273@SERC 44

45 2-bit Control Signals Signal name Value Action ALUOp ALUSrcB PCSource 00 ALU performs add 01 ALU performs subtract 10 Funct. field (0-5 bits of IR ) determines ALU operation 00 Second input of ALU B reg. 01 Second input of ALU 4 (constant) 10 Second input of ALU 0-15 bits of IR sign ext. to 32b 11 Second input of ALU 0-15 bits of IR sign ext. and left shift 2 bits 00 ALU output (PC +4) sent to PC 01 ALUOut (branch target addr.) sent to PC 10 Jump address IR[0-25] shifted left 2 bits, concatenated with PC+4[28-31], sent to PC Feb 13, 2010 SE-273@SERC 45

46 Control: Finite State Machine Clock cycle 1 Clock cycle 2 State 1 State 0 Start Instruction fetch Instruction decode and register fetch Clock cycles 3-5 FSM-M Memory access instr. FSM-R FSM-B FSM-J R-type instr. Branch instr. Jump instr. Feb 13, 2010 SE-273@SERC 46

47 State 0: Instruction Fetch (CC1) PCSource=00 MUX in1 PCW Write etc..=1 C P IorD=0 out in2 control Addr. Data Me emory to Control FSM Instr. re eg. (IR) IRWrite = Me em. Data (MDR) Re egister fil le RegDst RegWrite A Reg. B Reg g. AL LUSrcA=0 Shift left AL LUSrcB=01 4 ALU Add ALU UOut Reg g. MemRead = 1 MemWrite MemtoReg Sign extend Shift left 2 ALU control Feb 13, 2010 SE-273@SERC 47 ALUOp =00

48 State 0 Control FSM Outputs State0 Instruction fetch Start MemRead =1 ALUSrcA = 0 IorD = 0 IRWrite = 1 ALUSrcB = 01 ALUOp = 00 PCWrite = 1 PCSource = 00 State 1 Instruction decode/ Register fetch/ Branch addr. Outputs? Feb 13, 2010 SE-273@SERC 48

49 State 1: Instr. Decode/Reg. Fetch/ Branch Address (CC2) PCSource MUX in1 IorD PCW Write etc c. out C P in2 control Addr. Data Me emory to Control FSM Instr. re eg. (IR) IRWrite Me em. Data (MDR) Re egister fil le RegDst RegWrite A Reg. B Reg g. ALUSrcA=0 Shift left AL LUSrcB=11 4 ALU Add ALU UOut Reg g. MemRead MemWrite MemtoReg Sign extend Shift left 2 ALU control Feb 13, 2010 SE-273@SERC 49 ALUOp = 00

50 State 1 Control FSM Outputs State0 Instruction fetch (IF) Start MemRead =1 ALUSrcA = 0 IorD = 0 IRWrite = 1 ALUSrcB = 01 ALUOp = 00 PCWrite = 1 PCSource = 00 State 1 Instruction ti decode d (ID) / Register fetch / Branch addr. ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Opcode = BEQ Opcode = J-type FSM-M FSM-R FSM-B FSM-J Feb 13, 2010 SE-273@SERC 50

51 State 1 (Opcode = lw) FSM-M (CC3-5) CC4 PCSource MUX in1 PCW Write etc c. C P IorD=1 out in2 control Addr. Data Me emory to Control FSM Instr. re eg. (IR) IRWrite Me em. Data (MDR) Re egister fil le RegWrite=1 CC5 RegDst=0 A Reg. B Reg g. ALUSrcA=1 Shift left AL LUSrcB=10 4 CC3 ALU Add ALU UOut Reg g. MemRead=1 MemWrite MemtoReg= Sign extend Shift left 2 ALU control Feb 13, 2010 SE-273@SERC 51 ALUOp = 00

52 State 1 (Opcode= sw) FSM-M (CC3-4) CC4 Shift left 2 PCSource C Instr. reg. (IR) Register file A Reg. PCWrite etc. ALUOut Reg to Control FSM RegWrite CC3 P Memory B Reg. Addr. (MDR) ALUSrcA=1 ALUSrcB=10 ALU IorD=1 Mem. Data out Data IRWrite RegDst=0 MUX control Add in1 in2 CC4 4 MemRead MemWrite=1 MemtoReg Sign extend Shift left 2 ALU control Feb 13, 2010 SE-273@SERC 52 ALUOp = 00

53 FSM-M (Memory Access) From state 1 Opcode = lw or sw Read Memory data Opcode Compute mem addrress ALUSrcA =1 ALUSrcB = 10 ALUOp = 00 = lw = sw Opcode Write memory MemRead = 1 IorD = 1 MemWrite = 1 IorD = 1 Write register RegWrite = 1 MemtoReg = 1 RegDst = 0 To state 0 (Instr. Fetch) Feb 13, 2010 SE-273@SERC 53

54 State 1(Opcode=R-type) FSM-R R (CC3-4) PCSource MUX in1 IorD PCW Write etc c. out C P in2 control Addr. Data Me emory to Control FSM Instr. re eg. (IR) IRWrite Me em. Data (MDR) Re egister fil le RegWrite A Reg CC3 RegDst=0 CC4 B Reg g. ALUSrcA=1 Shift left AL LUSrcB=00 0 ALU ALU UOut Reg g. 4 funct. code MemRead MemWrite MemtoReg= Sign extend Shift left 2 ALU control Feb 13, 2010 SE-273@SERC 54 ALUOp = 10

55 FSM-R (R-type Instruction) From state t 1 Opcode = R-type ALU operation ALUSrcA =1 ALUSrcB = 00 ALUOp = 10 Write register RegWrite = 1 MemtoReg = 0 RegDst = 1 To state 0 (Instr. Fetch) Feb 13, 2010 SE-273@SERC 55

56 State 1 (Opcode = beq ) FSM-B (CC3) If(zero) Shift left 2 PCSource 01 C Instr. reg. (IR) to Control FSM Register file A Reg. ALUOut Reg. PCWrite etc..= RegWrite P Memory B Reg. Addr. (MDR) ALUSrcA=1 ALUSrcB=000 ALU IorD CC3 Mem. Data zero MUX out in1 in2 control Data IRWrite RegDst 4 subtract MemRead MemWrite MemtoReg Sign extend Shift left 2 ALU control ALUOp = 01 Feb 13, 2010 SE-273@SERC 56

57 Write PC on zero zero=1 PCWriteCond=1 PCWrite PCWrite etc.=1 Feb 13,

58 FSM-B (Branch) From state 1 Opcode = beq Write PC on branch condition ALUSrcA =1 ALUSrcB = 00 ALUOp = 01 PCWriteCond=1 PCSource=01 Branch condition: If A B=0 zero = 1 To state 0 (Instr. Fetch) Feb 13, 2010 SE-273@SERC 58

59 MUX in1 PCWrite etc. IorD PC out in2 State 1 (Opcode = j) FSM-J (CC3) Dat a control Addr. Mem MemRead MemWrite to Control moryfsm In nstr. reg. (IR) IRWrite Mem m. Data (M MDR) MemtoReg CC3 RegWrite Regis ster file RegDst A Reg. B Reg. SrcA ALU Shift left ALUS SrcB 4 LU AL zero Sign Shift extend left 2 ALU control Feb 13, 2010 SE-273@SERC PCSource 10 ALUOu ut Reg. ALUOp

60 Write PC zero PCWriteCond PCWrite=1 PCWrite etc.=1 Feb 13,

61 FSM-J (Jump) From state 1 Opcode = jump Write jump addr. In PC PCWrite=1 PCSource=10 To state 0 (Instr. Fetch) Feb 13, 2010 SE-273@SERC 61

62 Control FSM 3 Read memory data Start State 0 Instr. fetch/ adv. PC lw 2 Compute memory addr. sw Write Write register memory data 6 1 Instr. decode/reg. fetch/branch addr. R B ALU Write PC Write operation on branch jump addr. condition to PC 8 9 Write register J Feb 13, 2010 SE-273@SERC 62

63 Control FSM (Controller) 6 inputs (opcode) Combinational logic 16 control outputs Present state Next state Reset Clock FF FF FF FF Feb 13, 2010 SE-273@SERC 63

64 Designing the Control FSM Encode states; need 4 bits for 10 states, e.g., State 0 is 0000, state 1 is 0001, and so on. Write a truth table for combinational logic: Opcode Present state Control signals Next state Synthesize a logic circuit from the truth table. Connect four flip-flops between the next state outputs and present state inputs. Feb 13, 2010 SE-273@SERC 64

65 MemWrite Block Diagram of a Processor ALU control MemRead Controller (Control FSM) ALUOp 2-bits funct. [0,5] ALUOp 3-bits Opcode 6-bits zero Overflow ALUSrcAA ALUSrcB 2-bits PCSource 2-bits RegDst RegWritee MemtoReg IorD IRWrite PCWrite PCWriteCon nd Reset Clock Mem. Addr. Datapath (PC, register file, registers, ALU) Mem. write data Mem. data out Feb 13, 2010 SE-273@SERC 65

66 Exceptions or Interrupts Conditions under which h the processor may produce incorrect result or may hang. Illegal or undefined opcode. Arithmetic overflow, divide by zero, etc. Out of bounds memory address. EPC: 32-bit register holds the affected instruction address. Cause: 32-bit register holds an encoded exception type. For example, 0 for undefined instruction 1f for arithmetic ti overflow Feb 13, 2010 SE-273@SERC 66

67 PCWrite etc.=1 PC MUX in1 out Implementing Exceptions in2 control to Control FSM R) r. reg. (I Inst 0 1 CauseWrite=1 Cause 32-bit register (hex) ALUSrc ca=0 ALUSrcB B=01 4 ALU ALU control Feb 13, 2010 SE-273@SERC 67 PCSource 11 EPCWrite=1 EPC Overflow to Control FSM Subtract ALUOp =01

68 How Long Does It Take? Again Assume control logic is fast and does not affect the critical timing. Major time components are ALU, memory read/write, and register read/write. Time for hardware operations, suppose Memory read or write Register read ALU operation Register write 2ns 1ns 2ns 1ns Feb 13,

69 Single-Cycle Datapath R-type 6ns Load word (I-type) 8ns Store word (I-type) 7ns Branch on equal (I-type) 5ns Jump (J-type) 2ns Clock cycle time = 8ns Each instruction takes one cycle Feb 13, 2010 SE-273@SERC 69

70 Multicycle Datapath Clock cycle time is determined by the longest operation, ALU or memory: Clock cycle time = 2ns Cycles per instruction (CPI): lw 5 (10ns) sw 4 (8ns) R-type 4 (8ns) beq 3 (6ns) j 3 (6ns) Feb 13, 2010 SE-273@SERC 70

71 CPI of a Computer k (Instructions of type k) CPI k CPI = k (instructions ti of type k) where CPI k = Cycles for instruction of type k Note: CPI is dependent on the instruction mix of the program being run. Standard benchmark programs are used for specifying the performance of CPUs. Feb 13, 2010 SE-273@SERC 71

72 Example Consider a program containing: i loads 25% stores 10% branches 11% jumps 2% Arithmetic 52% CPI = = 4.12 for multicycle datapath CPI = 1.00 for single-cycle datapath Feb 13, 2010 SE-273@SERC 72

73 Multicycle vs. Single-Cycle Performance ratio = Single cycle time / Multicycle time (CPI cycle time) for single-cycle = (CPI cycle time) for multicycle ns = = ns Single cycle is faster in this case, but remember, performance ratio depends on the instruction mix. Feb 13, 2010 SE-273@SERC 73

74 Thank You Feb 13,