Fundamental Material Properties

Transcription

1 Fundamental Material Properties Dielectric Constant Thermal Expansion Coefficient Thermal Conductivity Processing Temperature Decomposition Temperature

2 HyperBGA HyperBGA is a registered trademark of Endicott Interconnect

3 ASIC* (ay-sik) Short for Application-Specific Integrated Circuit. A chip designed for a particular application (as opposed to the integrated circuits that control functions such as RAM in a PC). ASICs are built by connecting existing circuit building blocks in new ways. Since the building blocks already exist in a library, it is much easier to produce a new ASIC than to design a new chip from scratch. ASICs are commonly used in automotive computers to control the functions of the vehicle and in PDAs. * As defined in

4 Physical / Electrical Comparison Layers Substrate Thickness (µm) Dielectric Constant Line width (µm) nominal Line height (µm) nominal Impedance (Z o ) (W) Capacitance (pf/mm) Delay (ps/mm) Coupled Noise 1V/ns) HyperBGA Alumina Ceramic Ceramic is: thicker (5x), heavier and slower

5 Why low D k? Fast signal propagation time, Dielectric υ = c D D k k υ (in/ns) D k all assume Z o = 50 ohms lw h 2 ls h 1 Ceramic Epoxy/Glass PTFE Air also thinner and more tightly spaced. D k all physical dimensions in mils lw ls h 1 h

6 Thermal Stress, σ Silicon Chip Silicon Chip Chip or ceramic substrate or chip T b >> T a σ = E( T) α( T) dt T 2 σ = ( α ( T) α ( T)) E ( T) dt T 1 p c p E Youngs Modulus α Coefficient of thermal expansion (CTE) α p CTE of polymer CTE of chip α c

7 Thermal Stress Linear Expansion α 1 α 2 T g Temperature σ = K ( α α ) E( T T) + ( α α ) E ( T T ) 1 c 1 g 1 2 c 2 2 g Lower Composite stress by minimizing the CTE mismatch, lower the modulus, and lower the Tg. Materials lower CTE by resin & filler physical properties / loading

8 CTE Measurement: Thermal Mechanical Analysis Sample: IBM DC Z Size: mm Method: 5C/m N scan 2 Comment: 5C/m RT-225,LN2 cool to RT,5C/m RT-225 sc2 15 TMA File: A:\gktmab.219 Operator: G. Kohut T49 Run Date: 13-Feb :18p 10 Dimension Change (µm) C Alpha=65.5µm/m C C Alpha=340.µm/m C C C C Temperature ( C)

9 TCE Data for Primary Materials in the HyperBGA Composite Thermal Expansion Coefficient 30 TCE (ppm / C) Silica-filled PTFE Cu HyperBGA CIC* Si Temperature (C) Cu Invar Cu Silica Filled PTFE Cu Si HyperBGA * Invar is an alloy of Ni & Fe

10 Mechanical Properties of Packaging Materials Effective Modulus Mpsi Effective TCE ppm/ C T g C Silicon die (crystal) 27 3 Glass ceramic 19 3 Alumina ceramic 44 6 BT resin * 200 BT w/ 2116 cloth * PID soldermask * HyperBGA filled PTFE * Softening > 125 Outer layer dielectric Plated Cu CIC (Cu Invar Cu) Stainless Aluminum * Effective TCE below T g

11 Results of Thermal / mechanical modeling Accelerated reliability testing HyperBGA 0.4mm High Tg Epoxy 0.4mm Epoxy/Glass 0.4mm Epoxy/Glass 1.0mm SLC 1.0mm 42.5mm CCGA 32mm CBGA Relative BGA life for 0/100 C Ceramic Limited BGA fatigue life Very little warpage Component CTE Chip: 3 Ceramic: Thousands PC card: 18 Gore ( 3M ) Must control warpage Adhesive stresses Net: Limited die size Chip: 3 Laminate: 18 PC card: 18 HyperBGA CIC to control expansion Optimized CTE distribution Compliant dielectric Compliant adhesives Low Stress Chip: 3 Laminate: 10 PC card: 18

12 Thermoplastic Dielectric Material -- Silica Filled PTFE Material Composition / Properties i 50% Silica filled PTFE Silane coupler treated Silica mixed w/ PTFE aqueous dispersion Dried / Sintered / Sheeted Thickness: & Electrical properties: D k = 2.8, D f = Lower isotropic CTE = 25 ppm IBM formula versus Rogers formula PTFE is a semi-crystalline polymer

13 Crosslinked polymer Crystals can function like crosslinks Semi-crystalline polymer

14 HyperBGA Laminate Build Process is Sequential Underfill Bump Chip Starts with Ground Plane Inner layer PTFE is laminated Microvia 3rd Outer PTFE 2nd Middle PTFE 1st Inner PTFE Filled PTH BGA pad Soldermask Signal Power Ground CIC 2nd layer laminated Outer layer laminated Inner Layer exposed to three laminations Outer Layer exposed to one lamination What is effect of repeated laminations?

15 The Competition MICROLAM 600 Series Dielectrics Microlam is both thermoplastic & thermosetting MICROLAM 600 Series Microvia Dielectrics have optimized electrical and mechanical properties and consist of a non-woven, continuous toughening matrix and standard epoxy resins. Engineered to resist dielectric cracking and provide improved PCB mechanical reliability in cell phones, PDAs, and other portable devices, these high performance materials are processed using the same equipment and techniques as resin-coated copper and dry films.

16 Heat and Pressure Lamination: Squeezing Flow Cu-Foil Silica filled PTFE Silica filled PTFE (thermoplastic) Cu-Foil Core Panel Silica filled PTFE Epoxy prepreg (thermoset) Heat and Pressure Extreme Engineering: High temperature & pressure required to deform silica filled PTFE and sinter composite.

17 Conclusions For a high performance and high reliability chip package: Use thermal / mechanical modeling to optimize package design and materials selection Minimize the CTE difference between the chip and package Use dielectric material with small particle filler with high filler loading overall low modulus good adhesion to metal layers thermal stability A carefully designed process window is required for robust package performance ductility of dielectric material was a key parameter