Figure 1. Block Diagram Configuring the Si5341/40 with an MCU or Other Controller to Implement Spread Spectrum

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1 A N IMPLEMENTATION OF SPREAD-SPECTRUM CLOCKING USING AN MCU WITH THE Si5341/40 CLOCK GENERATORS One of the most effective approaches to controlling EMI is to use spread spectrum clock generation. Frequency spreading is done by modulating the frequency so the peak energy is lowered and distributed to other frequencies and their harmonics. Instead of a constant frequency, the clock is modulated across a smaller frequency that creates a frequency spectrum with sideband harmonics. By intentionally spreading the narrowband clock across a broader band the peak spectral energy of both the fundamental and harmonic frequencies can be reduced. The modulation frequency typically chosen is khz, with 0.5% down-spread. This comes from the PCIe specification and is the typical modulation profile which is broad enough to spread the energy around the carrier yet narrow enough to avoid creating timing and tracking issues. Some of the Silicon Labs clock generator products have this programmable capability built in, such as the Si5350/51. For products that do not have this capability, it is possible to use an MCU (or FPGA, for example) with the Si5341/40 devices if it has an external increment decrement pin feature for adjusting the output frequency. GPIO pins on the MCU can be used to control incrementing and decrementing the output frequency at a specific calculated time interval. An example of this is shown using the Silicon Labs C8051F850MCU with the Si5341 clock generator. These devices have external frequency increment and decrement pins that are exposed on the device that can be toggled to accomplish the spread spectrum modulation task. Although other Silicon Labs clock generator devices may also include the FINC and FDEC control pins, their register maps are different, and the example below will have different register settings. The same principles apply, and this methodology can be followed for other devices, but be aware that the register map may be different. Figure 1. Block Diagram Configuring the Si5341/40 with an MCU or Other Controller to Implement Spread Spectrum There are various calculations to consider to configure the system to include a modulation frequency of khz with a 0.5% down-spread magnitude. The first thing to consider is the clocking speed of the MCU to know how fast instructions can be set that will toggle the MCU GPIO pins. The C8051F850 MCU system clock speed is set to 24.5 MHz, which is ns (4.1E-08) per SYSCLK cycle. The accuracy of the MCU system clock is also important to consider. The accuracy of this MCU over voltage and temperature is 4.08%, which is adequate for this application. There is a limit on the speed at which the FINC and FDEC pins can be toggled. The frequency to toggle the FINC/ FDEC pin of the Si5341/40 cannot be much higher than 1 MHz. Therefore, the MCU must toggle the FINC or FDEC pin at a rate that causes the transitions to be somewhere below 1 MHz. The second consideration is the minimum number of MCU clock ticks required to perform a uniform high to low transition that can loop indefinitely. The calculations in Table 1 were used to find the edge transition timing. Rev /14 Copyright 2014 by Silicon Laboratories AN876

2 Table 1. MCU FINC/FDEC Transition Timing Optimization SYSCLK ticks per edge Time SYSCLK tick (24.5 MHz) Accumulated Time Per Edge Time Per Cycle (2xEdge) Frequency (1/TimePerCycle) 5 4.1E E E E E E E E E E E E E E E E E E E E-07 9E E E E E E E Figure 2. 5 SYSCLK Ticks per Edge The maximum possible frequency that the MCU can loop with an even repeatable cycle is five SYSCLK ticks per edge (2.4 MHz). This is due to the limitation of the while loop that is controlling the pin toggle. The while loop instruction takes 5 SYSCLK ticks. P0.0 Set 2 cycles Delay 3 cycles P0.0 Clear 2 cycles Delay 3 cycles P0.1 Set 2 cycles Delay 3 cycles P0.1 Clear 2 cycles While Loop 5 cycles 2 Rev. 0.1

3 Figure SYSCLK Ticks per Edge To achieve a toggle frequency slightly under 1 MHz, 13 SYSCLK ticks per edge are used. This means 11 delay cycles are necessary per edge, since a SET and CLEAR instruction take two SYSCLK ticks. From Table 2, the time to decrement by 15 cycles and then increment by 15 cycles (total of 30 cycles) will take 31.8 s, which is a frequency of 31.4 khz = /31.836E-6 = 31.4 khz, which is right in the middle of the PCIe 3.0 Specification (30-33 khz). A total of 30 steps are required, 15 Cycles of FDEC, and 15 cycles of FINC. Table 2. Calculations to Determine the Optimal PCIe Frequency and Number of Steps Required 6 MCU Half Cycles Time Per Clock Time Per Half Cycle Time Per Cycle MCU Frequency Optimal PCIe Fq #Total Steps E E E k E E E k E E E k E E E k E E E k E E E k E E E k E E E k E E E k E E E k 28 Rev

4 Figure 4. Pin Toggling Showing FDEC (P0.0) and FINC (P0.1) From the calculations above in Table 2, using 13 cycles per transition, the frequency controlling FINC and FDEC is set to under 1 MHz. This is well within the toggle frequency range of the MCU and typical FPGAs with general purpose I/O pins. With 15 steps down and 15 steps up, the modulation frequency is 31.4 khz. ClockBuilder Pro is a software tool to configure Si534x device settings to create frequency plans and to configure the clock inputs and outputs. In ClockBuilder Pro a project profile can be set up with 100 MHz for the output frequency. Reviewing the ClockBuilder Pro design report text file N0_NUM at register 0x0302 is set to 0x and N0_DEN is set to 0x The following calculations show how these registers are set: 100 MHz is the output frequency. The is the VCO Frequency in MHz. The denominator is set to 1 and the numerator can be calculated. The resulting value for the numerator and denominator is then left-shifted. NUM = 13600/200 = 68 0x44, left-shifted by 31 bits = 0x ( E11) DEN = 1, left-shifted by 31 bits = 0x ( ) Note: E11/ = DEN = NUM The down-spread for the modulation can be set to be 0.45%, which is slightly below 0.5% per the PCIe specification. Taking 0.45% of 100 MHz is equal to 450,000 Hz. So 450,000 Hz represents the total frequency that must be divided by 15 to get to the bottom of the down-spread. Dividing 450,000 Hz by 15 steps is equal to 30,000 Hz per step. 4 Rev. 0.1

5 Going back to the original form, but putting in the numerator multiplied by the output frequency ( E11 * 100 = NUM * 100). The numerator is left-shifted as from above (0x ), and then multiplied by 100 MHz, as seen below on the right-hand side of the equation DEN = Next the NUM*100 is divided by 100 with the additional 30 khz (which is one additional step) E13 = This resulting value is equal to the numerator step change. This value is then subtracted from the numerator value as shown below, and this is assigned as the step size used in N0_FSW field E = 43,795,528 (Step Size = N0_FSTEPW). This is a 44 bit Integer number located at register 0x033B This final calculation shows the 0.45% drop. The frequency should range from 100 MHz down to MHz = 99.55MHz In order to set up the part to enable the FINC/FDEC pins and to set the appropriate step size per command, the following register settings must be inserted into the frequency plan using ClockBuilder Pro. (See the above calculation.) The other register settings are required to use the FINC/FDEC from pin control of the MCU GPIO. These additional register settings can be entered using the EVB GUI. Table 3. Register Settings Required to Control the FINC/FDEC Pins with the MCU Field Name Register Values Value N0_FSTEPW 0x033B-0x ,795,528 (0x C-44-48) 0x033B=0x48 0x033C=0x44 0x033D=0x9C 0x033E=0x02 0x033F=0x00 0x0340=0x00 N_FSTEP_MSK 0x0339[0] 0 N_FSTEP_DEN 0x033A[0] 0 N_PIBYP 0x0A04[0] 0 M_FSTEP_MSK 0x0240[0] 1 N_CLK_DIS 0x0B4A[0] 0 11 The frequency modulation is shown below in Figure 5 from an MCU toggling the FINC and FDEC pins, showing the 0.45% down-spread from 100 MHz. Rev

6 Figure 5. Screen Capture of the Output Frequency Being Stepped Down and Up Using the MCU Conclusion For designers who may require a small number of PCIe 3.0 spread spectrum compliant clocks, a straightforward approach using a Si5341 and an external controller is presented. By utilizing appropriately timed GPIO pins from an external MCU, spread spectrum clocking (SSC) can be implemented by taking advantage of the Si5341 s frequency increment/decrement control pins. The results are PCIe 3.0 compatible outputs with spread spectrum clocking. 6 Rev. 0.1

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