DEPARTMENT OF COMPUTER SCIENCE CSC132 DIGITAL SYSTEMS. Assignment 1 Boolean Algebra and Logic Gate

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1 Assignment 1 Boolean Algebra and Logic Gate uestion 1 (i) Convert the following binary number to decimal (ii) Convert the following hexadecimal number 7F2.4 to binary number. uestion 2 List the ten BCD digits with an odd parity in the leftmost position (total of five bits per digit.) Repeat with an odd-parity bit. uestion 3 Noting that 3 2 =9, formulate a simple procedure for converting base-3 numbers directly to base-9. Use the procedure to convert ( ) 3 to base 9 uestion 4 Simply the expression using boolean algebra (i) x y + xy + xy (ii) (iii) x + xy + xz + x yz [ A B( C + BD) + AB] C uestion 5 Apply DeMorgan s theorems to the following expression A + BC + D( E + F). uestion 6 Simply the following expression using tabular method. F(a,b,c) = m(0,1,3,5,7) uestion 7 Simply the following Boolean functions to minimum number of literals (input variables). F = ABC + ABD + ABC + CD + BD uestion 8 Prove the following identities algebraically A D + CD + AB = ACD + ACD + ABC + ABC + ACD uestion 9 Given the following Boolean function: F = x yz + x yz + wxy + wxy + wxy (i) Obtain the truth table of the function. (ii) Draw the logic diagram using the original Boolean expression. (iii) Simply the function to a minimum number of literals using Boolean algebra. (iv) Obtain the truth table of the function form the simplified expression and show that it is the same as the one in part (a). (v) Draw the logic diagram from the simplified expression. -1-

2 Assignment 2 Simplification of Boolean Function uestion 1 Simplify the following Boolean function to minimum number of literals (input variables) F = A uestion 2 Prove the following identity algebraically B + AC = ( A + B + C) (Hint: Double complements and DeMorgan s theorem for multiple variables are needed) uestion 3 Using DeMorgan s theorem, convert the following Boolean expression to equivalent expressions that (i) have only OR and complement operations, and show that the functions can be implemented with NOR gates only; (ii) have only AND and complement operations, and show that the functions can be implemented with NAND gates only. f = ( y + z)( x + y)( y + z) uestion 4 Simply the following expression using K-map (a) f = abc + bcd + bcd + acd + abc + abcd (b) f ( w, x, y, z) = m(3,7,11,13,14,15 ) uestion 5 Using a K-map, convert the following standard (canonical) POS expression into a minimum POS expression, a standard SOP expression, and a minimum SOP expression. ( A + B + C + D) Assignment 3 Combinational Logic uestion 1 Convert the following circuit to an equivalent circuit A B C D E F (a) using 2-input NAND gates only (b) using 2-input NOR gates only -2-

3 uestion 2 Design the circuit of a 3-bit parity generator and the circuit of a 4-bit parity checker using an odd parity bit. uestion 3 Design a combinational circuit that converts a binary number of four bits to a decimal number in BCD. Note that the BCD number is the same as the binary number as long as the input is less than 9. The binary number from 1010 to 1111 converts into BCD numbers from to uestion 4 Construct a 16 1 MUX with five 4 1 MUXs. uestion 5 A combinational circuit is specified by the following three Boolean functions: F 1 (A,B)= m (0,2) F 2 (A,B)= m (1,2 ) F 3 (A,B)= ( 0,2) Implement the circuit with a 2 to 4 line decoder and external OR gates. uestion 6 Implement the following Boolean function with a 4 1 MUX and external gates. Connect inputs A and B to the selection lines and inputs C and D to the data input lines of the MUX. F = ( A, B, C, D) = m(1,3,4,11,12,13,14,15) Assignment 4 Sequential Circuit uestion 1 Consider the trailing-edge triggered flip flops shown below. a. b. c. D S J PRE R CLR K CLR a. Show a timing diagram for. (D-flip flop) b. Show a timing diagram for (SR- flip flop) if i. there is no CLR input ii. the CLR input is as shown -3-

4 c. Show a timing diagram for (JK flip flop) if i. There is no PRE input ii. The PRE input is as shown (in addition to the CLR input) uestion 2 For the following circuit, complete the timing diagram for the state of each flip flop and the output, where shown. All flip-flops are trailing-edge triggered. D q1 q1-4-

5 uestion 3 A sequential circuit has three D flip-flops, A, B, and C, and one input, x. It is described by the following flip-flop input functions: DA= (BC +B C)x + (BC + B C )x DB=A DC=B (a) Derive the state table for the circuit. (b) Draw two state diagrams: one for x=0 and the other for x=1 uestion 4 For the following state table and state assignment, show equations for the next state 1 (t+1), 2 (t+1) and the output (Z). (Present state) (t+1) Next state Z (output) State assign. X=0 X=1 X=0 X=1 1 2 A C A 0 1 A 0 1 B B A 1 0 B 1 1 C B C 0 1 C 0 0 uestion 5 A sequential circuit has one flip-flop, ; two inputs, x and y; and one output, S. It consists of a full-adder circuit connected to a D-flip-flop, as shown in Figure 1. Derive the state table and state diagram of the sequential circuit. x FULL ADDER S y C D CP Figure 1-5-

6 uestion 6 A sequential circuit has three flip-flops, A, B, C; one input, x; and one output, y. The state diagram is shown in Figure 2. The circuit must be analyzed to ensure that it is self-correcting. (a) Use D flip-flops in the design. (b) Use JK flip-flops in the design. Figure 2 Assignment 5 Digital Arithmetic and Counter uestion 1 Perform the following operation in the 2 s complement system. Use eight bits (including the sign bit) for each number. Check your results by converting the binary back to decimal. (a) Add +19 to -24 (b) Subtract +21 from -13 (c) Add +17 to -17 (d) Subtract +16 from +17 uestion 2 Add the following decimal numbers after converting each to each to its BCD code (a) (b) (c) uestion 3 Write the truth table for a half adder (input A and B; outputs SUM and CARRY). From the truth table, design a logic circuit that will act as a half adder. uestion 4 Design a counter with T flip-flops that goes through the following binary repeated sequence: 0, 1, 3, 7, 6, 4. Show that when binary states 010 and 101 are considered as don t care conditions, the counter may not operate properly. -6-

7 uestion 5 Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6. Use JK flip-flops. uestion 6 For the following circuit, determine the sum outputs for the following cases: (a) A register= 0011(+3), B register = 1110 (-2); SUB =1, ADD=0 (b) A register= 1001(-7), B register = 0100 (+4); SUB =0, ADD=1-7-

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