PHY4635/5635 Spring Lecture 21: The Pentium Series

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1 PHY4635/5635 Spring 2009 Lecture 21: The Pentium Series

2 Architectural Improvements for the Pentium Series 64-bit data path Superscalar execution Hyperthreading Dual-independent bus architecture MMX SSE, SSE2, SSE3 3DNow! Dynamic execution: Branch prediction Dataflow analysis Speculative execution Dual-cores

4 MEM/WB=Memory decode & Write back IF=Instruction fetch ID=Instruction decode Execute

5 Base pipeline Each block is performed by separate, independent circuitry in a pipe Instruction fetch Instruction decoding ALU - execute Memory decoding Write back

6 Linear System (80x86) (sequential operation) Instruction fetch Decode Execute / error reporting Memory decoding Write back

7 Instruction-level Parallelism Each step takes the same number of clock cycles to complete While ID is decoding, may as well do the IF for the next instruction

8 Superscalar Pipelining The Pentium has 2 pipes U and V pipe

9 Hyper-threading HT fills otherwise idle time in the CPU with multiple threads. Recall, a thread is P-4 or higher BIOS, motherboard, and OS must be also support HT.

10 Dual-independent Bus Architecture DIB employed in P-Pro through P-III Xeon 2 data buses allows concurrent access to data Controls data flow between L2 cache and CPU main pipe. Can fetch data that feeds into L2 cache for processing later. L2 cache now on the main CPU chip. VERY FAST!

11 MMX Technology Employed on Pentium Pro through Pentium II and Celeron A. Multimedia extensions (or matrix math extensions, depending on whom you ask). Improves: Video compression/decompression Image manipulation Encryption I/O processing How? Large internal L1 cache 57 new instructions that employ SIMD (single instruction, multiple data). SIMD: allows the application of a single instruction on multiple pieces of data e.g. image brightness increase, treat all pixels together instead of individually. Slows down floating point processes (uses both pipes for integer only).

12 SSEx Streaming SIMD extensions (SSE). Employed on Pentium III-present day. 70 more instructions over MMX set for graphics and sound. Allows concurrent floating point execution. SSE2 adds 144 more instructions (P-4) SSE3 adds 13 more instructions to handle conplex math, graphics, video encoding, thread synchronization. All SSE employ pre-fetching. SSE useful for MPEG2 (DVD) video SSE supported in DirectX 6.1 and newer (Win98SE).

13 3DNow! AMD s alternative to SSE. AMD licensed Intel s MMX but not SSE. First introduced in K6 series before Intel released SSE. 3DNow! 21 new instructions for matrices Enhanced 3DNow! 25 more instructions (SSE and and DSP). 3DNow! Professional 51 more instructions, making it fully SSE competitive.

14 Dynamic execution Branch prediction Front-end circuitry determines from instructions in the pipeline the anticipated sequence Used for high-end mainframes Dataflow analysis Reorganizes instruction sequence to optimize superscalar execution Speculative execution Actually executes some instructions in advance, stores results in temporary registers. Available on all P6 processors: P-Pro through P-III Xeon.

15 Dual-Core HT is designed to act as 2 CPUs with one processor. Many applications do not support HT and actually slow down on HT-enabled systems. Dual-core = two CPUs on one chip. Fully parallel without HT overhead. All applications benefit. Athlon 64 X2 and the Pentium Extreme Edition / Pentium D.

16 Pentium Extreme Edition (2005) Pentium D (2005) Intel s Dual Core

17 AMD s Dual Core Ahtlon 64 X2 Dual-core Opteron Run cooler than Intel Ahtlon 64X2, 2.4Ghz, 110W Pentium Extreme, 3.2GHz, 130W Although AMD s processor run at slower clocks, HyperTransport technology makes them equal in performance.

18 In Summary P1 (1 st generation) 1978 PC-XT; 4.77MHz P2 (2 nd generation) PC-AT; 6MHz; 16MB real memory; protected mode. P3 (3 rd generation) PS/2 Model 80; 32-bit; 4GB real memory; MMU & paging; native=protected mode; 16-33MHz P4 (4 th generation) DX, bit; 4GC real memory; reduced instruction execution time (2 cycles); Internal L1 cache; enhanced coprocessor; <133MHz P5 (5 th generation) bit data bus; superscalar/risc; branch prediction; MMX/SIMD P6 (6 th generation) 1995 P5+dynamic execution; DIB; SSE (P3); etc P7 (7 th generation) GHz-3.8GHz; 125 million transistors; 1066MHz FSB; deep out-of-order instruction execution; 16KB L1 / 1MB, 256-wide L2 cache; SSE3; Multiple low-power states. P8 (8 th generation) bit registers; Itanium, Itanium 2 Celeron=Pentium with no L2 cache (but now it has more); lower CPU bus speed (but now competitive). EM64T = 64-bit extension mode. Allows concurrent 32-bit and 64-bit processes.

Generations of the computer. processors.

Generations of the computer. processors. . Piotr Gwizdała 1 Contents 1 st Generation 2 nd Generation 3 rd Generation 4 th Generation 5 th Generation 6 th Generation 7 th Generation 8 th Generation Dual Core generation Improves and actualizations