VIRTUAL MEMORY. Prof. Cristina Silvano Politecnico di Milano

Transcription

1 VIRTUAL MEMORY Prof. Cristina Silvano Politecnico di Milano

2 Overview What s Virtual Memory? 2 3 Memory Management Unit (MMU) Translation Look Aside Buffer (TLB)

3 Virtual Memory The virtual memory is a mechanism to translate virtual addresses to the physical addresses (memory mapping) Virtual memory practically treats memory as a cache for the disk, where blocks in this cache are called pages Virtual Addresses Virtual addresses Address translation Physical Addresses Physical addresses Page fault Disk addresses

4 From virtual to physical address The concept of virtual memory has mainly been introduced to separate the addressing space of the processor and the actual size of the physical memory Virtual address Virtual page number Page offset Translation 20 bit 2 bit bit Physical page number Page offset Physical address

5 Page Table The translation mechanism between virtual pages to physical pages is based on a Page Table associated to each process: Each process needs its own page table! Page Table for each process is located in physical memory Page Table maps virtual page numbers (VPNs) to physical page numbers (PPNs) In principle, the Page Table should contain an entry for each virtual page of the process The VPN is used as index of the Page Table

6 Page Table The Page Table maps virtual page numbers to physical pages Page table register Virtual address Virtual page number Page offset 20 2 Valid Physical page number Page table If 0 then page is not present in memory Physical page number Page offset Physical address

7 Pages out of memory: validity bit The Page Table requires a validity bit to distinguish between pages in memory and pages in disk storage Virtual page Virtual page number Valid Page table Physical page or disk address Physical memory Disk storage Page fault

8 VM and Disk: Page replacement policy Set of all pages in Memory Head pointer Place pages on free list if used bit is still clear. Schedule pages with dirty bit set to be written to disk. Dirty bit: page written. Used bit: set to on any reference Tail pointer: Clear the used bit in the page table Architect s role: support setting dirty and used bits dirty used Page Table... Freelist Free Pages

9 Memory Management Unit (MMU) Basic idea: to add a cache to speed up the address translation Virtual page number Valid Tag TLB Physical page address 0 Physical memory Page table Physical page Valid or disk address Disk storage

10 Translation Look Aside (TLB) Buffers Translation Look Aside Buffers (TLB) Cache on translations hit VA PA miss CPU TLB Cache Main Memory Translation with a TLB miss Translation hit TLBs are: data Small typically not more than entries Typically, fully associative

11 What Actually Happens on a TLB Miss? Hardware traversed page tables: On TLB miss, hardware in MMU looks at current page table to fill TLB (may walk multiple levels) If PTE valid, hardware fills TLB and processor never knows If PTE marked as invalid, causes Page Fault, after which kernel decides what to do afterwards Software traversed page tables (like MIPS) On TLB miss, processor receives TLB fault Kernel traverses page table to find PTE If PTE valid, fills TLB and returns from fault If PTE marked as invalid, internally calls Page Fault handler Most chip sets provide hardware traversal Modern operating systems tend to have more TLB faults since they use translation for many things Examples: shared segments user level portions of an operating system

12 TLB and Cache Virtual address Virtual page number Page offset 2 TLB TLB hit Valid Dirty Tag Physical page number 20 Physical page number Page offset Physical address Physical address tag Cache index Byte offset Valid Tag Data Cache 32 Cache hit Data

13 Reducing translation time further As described, TLB lookup is in serial with cache lookup: Virtual Address V page no. 0 offset TLB Lookup V Access Rights PA P page no. Physical Address offset 0 Machines with TLBs can go one step further: they can overlap TLB lookup with cache access. It works because page offset is available early

14 Avoiding address translation during indexing of the cache to reduce hit time Cache must cope with translation of virtual address from the processor to the physical address to access the memory Basic idea: to use Page Offset (the part of the address which is identical in the virtual and physical address) as Cache Index Access to physical tags in cache can start immediately and in parallel with address translation so as to speed up the comparison of physical tags of cache Cache virtually indexed and physically tagged Main drawback: the size of the page limits the size for direct mapped caches (solution: higher associativity) Another option: Virtual Caches (Virtually Addressed Caches) Tags in cache are virtual addresses Translation only happens on cache misses

15 Overlapping TLB & Cache Access Virtual address Virtual page number Page offset 2 TLB TLB hit Valid Dirty Tag Physical page number 20 Physical page number Page offset Physical address Physical address tag Cache index Physical address tag Cache Index 2 2 Byte offset Valid Tag Data Cache 32 Cache hit Data

16 Overlapping TLB & Cache Access Here is how this might work with a 4K cache: 32 TLB assoc lookup index 4K Cache K Hit/ Miss 20 page # 0 2 disp 00 4 bytes FN = FN Data Hit/ Miss What if cache size is increased to 8KB? Overlap not complete Need to do something else

17 Problems With Overlapped TLB Access Overlapped access requires address bits used to index into cache do not change as result translation This usually limits things to small caches, large page sizes, or high n way set associative caches if you want a large cache Example: suppose everything the same except that the cache is increased to 8 K bytes instead of 4 K: virt page # 2 cache index disp Solutions: go to 8K byte page sizes; 0 go to 2 way set associative cache; or SW guarantee VA[3]=PA[3] This bit is changed by VA translation, but is needed for cache lookup way set assoc cache K

18 Three Advantages of Virtual Memory Translation: Program can be given consistent view of memory, even though physical memory is scrambled Makes multithreading reasonable (now used a lot!) Only the most important part of program ( Working Set ) must be in physical memory. Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later. Protection: Different threads (or processes) protected from each other. Different pages can be given special behavior (Read Only, Invisible to user programs, etc). Kernel data protected from User programs Very important for protection from malicious programs Sharing: Can map same physical page to multiple users ( Shared memory )

19 PUTTING ALL TOGETHER

20 ARM Cortex A8: Data Caches and Data TLB Next page: The virtual address, physical address, indexes, tags, and data blocks for the ARM Cortex A8 data caches and data TLB. Since the instruction and data hierarchies are symmetric, we show only one. The TLB (instruction or data) is fully associative with 32 entries. The L cache is four way set associative with 64 byte blocks and 32 KB capacity. The L2 cache is eight way set associative with 64 byte blocks and MB capacity. This figure doesn t show the valid bits and protection bits for the caches and TLB, nor the use of the way prediction bits that would dictate the predicted bank of the L cache.

21 ARM Cortex A8: Data Caches and Data TLB Copyright 20, Elsevier Inc. All rights Reserved.

22 Intel Core i7: Memory Hierarchy Next figure: The Intel Core i7 memory hierarchy and the steps in both instruction and data access. We show only reads for data. Writes are similar, in that they begin with a read (since caches are write back). Misses are handled by simply placing the data in a write buffer, since the L cache is not write allocated.

23 Intel i7: Memory Hierarchy Copyright 20, Elsevier Inc. All rights Reserved. Copyright 20, Elsevier Inc. All rights Reserved.