Lecture 18: Feedback

Transcription

1 Lecture 8: Feedback Gu-Yeon We Dvson o Engneerng and ppled Scences Harvard Unversty guyeon@eecs.harvard.edu We

2 Overvew eadng S&S: Chapter 8.~8.8 S&S: ppendx B (Two-Port Network Parameters) Background Negatve eedback or amplers was nvented n 97 by Harold Black to stablze the gan and correct the dstorton o amplers used n longdstance telephone networks. Negatve eedback (as well as postve eedback) s wdely used n analog crcuts today. n act, we used negatve eedback when we constructed op amps wth gan set (xed) usng resstors. Throughout the next lecture, we wll nvestgate the general theory o eedback and look at our basc eedback topologes or our types o ampler topologes. We wll return to concepts o eedback covered n Chapter 8 o S&S ater takng nvestgatng how to buld sngle- and twostage Op amps. We wll return to materal n Chapter 8 to study stablty o amplers, and see how compensaton can be utlzed. S&S has several examples o crcuts wth eedback usng BJTs. These lecture notes gve MOS crcut examples (many rom azav s textbook).

3 General Feedback Structure Let s start wth the basc structure o a eedback ampler. To make t general, the gure shows sgnal low as opposed to voltages or currents (.e., sgnals can be ether current or voltage). Source x s Σ x x o Load x The open-loop ampler has gan x o *x Output s ed back through a eedback network whch produces a sample (x ) o the output (x o ) x x o Where s called the eedback actor The nput to the ampler s x x s x (the subtracton makes eedback negatve) mplct to the above analyss s that nether the eedback block nor the load aect the ampler s gan (). Ths not generally true and so we wll later see how to deal wth t. The overall gan (closed-loop gan) can be solved to be: xo x + s called the loop gan and + s called the amount o eedback s 3

4 Fndng Loop Gan Generally, we can nd the loop gan wth the ollowng steps: Break the eedback loop anywhere (at the output n the ex. below) Zero out the nput sgnal x s pply a test sgnal to the nput o the eedback crcut Solve or the resultng sgnal x o at the output x o s a voltage sgnal, x tst s a voltage and measure the open-crcut voltage x o s a current sgnal, x tst s a current and measure the short-crcut current x s 0 Σ x x x x tst 0 x x o x x x tst x x o loop gan x x o tst x tst The negatve sgn comes rom the act that we are apply negatve eedback 4

5 Negatve Feedback Propertes Negatve eedback takes a sample o the output sgnal and apples t to the nput to get several desrable propertes. n amplers, negatve eedback can be appled to get the ollowng propertes Desenstzed gan gan less senstve to crcut component varatons educe nonlnear dstorton output proportonal to nput (constant gan ndependent o sgnal level) educe eect o nose Control nput and output mpedances by applyng approprate eedback topologes Extend bandwdth o ampler ll o these propertes can be acheved by tradng o gan Let s nvestgate a couple o these propertes n a lttle more detal usng the general structure descrbed n the prevous slde 5

6 Gan Desenstvty Feedback can be used to desenstze the closed-loop gan to varatons n the basc ampler. Let s see how. ssume s constant. Takng derentals o the closed-loop gan equaton gves + Take dervatve o d d + ( ) both sdes Dvde by d d + d ( + ) + Ths result shows the eects o varatons n on s mtgated by the eedback amount. + s also called the desenstvty amount We wll see through examples that eedback also aects the nput and resstance o the ampler (ncreases and decreases o by + actor) 6

7 Bandwdth Extenson We ve mentoned several tmes n the past that we can trade gan or bandwdth. Fnally, we see how to do so wth eedback Consder an ampler wth a hgh-requency response characterzed by a sngle pole and the expresson: M () s + s ω pply negatve eedback and the resultng closed-loop gan s: () s + ( s) () s Notce that the mdband gan reduces by (+ M ) whle the 3-dB roll-o requency ncreases by (+ M ) H M + s ω ( + M ) ( + ) H M 7

8 Basc Feedback Topologes Dependng on the nput sgnal (voltage or current) to be ampled and orm o the output (voltage or current), amplers can be classed nto our categores. Dependng on the ampler category, one o our types o eedback structures should be used (seres-shunt, seres-seres, shuntshunt, or shunt-seres) oltage ampler voltage-controlled voltage source equres hgh nput mpedance, low output mpedance Use seres-shunt eedback (voltage-voltage eedback) Current ampler current-controlled current source Use shunt-seres eedback (current-current eedback) Transconductance ampler voltage-controlled current source Use seres-seres eedback (current-voltage eedback) Transmpedance ampler current-controlled voltage source Use shunt-shunt eedback (voltage-current eedback) seres-shunt shunt-seres shunt-shunt seres-seres 8

9 Examples o the Four Types o mplers OUT OUT D D v OUT v OUT v N b v N b N N oltage mp Transmpedance mp Transconductance mp Current mp Shown above are smple examples o the our types o amplers. Oten, these amplers alone do not have good perormance (hgh output mpedance, low gan, etc.) and are augmented by addtonal ampler stages (see below) or derent conguratons (e.g., cascodng). OUT OUT D D D D v N v OUT b v OUT v N b N N lower Z out lower Z out hgher gan hgher gan 9

10 Sense and eturn Mechansms ddng a eedback loop conssts o sensng the output sgnal and returnng (a racton) o the result to the summng node at the nput. Gven the nputs and outputs can be ether voltages or currents, there are our types o eedback: voltage-voltage, voltage-current, current-voltage, and current-current where the rst part denotes the quantty sensed at the output and the second denotes the type o sgnal returned Examples o sensng voltage and current: out out v out voltmeter L sense L current meter v sense 0

11 Sense and eturn Cont d Here are some crcut examples o sensng and returnng voltages and currents: v n v out v n v n v v out v out v out v out v out v n v n v oltage return v v v n Current return n F n F

12 Seres-Shunt Feedback mpler (oltage-oltage Feedback) Samples the output voltage and returns a eedback voltage sgnal deal eedback network has nnte nput mpedance and zero output resstance Fnd the closed-loop gan and nput resstance s o ( s o ) o s + s s s o + ( + ) The output resstance can be ound by applyng a test voltage to the output o o + So, ncreases nput resstance and reduces output resstance makes ampler closer to deal CS

13 Crcut Example Feedback can be constructed out o capactors Fnd the open-loop gan t low requency, cap loads neglgble Break eedback and zero out nput to eedback v n M 3 M M M 4 C C v out ssume s at some DC bas equal to the DC value o v n g r r m ( ) o o4 Fnd the loop gan, closed-loop gan, and closed-loop out C vo gm ( ro ro 4 ) vtst C + C Note Note correcton: correcton: v v o and o and not not v v out, closed v v o tst + + C C C + C + C r C + C o g m gm C + C ( r r ) ( r r ) r g o4 m o o g m ( r r ) ( r r ) m o o4 o4 o o4 o4 + C C + C g M 3 M 4 M M Crcut to solve loop gan v o C C tst v tst 3

14 Seres-Seres Feedback mpler (Current-oltage FB) For a transconductance ampler (voltage nput, current output), we must apply the approprate eedback crcut Sense the output current and eedback a voltage sgnal. So, the eedback current s a transmpedance block that converts the current sgnal nto a voltage. o o (also called G m ) + s To solve or the loop gan: Break the eedback, short out the break n the current sense and applyng a test current out Loop Gan G tst To solve or and o + s + o + ( + ) pply a test voltage tst across O and O m G m out tst ZL o ( ) ( + ) tst tst o tst tst o tst tst tst ( + ) o 4

15 Crcut Example Source degeneraton (wth ) s a orm o current-voltage FB oltage across the resstor s the eedback voltage F subtracts rom n to reduce gs o the nmos out Wthout the eedback, out /v n g m g m s the eedback crcut that senses the output current and subtracts a voltage rom the nput n F out F out out g m ( + g ) v out n v m gs F g m ( v ) g m n v n out g + + g m m F F v n v gs g m v gs r o out 5

16 Shunt-Shunt Feedback mpler (oltage-current FB) When voltage-current FB s appled to a transmpedance ampler, output voltage s sensed and current s subtracted rom the nput The gan stage has some resstance The eedback stage s a tranconductor o o s + + o + s o nput and output resstances ( and o ) ollow the same orm as beore based on values or and + o ( ) + o ( ) 6

17 Crcut Example Transmpedance gan stage s through M (a common-base ampler) and eedback s thru the capactor dvder and M (transconductor). Solve or,, and. v gs s whatever voltage necessary or n C b D M out v out n D n n D C M n Loop gan s ound by breakng loop and applyng tst C vf C + C gmvf vout - D vout v tst v tst g m D C v ( C + C ) tst v tst g m D C C + C Crcut to nd v gs n g m v gs D v out Small-sgnal crcut to solve or D Closed-loop gan s just v out n + + g m D C D C + C tst C b M M out C 7

18 Shunt-Seres Feedback mpler (Current-Current FB) current-current FB crcut s used or current amplers For the crcut nput resstance should be low and output resstance be hgh crcut example s shown S and consttute the FB crcut D out S should be small and large The same steps can be taken to solve or,,,, and o emember that both and crcuts are current controlled current sources n S 8

19 Eects o Loadng So ar, we have assumed that the eedback crcut does not load the eedorward (openloop) ampler at the nput or the output. n realty, ths s not the case. Loadng may not be neglgble and complcate analyss. n order to properly model loadng eects, we should rst revew models o two-port networks. The eedback crcut can be consdered to be a two-port network that senses and produces currents or voltages. The ollowng are our types o lnear two-port networks usng Z, Y, or H or G (mpedance, admttance, or hybrd) models Z Z Z Z Z Z + Z + Z Y Y Y Y Y + Y Y + Y H G H H H H H + H + H G G G G G + G + G 9

20 Loadng n Seres-Shunt (oltage-oltage) FB Whch s the best model to use? deally, want nnte nput resstance and zero output resstance G-model G contrbuton to out s small compared to amplcaton so gnore G current source reverse transmsson thru the FB crcut s made purposely small Computer the closed-loop gan Zn e ( n G out ) Z + G out ( G ) n out n Z n n the lmt (deal case), /G and G 0 then equaton reduces to Zn + G G G + Z out out n n n e Z n Zn G Zn + G G + Zout Zn G + G Z + G G + Z n e G out G out G ~0 Z out G out + + G We can retan ths orm or closed-loop gan by solvng or the open-loop gan that takes loadng nto account 0

21 Open-Loop Gan wth Loadng For the prevous example, proper method or ncludng loadng to calculate the open-loop gan s shown n Conceptually, the approach s n e Z n e Z out out n out G G G /G add load both sdes (nput and output) wth the eedback crcut short the nput o the crcut that loads the nput o the ampler leave the output unconnected or the crcut that loads the output o the ampler Calculate the open-loop gan G and G 0 0

22 Summary o FB Types and -Port Models There s an approprate -port model to use or each o the eedback types (n table) conceptual summary o solvng or the open-loop gan wth eedback loadng eects are as ollows ttach separate eedback crcuts to both nput and output (ndvdually) as t would normally be connected For the eedback crcut attached to the nput (o the ampler), zero out the other sde o the eedback crcut (nput port) nput port to crcut s a voltage, attach to a 0-olt source nput port to crcut s a current, attach to a 0-mp source For the eedback crcut attached to the output (o the ampler), leave the other sde dsconnected output port o crcut s a voltage, leave as open crcut output port o crcut s a current, short output to ground Feedback Type Seres-Shunt (oltage-oltage) Seres-Seres (Current-oltage) Shunt-Shunt (oltage-current) Shunt-Seres (Current-Current) -port Model G Model Z Model Y Model H Model Let s look at some examples o how to break the eedback and determne the open-loop gan that ncludes the eects o eedback.

23 Loadng n Seres-Shunt (oltage-oltage) FB Example n out n open G /G D n crcut out n D M M open S D S S D The open-loop gan (wth loadng) can be calculated to be + { g [ ( )]} open D open loop m D n F S + gm F S 3

24 Loadng n Seres-Seres (Current-oltage) FB Example out / e n e out n open Z Z D D n out n M M M 3 open D D S crcut S S S3 S3 S3 The open-loop gan (transconductance) can be solved to be: open loop open n D g m D ( F + S 3 ) S + gm ( F + S) S 3 + gm3 4

25 Loadng n Shunt-Shunt (oltage-current) FB Example out / e n e out n open /Y /Y crcut D D F out out n S n S The open-loop gan (transmpedance) can be solved to be: open open loop gm S F D n ( )( ) F 5

26 Loadng n Shunt-Seres (Current-Current) FB Example out / e n e out n open /H H D out D open n n crcut S S S The open-loop (current) gan be solved to be: open loop open n g m ( + ) S F D F + S g m 6

27 Next Tme eadng S&S Chapter 0.7~0.8 What to look orward to We wll sht gears a lttle bt and look at a ew approaches or buldng CMOS Operatonal mplers. We wll begn wth sngle-stage op amps and the proceed to two-stage op amps and some o ther advantages and dsadvantages. The nvestgaton o op amp desgns wth multple poles orces us to then deal wth stablty ssues. The nal lecture wll cover stablty and compensaton n ampler desgn. eadng or the nal lecture s S&S Chapter 8.8~8.. 7